[go: up one dir, main page]

TW200512867A - Methods of simultaneously fabricating isolation structures having varying dimensions - Google Patents

Methods of simultaneously fabricating isolation structures having varying dimensions

Info

Publication number
TW200512867A
TW200512867A TW092126944A TW92126944A TW200512867A TW 200512867 A TW200512867 A TW 200512867A TW 092126944 A TW092126944 A TW 092126944A TW 92126944 A TW92126944 A TW 92126944A TW 200512867 A TW200512867 A TW 200512867A
Authority
TW
Taiwan
Prior art keywords
region
hard mask
isolation structures
type features
trench
Prior art date
Application number
TW092126944A
Other languages
Chinese (zh)
Other versions
TWI239590B (en
Inventor
Hsu-Sheng Yu
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW92126944A priority Critical patent/TWI239590B/en
Publication of TW200512867A publication Critical patent/TW200512867A/en
Application granted granted Critical
Publication of TWI239590B publication Critical patent/TWI239590B/en

Links

Landscapes

  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Shallow trench isolation structures are simultaneously fabricated such that ones in a cell region have first-type features and others in a periphery region have second-type features. The first-type features can be rounded edges or can be first depths and widths, and the second-type features can be unrounded edges or can be second depths and widths which are different from the first depths and widths. The method includes forming patterned photoresist over a hard mask over portion of a cell and a periphery region, and removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, followed by the trench in the periphery region being deepened while a trench in the cell region is formed.
TW92126944A 2003-09-30 2003-09-30 Methods of simultaneously fabricating shallow trench isolation structures having varying dimensions and structure thereof TWI239590B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92126944A TWI239590B (en) 2003-09-30 2003-09-30 Methods of simultaneously fabricating shallow trench isolation structures having varying dimensions and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92126944A TWI239590B (en) 2003-09-30 2003-09-30 Methods of simultaneously fabricating shallow trench isolation structures having varying dimensions and structure thereof

Publications (2)

Publication Number Publication Date
TW200512867A true TW200512867A (en) 2005-04-01
TWI239590B TWI239590B (en) 2005-09-11

Family

ID=37007479

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92126944A TWI239590B (en) 2003-09-30 2003-09-30 Methods of simultaneously fabricating shallow trench isolation structures having varying dimensions and structure thereof

Country Status (1)

Country Link
TW (1) TWI239590B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI869750B (en) * 2022-01-24 2025-01-11 美商格芯（美國）集成電路科技有限公司 Trench isolation having three portions with different materials, and ldmos fet including same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI869750B (en) * 2022-01-24 2025-01-11 美商格芯（美國）集成電路科技有限公司 Trench isolation having three portions with different materials, and ldmos fet including same
US12295161B2 (en) 2022-01-24 2025-05-06 Globalfoundries U.S. Inc. Trench isolation having three portions with different materials, and LDMOS FET including same

Also Published As

Publication number Publication date
TWI239590B (en) 2005-09-11

Similar Documents

Publication Publication Date Title
TW200620456A (en) Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches
TWI388057B (en) Semiconductor component with multiple channels and manufacturing method thereof
EP1933375A3 (en) Methods for Recess Etching
US7514312B2 (en) Method of manufacturing semiconductor device
TWI264766B (en) Method for fabricating recessed gate structure
TW200713420A (en) Method of fabricating shallow trench isolation structure
US9508587B2 (en) Formation of isolation surrounding well implantation
TW200512867A (en) Methods of simultaneously fabricating isolation structures having varying dimensions
TW200501315A (en) Method of forming capacitors having geometric deep trench
TW200710965A (en) Method of forming align key in well structure formation process and method of forming element isolation structure using the align key
WO2004071153A8 (en) Method of forming sub-micron-size structures over a substrate
WO2007127197A3 (en) Mask structure for manufacture of trench type semiconductor device
TW200415719A (en) Method of planarizing a semiconductor die
TW200518259A (en) Method of fabricating shallow isolation structures and trenches thereof
US7691718B2 (en) Dual layer hard mask for block salicide poly resistor (BSR) patterning
US20180197858A1 (en) Structure and method for equal substrate to channel height between n and p fin-fets
TW200644068A (en) Manufacturing method for gate dielectric layer
KR100739246B1 (en) Source / drain region formation method of semiconductor device
TW200715478A (en) Method of fabricating a bottle-shaped trench
KR20110048166A (en) Manufacturing method of LCD drive element
TW200618315A (en) Methods of forming gate and flash having thereof
KR970053418A (en) Semiconductor Device Separation Method
TW200746311A (en) Selective removal of a silicon oxide layer
KR960039275A (en) Device Separation Method of Semiconductor Device
TW200744152A (en) Method for forming semiconductor shallow trench isolation

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent