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TW200509376A - Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card - Google Patents

Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card

Info

Publication number
TW200509376A
TW200509376A TW093114032A TW93114032A TW200509376A TW 200509376 A TW200509376 A TW 200509376A TW 093114032 A TW093114032 A TW 093114032A TW 93114032 A TW93114032 A TW 93114032A TW 200509376 A TW200509376 A TW 200509376A
Authority
TW
Taiwan
Prior art keywords
gate electrode
retaining portion
charge retaining
semiconductor
channel region
Prior art date
Application number
TW093114032A
Other languages
Chinese (zh)
Other versions
TWI248201B (en
Inventor
Hiroshi Iwata
Takayuki Ogura
Akihide Shibata
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2003141031A external-priority patent/JP2004343014A/en
Priority claimed from JP2003142120A external-priority patent/JP4620334B2/en
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200509376A publication Critical patent/TW200509376A/en
Application granted granted Critical
Publication of TWI248201B publication Critical patent/TWI248201B/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A semiconductor memory device including memory cells, each memory cell including: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region located below the gate electrode; a pair of source and drain regions arranged on opposite sides of the channel region, the source and drain regions having a conductive type opposite to that of the channel region; and memory functional units located on opposite sides, respectively, of the gate electrode, each memory functional unit including a charge retaining portion and an anti-dissipation insulator, the charge retaining portion being made of a material serving to store charges, the anti-dissipation insulator serving to prevent the stored charges from being dissipated by separating the charge retaining portion from both the gate electrode and the substrate, wherein a distance between a side wall of the gate electrode and a side of the charge retaining portion facing each other (T2) is adapted to differ from a distance between a bottom of the charge retaining portion and a surface of the substrate (T1).
TW093114032A 2003-05-19 2004-05-19 Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card TWI248201B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003141031A JP2004343014A (en) 2003-05-19 2003-05-19 Semiconductor storage device, semiconductor device, manufacturing method thereof, portable electronic device, and IC card
JP2003142120A JP4620334B2 (en) 2003-05-20 2003-05-20 Semiconductor memory device, semiconductor device, portable electronic device including them, and IC card

Publications (2)

Publication Number Publication Date
TW200509376A true TW200509376A (en) 2005-03-01
TWI248201B TWI248201B (en) 2006-01-21

Family

ID=37378167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093114032A TWI248201B (en) 2003-05-19 2004-05-19 Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card

Country Status (2)

Country Link
KR (1) KR100622414B1 (en)
TW (1) TWI248201B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7972924B2 (en) 2007-10-02 2011-07-05 Nanya Technology Corp. Method for manufacturing a memory

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745400B1 (en) * 2006-03-08 2007-08-02 삼성전자주식회사 Gate structure and method for forming same, nonvolatile memory device and method for manufacturing same
KR100784082B1 (en) * 2006-06-29 2007-12-10 주식회사 하이닉스반도체 Semiconductor memory device and manufacturing method thereof
KR100803690B1 (en) * 2006-08-10 2008-02-20 삼성전자주식회사 Electro-mechanical nonvolatile memory device and method of manufacturing the same.
KR100757323B1 (en) * 2006-09-29 2007-09-11 삼성전자주식회사 Charge trap type nonvolatile memory device and manufacturing method thereof
CN119495561B (en) * 2023-08-16 2025-09-23 浙江创芯集成电路有限公司 Method for forming semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7972924B2 (en) 2007-10-02 2011-07-05 Nanya Technology Corp. Method for manufacturing a memory

Also Published As

Publication number Publication date
KR20040101002A (en) 2004-12-02
KR100622414B1 (en) 2006-09-19
TWI248201B (en) 2006-01-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees