TW200422930A - Parallel method of flash memory - Google Patents

Abstract

A parallel method of flash memory is provided. It utilizes multiple independent data buses to move the data in the flash memory. The action principle is that the manager will use multiple page as a unit to take read/write action on flash memory when reading/writing many blocks. Through adopting parallel usage and inter-leave structures, the data movement at the same time period increases several times. The mother-child concept is applied cooperatively, that is, one logic site is owned by two entities, so the manager doesn't need to take move and erase actions repetitively on the flash memory during data writing. Hence the flash memory life is extended and the data write speed is increased. Besides, through the copy-back command, the busy state wait is reduced, so the data movement time is effectively lowered.

Description

200422930 V. Description of the invention Cl) [Technical field to which the invention belongs] The present invention is a method for using parallel dual-track of flash memory, especially a method for processing and transferring data in flash memory. Under the staggered execution architecture, the data that the 'manager can handle and process in flash memory at the same time will be several times that of the conventional flash memory management architecture. The invention can reduce the speed Flash memory data transfer time and reduce waiting time for busy status. ~ [Prior art] Reasonable handling, IE 1 6. There are degrees, and it descends, flashes quickly, and the physical memory of the busy body understands to write Γ 0. The action is a unit, and the current speed is not Ε Ε 1 6 6 Μ limit, the low-speed memory secondary state, the physical characteristics will be relatively dynamic, and not managed by one • The tribute system on the j back is fast, for example 3 9 4 is 8 0 B s, but because This makes the storage side because, when the flash will enter the busy device, the flash memory will be used to complete the device's' unless the flash block's data is made, the flash memory method will use the "block as the unit; in the data The copying process of USBOMb is plastic and waits for the state of the fast memory. At the same time, the speed is no memory and all memory is changed to 0 ". Therefore, in the shell, 2 · 〇 is s, the ID flash memory flash memory is written and its Wait until the quick method is improved; Γ 1 J, which erases, can turn the data into "1". It is also managed by the host.

Page 4 The E interface is used for body devices to process data. The flash time is very fast. The memory is based on the flash action, and the fast flash is controlled by "Ί 丄 j". After a long time leaving the tongue Ji Yi flash memory becomes more of the block of division

200422930 ------ 5. Description of the invention (2) File configuration table of the new flash memory. In the case, the data on the flash memory-the time is all-some small files, the flash memory has to be constantly Extraction-^ Process the data of several pages of blocks, move the data in the old block to the new block j 2 and continue to erase blocks. In addition, based on the flash two ghosts, and constantly The erasing action of the old flash memory exceeds the physical characteristics and damage to the internal memory, so it will easily cause the flash memory to erase the flash memory later. , A ° Brother's life of the memory, you must reduce the order of flash memory Back to increase speed, because β-day itopy is constantly moved, making the data in the memory of flash memory ^ flash memory < Data (R ead D at need to continuously read D "a) to the flash memory, causing the data ... " e Copy & R to the flash memory to enter a busy state, when the body The data will not be read out, but: after the C k 2 instruction, the flash memory, and then just the W " te instruction in the register in the flash memory, A 5 memory, and under the two body ... The data in the ack memory is written into the flash memory 3, the second body: J will be stored in the internal temporarily to read the data and then write to the "time to come ;; ^ the time of the entire action please ^ shown in Figure -A, It is the block 3 of the page used to be used for block 0. The wiper is going to write two pens. The manager first processes the first page: > First write what Pei wants to do ', please refer to page 2, page 5, 200422930 V. Description of the invention (3) _ Block 3, about the palace man & @ page To go to the block, please refer to $ 第 =: the data is written to the relatively new block. The data of the new block is filled into the page of the new block ^, which means that the person who has used the management branch will use the remaining pages in the second old block. Block ::: 4, at this time, the manager will not continue to write the material to the next page block immediately; Go to the system block, wait until all the page blocks on the right & times ^ are moved from the old block to the new complete 0 π I ^ Ϊ After writing, then the remaining page blocks; = = [的Blocks go, please refer to Figure-F: So, Ϊ = 2 blocks, then erase the old blocks, move to the new blocks, and keep 2 = the old £ blocks The memory failure rate will be very high, so how to mention it; you can 'flash the flash = degree and reduce the erasing action of the flash memory, yes; = limited' because there are branches::; C 2 instruction in The management can be divided into four block planes (P 1 ane). The flash memory of ck can only accept the command of C0Py Back and the order of the block plane blocks is configured. Block faces are: 4 '8 ... 1020 block, also: The block No. 0 of the block is the "+ 〇 (0" $ 255) block block "address block is the first, 5, 9 · · block of all magnetic blocks Included in Ghost Face 1, that is, all "physical" addresses are 4η ΐ〇2ΐ blocks,

丄 (0 ^ η $ 2 5 R Page 6 200422930 V. Description of the Invention (4)), 10 ·· 4 η + 2 (Blocks are all and all blocks, such as the first 0 magnetic blocks are all the first in the flash memory. Therefore, it is necessary to divide it into four in order to accept C. [Summary of the Invention, therefore, the issue of 'sends through multiple tests, without processing speed, (Para the present invention Para 1 independent # 说 其 运动 Originally uses the blocks included in the multiple page area 2 • Block 1 02 2 (that is, 0′n $ 255) The 3rd, 7th, and 11th “physical” address is 4 η + In this case, for the blocks contained in the 0th magnetic zone of the block, the blocks in the management memory are actually magnetic zone 0, magnetic 4 η + 0 (0, 4, 8 Copy Back Block Plan (P 1 ane) 〇 y Back's instructions] It is clear that people have made assessments and considerations of the above-mentioned technologies, and engaged in trial making and modification to reduce the time to move data. 1 1 e 1 ) The method of use is a kind of flash memory 1 e 1) The method of use, the material bus is used to read the flash memory The block is the unit, and its flash is the second of all magnetic regions, 6 is all "physical" addresses are included in the block 'block surface 3 • ·· 1 0 2 3 block, 3C〇 ^ n ^ 255 ) The allocation management is different from the past. The non-flash memory actually contains the zone 0, zone 2 and zone 3 of the 0th magnetic zone. • · 1 0 2 0) Block _ flash memory Management is all, and ordering in the same area is a big limitation. The lack is to collect relevant information. The accumulated patents in the industry that have accumulated this industry for many years have led to such improvements in flash memory. Double track (_ The main purpose is to use Donuti to transfer data. When writing multiple sections, manage t memory to read or write. # 200422930 V. Description of the invention (5). Parallel dual-use method plus interleaved execution (i: = two ave) architecture under the 'utilization of more than one flash & two μ + s principle, the use of flash memory is interleaved to reduce etc. # 忙 忧 的Time 'prolongs the life of the QA memory, and :: The speed of writing data in the flash memory of the second juice: The smoothness of the increase, so that the manager at the same time will be shaken by two entities. The logical position is the same as the price. The manager will define the "physical block" corresponding to this logical block, and the manager will then from the spare logical area will be consistent with the logical block of the parent area. If the host side wants to write two to The first block to "1" data, when the data == ϊν blocks starting to fill the page block to the child block: instead of immediately leaving the parent block remaining a this age θ ^ to the next time When the host side wants to write data = 疋 Will continue to write from the previous address? If yes; Find a new one to do. F is, Ji Rugong "l come, and continue to write blocks directly from the sub-block to the parent area-come 'when the data is written, the manager does not keep " = Second, life expectancy, and flash memory can be improved = New c 〇P increase or decrease with the use of flash memory?

When you are busy, when you are in the flash memory, C 〇py said two ί t J Η page 8 200422930 V. The description of the invention (6) will not read the data, but put it in the flash memory ^ ip! 3 ° k W r 1 1 e command, the flash memory will be i to ii instead of i ΐ the data in the internal register is written into the flash memory, and the entire operation time will be shorter than reading the data Rewrite the time spent ϋ :: = Parallel dual-use method of the body to manage flash !, uSm any host-side device, such as ... 丄 P CMC! 八 介 = flash drive, card reader or … / I A; 丨 A special card device can be used. In particular, I will use the parallel dual-track method of using i :::: J ::: 2 if combined with the instructions of using Flash 2 5 and using the mother and child views to manage the flash memory 7 such as: : C 0 ”B ack inconvenience caused by bottle display, and can = overcome the need to improve the conventional technology to increase the service life. The time required for the writing of the ugly shell material, and [implementation method] The understanding of the invention step, so the present invention = t, month's S and the effectiveness have been further described in detail in the preferred embodiment of the present invention: the segment and its structure, please refer to Figure A for the drawing, '俾 利 Understand completely. Construct two pieces of data to block 〇 Use the concept of parent / child to prepare two pieces of data to block; Step diagram, when the manager is accurate, please refer to the first section for the manager The data of block 3 of the pen page shown in Figure 2B, that is, the data 200422930 V. Invention Description (7) The above-mentioned pages to be written to the relative pages of blocks ~ Blocks, the master 夂 夂 -r, first follow The mother block moved to the child's tongue in May. Refer to Figure _C, which is for the management of thousands of pounds: Taxi 3 ' Write the pen data to the sub-area ”To the page area, refer to the second diagram shown in Figure D, which is the tube °°, block, page block 4, please refer to the -E 者: the second data is filled in the sub- In the month of the month, the brother J did not understand what the picture was, and moved the remaining page blocks in the parent block to the child block, and then did not continue to write data to the child block ghost, and疋 Wait for the second stroke of the flash ^^ body next to the: block, and then continue to wait until the inductive action occurs, the manager writes the new-pen line under the sub-block-one page block 5 * = 枓 Continue the ghost page block is full, only the parent area # is tied off, and completely replaced by the child block. (Flash "body I: structure: two capacity of 6 4Me ga B yte After executing the architecture: Complex ?: The block has 3 2 page blocks. When the two page blocks are formed, the block becomes the second one: The block becomes a "page block. The first page block is: 2 The first page block of flash memory, the first page block is m. The first page block of flash memory, the flute — page block is Γ flash memory. The original second page block, That is to say,-area 2? The original second page block of flash memory, also = body, and the odd number; the even-numbered page blocks of ΐ will be allocated to the first flash memory. Allocate to the second flash memory. Consider only the interleaved execution diagram, which is used to describe the situation and architecture flowchart using only two flash memories and write two or two: Take the write as an example That is, when the above segment reaches the fast memory, the first pen area will be written; 1Η page 10 200422930 V. Description of the invention (8) Write the first flash memory (the body (3 3 0)) into c 〇 nditi Re eday) 3 3 0), and 4 0), if you need to wait for the second one can immediately enable the second section to write to the first one can save a lot of time (1 0 〇) the main End (2 ^ 'write 2 2 〇〇) to judge the execution of the line execution from 0 to 〇 write from 0

K writes into a busy state ο η) tense can be used for the second transaction, the third flash memory, a flash memory, and the following read / enter execution (required to read (320 to be written ( 340 — two fast flashes, two fast flashes to the first data to the 3 3 0 state (B, the program immediately writes the material to the sector body (3 memory to go to, (the current write refers to the 2 2 0 page area) ), Even page area), even memory), and when the first flash usy does not have to wait for it to return to wait until the second flash memory is enabled, the second flash memory goes to the same method 4 0) jump out of the busy state (330), and the 3rd 0), so the process will execute the order according to the following steps, read and execute (2 1); whether the block is odd or even, the number is executed (3 1 〇); Whether the block is odd or even, the number is executed (3 3 0); read data is executed (4 1 memory to be stored (body ((3, no, just three strokes, 0) odd and odd 0)) memory read data to execute (4 1 〇) One flash memory execution (4 2 0) Two flash memory execution (4 2 0)

200422930 V. Description of the invention (9) (4 1 0) Determine whether to continue reading the data, "yes" jump back to execution (210), "no" execute (500); (4 2 0) determine whether to continue writing Data, "yes" jumps back to execution (2 2 0), ": η 〇" executes (5 0 0); (5 0 0) ends jumping out of the loop. Please refer to the fourth diagram shown in FIG. A, which is a flow chart for describing how to read two flash memories at the same time by using the parallel dual-track method of the present invention. Flash memory to read and write, so the hardware must have two separate sets of flash memory data signal buses, these two signals are connected to two flash memories_, and the manager will The two sets of data signals are used to move data to the two flash memories at the same time. To read data from the flash memories, the administrator simultaneously reads the data from the two flash memories. Then use these two sets of independent data buses to read data from the first flash memory and the second flash memory respectively, the steps are as follows: (1 0 0) the host side reads two Or two or more pieces of data to (2 1 0) and (2 2 0); (2 1 0) The manager uses the first set of data signal bus to read data from the first flash memory and executes (3 1 0); g (2 2 0) The manager uses the second set of data signal buses from the second flash Read data from the server and execute (3 2 0); (3 1 0) the first flash memory transfers data to the controller's buffer and executes (4 0 0); (3 2 0) the second Flash memory transfers data to the controller's buffer

Page 12 200422930 Description of the invention (10) _--- 4 0 〇 Christine's execution (400); transfer 2 sections of data from the buffer to (5 0 0); 丨 host side, execute (5 0 0) Check whether to continue sending data to the host. "Execute (210) and (220)," yes "(600); n 〇" execute (6 〇) to jump out of the loop. Conversely, please refer to the figure shown in the fourth B, which is used to describe the use of parallel dual-track to two flash memories at the same time = ^, if two data are to be written to the flash memory at this time, the two machines Privately write the data under the two flash memory commands, and then use the = u simultaneously

^ ^ t ^ aw it ^ f ^ ^ ^ 5.j ^ ^ ^ ^ JJ ^ ϋ Go to the first flash memory, the steps are as follows:, σ heart 1 〇0) Write two or two strokes on the host side For the above data, execute (200), 2000) ff 2 send two pieces of data to buffer 11, execute (3 1 (3 1 〇) manager] 2 〇) 'the first group > material flood number The bus moves the data to; Flash memory to write and execute (4 1 〇.) (3 2 0) Manager 4 1〇 The first cheek flash memory to write and execute (4 2 〇Flash memory transfers data to the controller's buffer

The second frequency uses the second set of data signal buses to move the data to 200422930. V. Description of the invention (11) The device executes (50 0); (4 2 0) The second flash memory transmits the data to the controller. Buffer, execute (500); (5 0 0) check whether to continue writing data to flash memory, "yes" execute (200), "no" execute (600)

Rows of blocks} Block flow moved into C will be divided into f C, e, and C will not increase U block error I, η tube breaks the new body CB area and I will be shown. And, table Z, the body must read e on the memory, the following device 1},} to C} memory need to do t memory body flash memory ae e} area k memory body i tube flash memory temp cn table no magnetic C flash capital memory Γ into the r body after the short note, come to ob 0, the short note made by the w flash head e real z} za four 1 in the head flash C will replace the fast finger t cecp has B, Fast material will be a pair of body η body area g area C body C} body pairing, Xindang} memory 1 memory a magnetic block memory block e memory, d is recorded with P | Breaking the writing made 3 flashes, 7 flashes of CI pages, flashes a, and flashes e faster than Γ. Fast block use | Fast 4P is going to be} If R is rising in ο circle,} area 2C of I needs a, raise k and put m back to page 1 and put the so block on t to make C is e to clear a In the bit / el- ^ region, the storage mechanism a moves to a and M. At the moment, kt has the page management D. Β, 3 said that the ik real cy area is in the} state h Ob s C Ob magnetic 2 is obtained by the da shape yy read S ο yo 1M 3 yo, so at 1PP material a 6 h 1 官 官 B 4 Every time there is ea busy ο ο poor 1 (PB of C6, including Cheng Dong RD into CC will be F

Page 14 200422930 V. Description of the invention (12) f e r), and then just need to put Co p y on the flash memory

Back Write command, the flash memory will write the data that has been stored in the internal register to the flash memory, and the time to complete the entire action will be longer than reading and writing the data. The time is short. Since the Flash memory of Co pypy ack will be divided into four blocks, the flash memory with a capacity of 64 Mega (10th power of 10) ytes or above only supports Co pypy B. The ack command uses two 64 Mbytes of flash memory as an example. Please refer to the fifth figure A, which describes the allocation of 1_ area page (Page) in I _ block (B 1 ock) of flash memory managed by staggered execution, each flash memory Magnetic field (Z ο ne) 0 composition

I _ magnetic zone (Z ο ne) 〇 'Each magnetic memory's magnetic zone 1 贝 1J constitutes I _ magnetic zone (Z ο ne) 1' and so on can be divided into I _ magnetic zone (Zone) 0, I_ magnetic zone (Zone) 1, I _ magnetic zone (Zone) 2 'and I _ magnetic zone (Zone) 3' four large blocks, and one I _ magnetic zone (Z ο ne) is still only 1 0 2 4 I —Blocks, and each 1_Block (B 1 0ck) is also formed by the same block combination of two flash memories ||, because of this, each I —The 1_page block (Page) of the block (B1 ock) will be twice the block, that is, an I _ block (B1 ock) has 64 I_page blocks (Page), that is, It is said that an interleaved execution architecture composed of two 64Mbytes has four I _ magnetic zones (Zone) each I _ magnetic zone (

Page 15 200422930 Five explanations B I C blocks 4 areas 6 I have 1 \ ly k 4 C 2 0 ο -—_ 1 B has C} blocks e area η-Ο k blocks C area ο page per

2 1 5 X 8 2 IX X 4 2 ο τ—Η X 2 is the regular quantity. Capacity > total e its g while a P a g 6 M 2 X 4 6 equals

The order is the flow rule, and the pages of the partition are divided into blocks e, g, a, P, C, two-phase blocks, middle, S, k e 1C t I ο y, *-· B) B

S Θ ty B The block area is based on the area magnetism I ο I is in}, oe \) y Ω is e ο 0 g ζ) a (kp area cc magneto 1 area body B in the block page-It / IV I II i Fast I o 1 of the flash region of block 1} k k o C to \ 1 / o with e · point η B is oc set Z block location body

I area and magnetic block, inner area ο body page} memory of e ο g flash / a fast k P c c two ο block 1 to 3 pages with c block ο 1 area 3} block ke area cb 〇 中 oao -— "-p \ ly B (ec block n block o block page z from 1C to the allocation point c and then block Sc one product-〇〇) ο e) S β a η ρ 〇 (ζ block C Area I magnetic I, I body, remember ο remember \) y flash e fast S a a P P block M ((| Block I magnetic area, page 1 body} memory ο e remember} g flash ka fast CP particles οC 2 1 block B area to {page back block allocation area ο points X) / 0〇1K \) / \) / c ee og η 1—- 3 ο Β ρ ζ execute k wrong c cross ο After 1 body 'Β It (The flash area of the block is described quickly. I f is c & U is the crotch is CD. Ο, π is deduced. Ο This is the picture. {In the B domain, the 5th district 1st | Read I CU reference For g, please manage 8 lines of P, and change the position of the tube body to implement the above formula. The most necessary k is IJ C, which is a formula, B points, and the ky position CP body a. Ο Real BC Y plus 111P in the middle of y, not B ο if five C, and A if you add five points to the dan \) κ SC > page 16 200422930 V. Description of the invention (14) y is the body I fast y > Block package + surface package} package evil) p, C is real c. PCDC area cn block LO block oe ο block 1} οη block, block 3 block 4 is block 52C block ccn block C block, I ec a block order} block number,} 2} block 13 side ο into the partition After the page, 1 of g refers to e magnetic} kvlle magnetic 1 + block Z additional magnetic | physical} 3 new 0 ^ 0 n-) k C η η |} η region c epitope II tube ep'c Ikaleca < lal54 and area description -11 and 11 {Let surface 101 have 113101 have 5th place, magnetic body position} ko block finger block ap place OIBCP place 2} | is the real position k CZ area BC is ZBC1C Is < ll} kc, Γ body 0 ac page 坆 area} < {block + face}]! 'C | shown in the real aB area 1C four eyIk block area n block kvllnal Equation 1 magnetic ca npcc magnetic area 14 area cool graph square tube By I IB points ao-a | 1C first, aczB new B CPCI 1CI1II |} 12 < {is a six-tube block ο | and y, P is subject to B's } I} k B + block view, cl cl} P-type C and OC have 5 e ccn block area can be A new error I can be converted into ko aspect} Block Lolna block 4 area I is the intersection of six I Add and change the CC block to the e zone 2} ol zone, IO order, and the district of a)} n-) < = ez BI's reading guide}} show a new kack n nccc} k5 e reference k clear ee table B body k-cl Icvlla area Iec5n Please 0 out] 100 < Yi 0 with 30.1301 magnetic domain 11132 3 a said oa collocated block referred to a and 1C of LEP | | the ol < lll B of ZP bit area flash B, B side including BOCII comprises ZBnp

move

I

Page 17 200422930

ane) 1 is the new z-c magnetic field (• etc.) 5. Description of the invention (15) 0, block area (p 1

Zone) 1 · · In the initialization of the "logical" and "physical" positions of the flash memory, in the management of the flash memory, each block will have a "logical" position and a "physical" position. The "logical" position is where the host wants to read the data; the "physical" position is where the flash memory is managed. If interleaved execution and C0py Back are not considered, the "shell" can be considered as flash memory Actual location, but because of the addition of interleaved execution and management of C pypy ack, it is mentioned here that the "Entity" is not the same as the actual location of the flash memory. Before memory, you must first find out the relative "logical" position of the "^ body" in each block in the flash memory. This table that logically maps to the "physical" position is called a link table (Link T ab 1 e) Because the management structure is based on the parent / child concept, two "physical" positions may appear in a flash memory and refer to the same "logical" position at the same time, and the manager must go Judge these two "Entity" position which is the mother and which is the child, merge the mother and the child, fill the remaining page blocks of the child with the parent's page blocks, and then erase the mother, so link the table (Link T The "r logic" and "entity" in ab 1 e) will become one-to-one correspondences. After the link tables (L ink T abje ^) are all established, then the host end will be under the flash memory. The "logical location" official can quickly find out the "physical" position of the flash memory and process the flash memory. In addition to creating a link table, another function is being initialized. In the process, some

200422930 V. Description of the invention (16) Logical blocks or some blocks that were not handled properly are recorded as spare blocks. These spare blocks are the "new blocks" needed for flash memory to read and write. After the mother and son are merged and the mother is erased, this block is recorded as a spare block. Please refer to FIG. 7 for a flowchart of processing data read from the host to the flash memory according to the description of the present invention. The present invention will be performed according to the following steps, step (a) He a d_ obtained from the host (700)

The 6th bit in Number (Byte) is recorded as the position of the host. Determine whether it belongs to the CHS call or LBA notation (7 10), "0" gCHS notation, and "1" is the LBA calculation. Method, if it is LBA, perform (7 2 0), CHS then (711), convert the position from CHS to LBA, and then (720), and the conversion method of LBA and CHS is as follows: LBA = (((Trackx Head — Per _ Track) + Head — Num) x Sector _ Per _ Head) + Sector _ N um) — 1; 钃 Note: a: The parameters in the above formula are all represented by CHS. b: Track • (track)

Cylinder) 〇 c -Head _ Per _ T r a c k ·· — tracks (

Page 19 200422930 V. Description of the invention (17) How many heads is Trac? d: Head — Num: The number of heads (Head). e: Se c t 〇 Per _ Num: how many sectors are there in a magnetic head (H e a d). f: Sect or _ Num: The number of sectors (Sector) ° g: The L B A representation converted by the formula in this way indicates that this position is the number of sectors (Sec tor). h: Sector Counter: How many pieces of data to send to the host (Η 〇 s t). Step (b) how many magnetic zones (Z ο ne) the flash memory has, how many blocks are there in a magnetic zone, and how many page blocks are there in a block (P age) (a page block is a section) to calculate the position (720) indicated by this LBA, and this position is the so-called logical address, that is, the logical position, this section is in the several magnetic zones The number of blocks and pages in the block, and then through the link table (Link T ab 1 e) point out the corresponding "Entity" position (7 3 0); Step (3) by the fifth A The conversion methods shown in Figures 5, 5B, and 6 correspond to the actual location of the flash memory (740). The step (4) is managed by two page blocks (P age ) Is single

Page 20 200422930 V. Description of the invention (18)

Step (5) Step (6), but the data to be read if the number is more than one (Page (751) (7 5 0) Page) is entered into the flash memory of this data , The flash memory system's buffer flash memory of the two flash memory 6 2), and then 6 3), and two pages of block data (7 5 two sets of signals with the flash memory to make bits Do not read the data at the same time to judge the current 7 500), two pages of block data, the material is only one page block (do read data manager judgment body or the second one flash mark The first material is sent to the second fast burst signal controlled by the second fast burst (7 host side (7); when the manager reads the group signal and the first and second bursts in a way The machine side (Η 〇, so the reading is a pen or pen, that management) is the soap level. 'If it is currently, then the management is the early position to go to the right line (7 6 0 is in the first mile (7 6 0 managers will To read the actuator (7 6 'The manager recalls the data to the buffer to execute Jump out (page 0), the st of the first read data in the management needs more than one stroke to get the data (or you can read the data to be read in a way to get _ flash memory); A flash memory) 'If you are using the first group of messages, and use 1), if you are using the second action, and the controller ’s slow data is sent to the circle (7 7 1), the person using the unit One flash memory action (7 5

Step on page 21 (200422930 V. Description of the invention (19) 1), (The first group (Address Bu when the command is issued, and the poor materials are stored in order to send the data to the host's flash memory in order. The data is missing. Memory, because the flash memory started on the host end, so the starting address to determine the two steps (seven) when the position is incremented to determine whether the flash memory read (7 8 0) Steps go to (7 5 〇). Please refer to the eighth figure, which is a flowchart of processing the flash memory to the present invention. The present is as follows: χ) Obtain N umber (Byte record as The representation of the position under the host side is still LBA "is CHS notation," 1 for LBA is performed (8 2 (8 1 1), and the position is performed from ◦ (820), and the L method is as follows: · and The address signal S) of the second group will differ by Γ 1 ″) In the buffer of the controller, the terminal (7 5 2) must be sent to the flash memory first. The address may be obtained from the second manager. End of the material order (7 7 〇) and information to continue to quickly, if necessary, skip back to the process The description on the host side writes the 6th bit of Head_) which will be executed according to the following steps. It is judged that it belongs to the CHS method (8 1 〇), "0" is the LBA algorithm, 〇), and CHS performs HS to lbA, BA and CHS conversion

200422930

V. Description of the invention (20) LBA = (((T rack XH ead — Per _ T rack) + H ead N um) XS ect 〇r Per H ead) + S ect 0 r N um) — 1 j : A: The parameters in the above formula are all represented by CHS. b: Track: several cylinders (Cylinder) 〇c: Head Per Track: one magnetic holder (Γ ο ot) (C d head ea magnetic s 6 Η one section 〇: area d head In A magnetic U, e, and N. The first | segment: the first? ^ 111 111 less: e U more mp less N is U | more I} Nr has rk-ο) ο cdtdt aacac Γ 6 6 Θ 6 o THSHS def g: The LBA notation converted by this formula indicates that this position is the sector. h: Sector Counter: How many pieces of data to send to the host (Η 〇 s t). Step (b) how many magnetic zones (Z ο ne), how many blocks (Z ο ne) are there in a flash memory, and how many page blocks are in a block? (P age) (— a page block (Page) is calculated as a sector (Sector)

Page 23 200422930 V. Description of the invention (21) The position indicated by L · BA (82 positions is the so-called logical address, this section is the first page block in the magnetic sector, and then After the link form (ding ab 1 e) will correspond to the "actual 8 3 0); Step (c) from the fifth A, five B, six A, six B formula to truly correspond to the actual position (840) pointed out; Step (d) Although the management is based on two page blocks (bits to read data, but the host side (the data entered is not necessarily even), the obtained judgment is that the data currently written is ( 850), if it is more than one stroke, use two pages (Page) as the writing data, proceed to (851), if the data has only one stroke (850), then one page block (Page) is used to fill in the information. Action (step (5)) The manager judges whether this data is written in the body or the second flash memory (8 one flash memory, the manager number is moved from the buffer of the controller). The data memory (8 6 1) 〇) is located, and this is the logical location, several blocks, The position of “Several Links” indicates that the Page of the conversion party to the flash memory shown in the figure is a single i H 〇st.) When reading data—a pen or more than one stroke, the manager can use the unit method. Fill in what is currently being written. The manager has a bit to store the flash memory 8 6 0); the first flash memory 6 0), if it is the first, use the first group of messages to the first flash memory, if it is On the second

V. Description of the invention (22) In the memory of Shaanxi Shan, that step (six buffers of the controller adds the second set of signals from the second signal to j: do _ λ 11 miles to the second The flash memory should be managed by K = 8 (8 6 2); Tian Luzhuli: ^ read data in two hundred ways ^ ^ age) as the group signal and the second group H 5 〇), the manager Use the first and the first -_ # n, # # to simultaneously fill in the data for the first flash memory = memory (85 (A ddr: ^ h the first and second address signals "And the data will follow": two :) will differ by "1") Expected flash memory, ^ jf controller's buffer transfer < to the first flash memory τ :: data missing It is necessary to fill in the address that may be from the second flash to the host side to get the host side =: = 'so the management order (8 5 2); the steps to determine the two pieces of data (seven ） Segment count of -2 and judge 0 again ”to perform (8 5 3) jump;】 to“ ”to perform (87〇); if not, if it is not“ 〇 step (eight), then judge whether the segment count is as large as At this time, the data to be written is "8 7). At this time, the manager reads only one item from the host. If this is the case, the manager = pen data (8δ〇) 8 7 1); read from the host. Two pieces of data (^ increase in the position of the field to determine whether there is still data to continue from the fast

On page 25, it is necessary to jump back to the process of flash memory devices (such as the USB card of the US Β • 〇 series. Only the best embodiment, therefore, any application that should still be included in the parallel dual-track use of this issue ' Therefore, the application requirements of the present invention are in order to protect the inventor's request for instructions from the letter 200422930 V. Description of the invention (23) The flash brother reads (8 9 0), if the step (8 5 0). The parallel dual-use method is used to manage the 1 · 1 series of flash drives, card readers, USB flash drives, card readers, or I DE / PCMC ΙΑ interfaces that are suitable for any host (Η 〇st). However, what is disclosed above is only the inability of the present invention to limit the scope of the patent of the present invention, and equal changes and modifications made due to the scope of the patent of the invention are clearly covered by the scope of the patent. 'When the above-mentioned flash memory method of the present invention is used, in order to truly achieve its efficacy and to be a creative creation with excellent practicability, in order to comply with the invention patent and apply according to law, I hope the review committee will grant this case as soon as possible, if the invention is hard, Jun Jury members have HE JI doubt, 'man-diligent with the invention, the public will be real sense.

Page 26 200422930 Simple illustration of the diagram [Simple illustration of the diagram]

Figure A

Figure B The technical steps of the technical drawing are as follows: ο from the 3 page of the block page to the material 0. Two writes are from the page of the block page ο the block to the material / cr are written as the first page

Figure C Block page from ο Block to material. Two} write two for C technique graphics step use for 3 series

From block ο to block Λ-r on the block page in Figure D. Two} write three for the C technique graphics step steps for the 3 series

Ο Block to material in Figure E Block page. Two} write four for the C-graphics technique step-by-step for the 3 series

Figure ο Block ο from block page to material A-r. Two} write five for C-techniques.

Figure A to the material and writing structure of the concept of the two children} \ Six mothers (using Tuli to describe step by step as the 3 series

Figure B to material Ar. Two} write a structure C frame picture concept of the child of the step 3 \ block parent page with a page description ο describe the block as the first

Figures C to 枓 -r. Two} write the second structure of the C frame picture concept of the child of the step 3 \ block parent page with a page description ο describe the block as the first

Figure D to material Ar. Two-write Three-frame C-frame Picture Concept Son of Steps 3 \ Block parent page description of page block

Figure E to the material. Two. Write four frames and five C frames C 1 1 | Into the heart 1 1 | Step by step 3 of the step child \ 3 The block description of the parent block is described as a block page. The drawing briefly explains the second F diagram, the second G diagram, the third diagram, the fourth A diagram, the fourth B diagram, the fifth A diagram, the fifth B diagram, the sixth A diagram, the sixth B diagram, the seventh diagram, and the eighth diagram. The page of block 0 is for describing profitability. The page of block 0 is for describing the status of only lines and for describing fastness to 2 fast lines. For describing fastness to 2 fast lines is to describe fast blocks (B 1 0 points.) It is used to describe the fast domain (Zon distribution). It is used to describe the plus management method. It is used to describe the plus management method. It is the processing stream of the present invention. It is the parent / child block 3 of the processing stream of the present invention. Use parent / child block 3 to use two fast architecture processes. Use the flash memory of the present invention. Use the conceptual framework of the flash memory of the present invention to write two pieces of data to the step diagram (6). Two data to the step diagram (seven). Flash memory and only consider interleaving. The use of parallel dual tracks is the same as the reading process The use of parallel dual tracks is the same as the flow chart for writing. I_ area I — area page (Flash) of interleaved execution management — I — area (e) of I — block ( BiOck) into the Copy Back instruction of the new "through body" position distribution (1). Enter the new "solid" position distribution map (2) in the Copy Back instruction. It describes the host-to-flash memory read process map. The description of the host writes data to the flash memory.

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Claims (1)

2UO422930 VI. Application for patent scope 1 A kind of action that can stand alone when there is a page area under a single meal riding structure 2. If you apply for a dual track to make the bottom 3, as for the user, because of the execution, the same handling, It is customary. 4. If you apply for the user, then enter the action of the control side to flash the flash δ memory and use the parallel dual-control method. It mainly uses multiple groups of 2 = buses. You must write the flash memory as a resource for transportation. The poor material of the multi-stroke segment r) will use multiple page blocks (... ㈠ ,, 己, memory) to read or write each time, so there are J hard-frames: standing For the data bus, the control side does not read or write the flash memory in units of a few years. The patent application method must enter the first item of the patent scope, where the second method is used in one step, where The use of more than one flash memory in parallel has a fast time. Therefore, in the patent method of the transport method, each of them is independent at the same time. The two parallel tracks are used to speed up the flash memory. Flash Parallel tracks plus the body of the flash memory on a staggered implementation of the architecture. Flash memory's parallel dual-track staggered execution architecture under the memory management together, staggered less waiting for busy time data bus, the data can be carried by the data processing side several times around the second method, Among them, the parallel dual, dual-track, and dual-track architecture of the flash memory is described in parallel. The next step is to use the concept of mother / child to cope with the flash memory. Erase memory life and increase speed. You do n’t need to, you can write in flash, extend the flash 200422930 VI. Patent application scope 5. The parallel dual-track use method of flash memory as described in item 2 of the patent application scope, wherein under the framework of parallel dual execution plus interleaved execution, the instructions of Copy Copy are further added to Temporarily storing data in a buffer (Buffer) can reduce the waiting busy state and shorten the data moving time. 6. The parallel dual-use method of flash memory as described in item 1 of the scope of the patent application, wherein the parallel dual-track use method for managing the flash memory structure is applicable to any host-side (Ho st) device ( Such as USB 1 · 1 series flash drives, card readers, USB 2 · 0 series flash drives, card readers or I DE / PCMC I eight interface _ interface card. Page 30