200421229 玖、發明說明： 【發明所屬之技術領域】 本申請案優先於2002年8月12曰提出申請的美國臨時專 利申請案第60/403，112號，其以提及方式併入本文中。 本發明與液晶顯不有關。 【先前技術】 投影顯示器及所謂的平板顯示器已根據液晶顯示器 (LCD)面板得到發展。通常藉由將適當的電壓施加至液晶顯 示器面板上的-連串列與行電極而將影像資訊提供給此等 面板。該等列與行電極的交錯定義圖像元素（像素），其光學 特：視施加於該等列與行電極上的電壓而定。某些液晶顯 示器面板亦包括—薄膜電晶體（祕film transistor ; TFT)陣 列且或夕個TFT可與每個像素相關聯，以允許對施加於 ^固像素上的電壓之控制更獨立料他像素上所施加的電 液日日顯示器通常在數個重 相 分變化，包括顯？ /數上展不相虽大的逐部 回應以及行：Γ;:::域的傳輸—致性、顯示電光 ^ 夕日日矽基的顯不器，此類變化俜 起因於多^基板的可變匕係 及其他製造程序有關。 、“…員不器裝配件 發生的製:變在化包:二晶顯示器的產品(例如-投影機)中所 整連行處理。：:=0一結束時的大量最終調 示器測試來進行b豕用自動測$設備或手動實施的顯 此專方法不但耗時，而且昂貴。此外， 87230 200421229 此類調整通常在產品組合時重複進行。t更換液 時也會出現類似的問題。由於每 曰曰，.’’、不杰 q在女衣更換顯示器之後進行調整。此等耗時… =整料不適合於產生服務技術人員所要求的效能= *而將辩貝不產品退回給製造商進行修理。因此 /步及額外的費用，並給客戶造成 ° 、 各尸仏戚不便。因此，需要改盖的 液晶顯示器方法與裝置。 "、 【發明内容】 顯不系統包括一顯示面板以及電連接至該顯示面板的一 互連。一記憶體係配置成用於儲存與該顯示面板相關聯的 顯不校正值’並固定於該互連。在代表性範例中，一顯示 控制器係配置用於根據該等儲存的顯示校正值處理一声像 信號，並將一關聯的影像輸送至該顯示面板。在其他=例 :’提供-記憶體，配置成用於健存顯示面板校正值的預 叹值’亚固定於該顯示控制器。在額外的範例中，該記債 體係配置用於儲存與紅色、綠色及藍色影像彩色成：相： 聯的校正值。 顯示系統包括-紅色成分（R)顯示面板，其配置用於接收 一紅色影像成分；-綠色成分（G)顯示面板’其配置用於接 收一綠色影像成分；以及一藍色成分（B)顯示面板，其配置 用於接收-藍色影像成分。一顯示控制器使用個別的r、g 及B互連電連接至該等彩色面板。一R記憶體'一G記憶體 及一 B記憶體係分別配置成用於儲存與該等R、g及b顯示面 板相關聯的校正值，且分別固定於該等R、g及B互連。在 87230 -7- 200421229 額外的範例中，該顯示控制器係配 用於從該等R、G及B σ思豆中擷取所儲存的校正值。在其他範例中，一預設記 憶體係配置用於儲存預設的校正值。在其他代表性範= ，该顯示控制器係酉己置將校正值儲存於該等R、G5t^憶體 〇 顯不系統包括-顯示面板以及_儲存裝置，其配置用於 保留與該顯示ϋ相關聯的校正值。提供_讀取及處理裝置 :用於讀取該記憶體中所儲存的顯示校正值，並根據該等 权正值處理影像值。此外，提供_固定裝置，用於 憶體固定於一顯示面板上。 & _不器裝配件包括-顯示面板以及一互連，其配置用於 將影像信號提供給該顯示面板。該互連係固定於顯示面板 且。己憶體係配置用於儲存與該顯示面板相關聯的校正 值，亚®定於該互連。在代表性範例中，該互連為一撓性 電纜。在其他範例中，該記憶體為一電子可抹除可程式化 唯^己憶體（electrically erasable programmable read 〇吻 mem〇ry ; EEPR〇M)，且該顯示面板為一液晶顯示器。在其 他的代表性範例中，該顯示面板為一 LSSH液晶顯示器，且 該記憶體係配置用於儲存與逐行顯示變化相關聯的校正值 。在其他範例中，該顯示面板為一 LSSH液晶顯示器，且該 記憶體係配置用於儲存與逐行顯示變化、資料斜坡時序、 底板電壓、區域亮度與電光傳送功能之至少一個相關聯的 权正值。在其它範例中，該顯示面板包括與不同色彩成分 相關的至少兩個子面板，且該記憶體係配置用於儲存兩個 87230 200421229 色彩成分的校正值。在額外 . 外的靶例中，該互連係配晋用# 將才父正值輸送至該記憶體。 ”配置用於 顯示互連包括一撓性電纜， 以及_記,丨音A 一 於附著於—顯示器， 顯示哭相x 規14包繞且配置用於儲存盥該 用:二相關的权正值。在其他範例中，該撓性電㈣配置 用於輸送與至少兩個色彩成 ^見係配置 體係配置用於儲存與該等至 …己匕 值。在其他範例中，該撓性電产传=成刀相關聯的校正 至所附著的記憶體。 見…己置用於將校正值輸送 許中方法已括將與一顯不器相關的校正值儲存至一記情 且中，亚將該記憶體附著於該顯示器。在 心 該儲存包、括儲存與至少兩個 、、乾例中， 们色心成分相關聯的校正值。在 巳歹1 、亥附者包括將該記憶體固定於 /文將參考附圖說明此等及其他特徵與優點。 【實施方式】 口手夕重要的液晶顯示器表砉 試斑.、0|丨θ >數絰過液晶顯示器製造商的測 ,:二]:。此等測試與測量結果可輸送至-嶋顯示產品 器服務技術人員’以減少或消除對額外液晶顯示 3 1里的而要。本發明提供了用於補償液晶顯示器與 不器個別變化的方法及系統，以及以此類系統與方 :、：礎：顯不器組合。雖然所說明的範例係關於多晶矽 〜心H ’但其他範例係關於陰極㈣ 卫可以為直接與像素值相關聯的值，或可與計算、内 87230 200421229 插或獲得像素值所需的參數相關聯。例如，校正值包括 個，素的個別校正值或用於計算此類值的功能值。如本文 斤提及杬正值與一特定液晶顯示器相關聯。盘數個顯 器相關聯的值或通用校正值稱為預設值。一液晶顯示；： 板可包括與個別色彩成分相關聯的區域（「子面板」），使得 例如可藉由組合該等子面板的影{象而以一單一面板獲得全 :*員丁 σσ或者’可操作—具有單—像素區域的液晶顯示 器面板’以便產生列順序、訊框順序或其他順序的彩色 示器。 〜 茶考圖1 ’ 一液晶顯示器顯示系統1〇〇包括一液晶顯示秦 裝配件105與-顯示控制器14〇，其包括一現場可程式問轉 120 (field programmable gate array ； FPGA) 〇 ^ ^ a ^ ^ 裔裝配件105包括一液晶顯示器顯示模組li〇，其透過一摘 性電缓13()連接至該顯示控制器14()。該液晶顯示器顯示模 ㈣〇包括與紅色、綠色及藍色彩色成分相關聯的液晶顯示 114、116。顯示控制器14〇可包括一特定應用積體 電路（ASIC)、-DSP處理器、離散邏輯或類似的半導體元件 以取代或補充現場可程式閘陣列12G。或者，現場可程式間 陣列120的至少某些功能可根據_電腦可讀取媒體上儲存 的電腦可執行指令實施，且該等指令配置成可由一處理器 執行’例如與個人電腦或網路電腦、手持電腦相關的通用 處理器或專用處理器。 顯示控制器140係配置用於為該顯示器m提供視訊資料 ’其可為例如一個人電腦視訊卡或其他視訊驅動器。該現 87230 -10- 200421229 唯王^陣列120係配置用於從_電子可抹除可程式化 所= 或其他附著於該撓性電、€13()的記憶體擷取 後二：:校正值。通常在顯示器裝配件製造程序完成 Η隍里 此4校正值’但顯示控制11140與現場可程式 可配置用於在其他時間將校正值儲存於電子可 示可私式化唯讀記憶體16〇中。撓性電㈣⑽固定於— =的顯示H裝配件，使得所儲存的校正值根據該特定液 广益的特性可與一特定顯示器裝配件相關聯。此外， :可抹除可程式化唯讀記憶體16〇亦可配置用於儲存通 厂^不器裝配件校正參數。對於一三色顯示模組，如該顯 ^組’可針對該等三個彩色成分之每—個提供校正值表 柄電子可抹除可程式化唯讀記憶體16〇包括非揮發性記怜 體，通常小至处字元x8位元的記憶體足以儲存校正值^ 亦可使用較大或較小的記憶體。因為顯示器11()經_1 ^可決定適當的校正值來校正、補償或消_中的 變化，且此等值儲存於雷；i &上 ㈣於電子可抹除可程式化唯讀記憶體16〇 中。所配置的顯示系統100係要使得當啟動顯示器装配件 m時，現場可程式間陣m2G讀取儲存於電子可抹除可程 式化唯讀記憶體！60中的值，並將其載入現場可程式閑陣歹; 120中適當的表格或暫存器。如上所述，電子可抹除可 化唯讀記憶體160中所錯存的值可由，製造商或一； 端使用者Η改變，並且若需要，可覆寫該等現場可 閑陣列表格或暫存器中的值。校正資料亦可館存於r〇^ 87230 200421229 EPROM、RAM或其他電腦可讀取媒體中。 在一粑例中，該等液晶顯示器！ 12、i 14、i 16係以所謂的 線掃描取樣與保持⑴此scan sample and h〇id ; LSSH)設計 為基礎中—液晶顯示器之—列中所有像素的影像值係 根據所取樣的輸人影像值加以確^，該等輸 送至個別行比較器’以控制將一資料斜坡信號施加於= 像素上。此類系統說明於（例如）pCT公開案w〇 〇2/5〇81〇。 圖5說明一 LSSH顯示器之一部分。此類顯示器之典型 的校正值可與以下各項相關聯：顯示器中的區域亮度變化 、顯示電光回應的變化、與資料斜坡信號產生相關的值(方 便地儲存於—資料斜坡表格中）、行非-致性校正值（方便地 儲存於-订校正表;^中）、基於一資料斜坡ENABLE(致動） 暫存器中所储存的一或多個值的時序調整值、一 backplane(底板）偏移暫存器巾所儲存的底板電壓值。因 此，電子可抹除可程式化唯讀記憶體⑽可包括數組資料， 包括資料斜坡表’’行校正值；用於閃爍調整的電壓與時序 值X及區域才又正值。通常針對每個色彩成分提供資料組 。根據此類校正值，顯示控制器14G可決定已校正的影像資 :’並將已校正的影像資料轉送至該顯示器ιι〇。例如，可 安裝-特定液晶顯示器用於—綠色彩色成分，且對於該顯 示系統將其識別為一綠色顯示器。該顯示控制器14〇可配置 用於從電子可抹除可程式化唯讀記憶體⑽擷取與綠色相 關的校正值。 應注意 亦可採用替代的配置 例如，現場可程式閘陣 87230 -12 - 200421229 列120可使用撓性㈣13G或其他電纟覽或互連連接至顯示器 m’或可位於該顯示器110處，或固定於一挽性電繞。亦 可使用其他配置。 。。圖2為一示意區塊圖’說明現場可程式閘陣列120及顯示 益110的額外特徵。提供—組26()電子可抹除可程式化唯讀 記憶體261至264’各用於每個色彩通道（261至263),加上一 用於預設值的板預設電子可抹除可程式化唯讀記憶體加 ^以代替用於一組顯示器的單一電子可抹除可程式化唯讀 記憶體16G。因為儲存於該電子可抹除可程式化唯讀記憶體 2 6 4中的值並非一特定液晶顯示器或一組液晶顯示器所專 用’故該電子可抹除可程式化唯讀記憶體264可位於該顯示 控制器140處。 該現場可程式閘陣列12〇可配置成包括一微定序器區塊 210、一内部I2C介面220以及一微儲存器（區塊尺八熥)]%。 現場可程式閘陣列120亦可包括圖令未顯示的額外元件。現 場可程式閘陣列120中所實施的組件可藉由匯流排（如代表 性匯流排232、234)相互通信。資料匯流排235、236 '幻7 亦用於在現場可程式閘陣列120内通信，並在下文中說明。 微定序器210為包括預定義「程式」的微碼引擎，該等程式 從電子可抹除可程式化唯讀記憶體26〇讀取值，並將其寫入 現場可程式閘陣列120中的位址位置，如微儲存器23〇。或 者，微定序器210可透過外部介面24〇讀取或寫入資料。微 定序器210可配置用於將所有的電子可抹除可程式化唯讀 記憶體資料載入現場可程式閘陣列12〇中對應的暫存器，2 87230 200421229 在接收到來外部介面24G的命令後載人部分或全部暫存写 外部介面包括一串列資料（Εχτ一SDA)線242與一串列 (EXT—SCL)時脈線244，且通常由作為該顯示控制器14〇之 一部^的系統級微控制器（未顯示）加以控制。在此範例中， 1 C」（或「I2C」）匯流排係用於在現場可程式閘陣列 與其他顯示系統（如顯示控制器14〇與電子可抹除可程式化 唯頃記憶體26G)之間進行通信。12<3匯流排可以為一簡單、 雙向、一線串列資料（SDA)及串列時脈（SCL)匯流排用於IC 之間通。然而，可使用其他類型的控制匯流排。 與 I2C 介面 圖3為區塊圖，說明I2C介面220、微定序器210及匯流 排夕工态3 1 〇的運作。圖中顯示微儲存器區塊ram23 〇、自 動載入邏輯330以及至内部現場可程式閘陣列匯流排的連 接。此等連接包括一 8位元位址匯流排235以及8位元資料匯 流排236、一 6位元頁面匯流排237以及一 i位元寫入選通324。 I2C 面220實行數項功能。其監視外部介面24〇的命令序 列，包括現場可程式閘陣列丨2〇正確的主要位址。當其將此 類命令序列偵測為一寫入序列之一部分時，其將進入資料 解除串列化於位址及資料匯流排235、236上。其亦在該寫 入選通線324上發送一適當定時的信號。當I2C介面22〇將此 *員中令读測為一讀取序列之一部分時，其將該等資料串列 化於貧料匯流排236上，並將其發送回到外部I2C連接240之 外0 87230 -14- 200421229 I2C 面220亦對出現於頁面匯流排237上的資料進行解 碼。根據I2C介面220中的一間接頁面暫存器（未顯示）的内容 對頁面資料進行解碼。如圖3所示，256個字元的64個頁面 勻可k仏此外71面22〇可解碼所用的額外功能，例如， 您端控制微定序器210的運作。當由從控制暫存器34〇輸送 至一輸入342的一 MSTR信號致動時，I2C介面22〇與微定序 為2 10成為外部I2C連接240的匯流排主控器。在此條件下， 可將I2C位址與資料寫入至外部I2C連接24〇上的其他元件。 在此範例中，電子可抹除可程式化唯讀記憶體261至264 , 皆具有相同的I2C位址。這需要串列資料線251、252、253 、254的多工處理（微定序器21〇與I2C介面22〇的外部）。此等 資料線可將現場可程式閘陣列】2〇連接至液晶顯示器丨丨2、 U4、116(顯示於圖2中）。將時脈信號D—SCL255發送至所有 的顯示器112、114、116及所有的電子可抹除可程式化唯讀 記憶體261至264。多工處理由一匯流排多工器31〇進行操作 。匯流排多工器310包括一控制暫存器340與一偏移暫存器 3 5 0。控制暫存态3 4 0允許選擇該組2 6 0中一特定的電子可抹 除可程式化唯讀記憶體供微定序器210存取。匯流排多工器 3 10亦可多工處理I2C介面220與該微定序器210之間的位址 匯流排235、資料匯流排236、頁面匯流排237與寫入選通線 324。此外，匯流排多工器310可解多工處理來自該組26〇電 子可抹除可程式化唯讀記憶體的資料，並使用偏移暫存器 35 0將資料解除串列化於資料匯流排236上。匯流排多工器 3 10係藉由匯流排371、372、373及資料線342、3 74連接至 87230 •15- 200421229 I2C介面220。匯流排多工器3 1〇係藉由匯流排375、3%、 及線378、379、380連接至該微定序器21〇。 z 』此有其他 微定序器 圖4顯示微定序器21〇的一簡化區塊圖。微定序界幻〇執一 :存於現場可程式㈣列丨尉的指令以讀取與寫入夕^ 電子可抹除可程式化唯讀記憶體261至264上的序列。微定 序器210亦可將資料傳送進入特定的位址，或透過外部介： 240將貧料從現場可程式閘陣列12〇傳送出去。微定序器幻〇 可視為一訂製用於管理一 I2c介面的微處理器。 π 表格1在一代表性範例中列出微定序器210的一指令隼。 指令係採用16位元字元的形式，其中較低的7個位元=作 碼與旗標組成。較高的9個位元包括欲輸出的資料、運瞀元 、位址暫存器4U或頁面暫存器414的位址，或程㈣=哭 416或傳送迴路計數暫存器418之分支位址。在表丨中 較高9個位元運算^搁位的值 _ 指令 說明200421229 (1) Description of the invention: [Technical field to which the invention belongs] This application has priority over US Provisional Patent Application No. 60 / 403,112, filed on August 12, 2002, which is incorporated herein by reference. The present invention is not related to liquid crystals. [Prior Art] Projection displays and so-called flat panel displays have been developed based on liquid crystal display (LCD) panels. The image information is usually provided to these panels by applying a proper voltage to the -series and row electrodes on the panel of the liquid crystal display. The interleaving of the column and row electrodes defines a picture element (pixel), and its optical characteristics: It depends on the voltage applied to the column and row electrodes. Some liquid crystal display panels also include-thin film transistor (TFT) arrays and or TFTs can be associated with each pixel to allow more independent control of the voltage applied to the fixed pixels The electro-hydraulic day-to-day display applied on the display usually changes in several phases, including display? The number-by-part response and the line-by-line response are as follows: Γ; ::: The transmission of the field—consistency, display of electro-optic ^ Silicon-based display devices, such changes are due to the availability of multiple substrates. Changing knives and other manufacturing processes. , "... the system of the production of the fittings: change in the package: two-crystal display products (such as-projectors) in a row to deal with. :: = 0 at the end of a large number of final monitor test to carry out b 豕 This special method using automatic measurement equipment or manual implementation is not only time consuming, but also expensive. In addition, 87230 200421229 such adjustments are usually repeated in the product mix. t Similar problems occur when changing fluids. "...", Bu Jie adjusted after changing the display of the women's clothing. These time-consuming ... = the whole material is not suitable for the performance required by the service technician = * and the product is returned to the manufacturer Repair. Therefore, steps / extra costs and inconvenience to customers. Therefore, the LCD display method and device need to be changed. &Quot;, [Abstract] The display system includes a display panel and a power supply. An interconnect connected to the display panel. A memory system is configured to store display correction values' associated with the display panel and fixed to the interconnect. In a representative example, a display control The device is configured to process an audiovisual signal according to the stored display correction values, and send an associated image to the display panel. In other = example: 'provide-memory, configured for healthy display panel correction The value of the predictive value is fixed to the display controller. In an additional example, the debit system is configured to store correction values that are associated with the red, green, and blue images: phase correction: The display system includes- A red component (R) display panel configured to receive a red image component; a green component (G) display panel 'configured to receive a green image component; and a blue component (B) display panel having a configuration For receiving-blue image components. A display controller is electrically connected to the color panels using individual r, g, and B interconnects. An R memory, a G memory, and a B memory system are configured for The correction values associated with the R, g, and b display panels are stored and fixed to the R, g, and B interconnects, respectively. In an additional example of 87230 -7- 200421229, the display controller is configured for From these R, G, and B σ The stored correction value is retrieved from Think Bean. In other examples, a preset memory system is configured to store the preset correction value. In other representative ranges =, the display controller has stored the correction value. The R, G5t memory system includes a display panel and a storage device, which are configured to retain the correction value associated with the display device. A reading and processing device is provided for reading the display device. The display correction value stored in the memory, and the image value is processed according to the weighted values. In addition, _fixing device is provided for fixing the body on a display panel. &Amp; And an interconnect configured to provide an image signal to the display panel. The interconnect is fixed to the display panel and. The Memories system is configured to store the correction values associated with the display panel, and Asia® is scheduled for this interconnect. In the representative example, the interconnect is a flexible cable. In other examples, the memory is an electrically erasable programmable read (electrically erasable programmable read memory) (EEPROM), and the display panel is a liquid crystal display. In other representative examples, the display panel is an LSSH liquid crystal display, and the memory system is configured to store correction values associated with progressive display changes. In other examples, the display panel is an LSSH liquid crystal display, and the memory system is configured to store at least one weighted value associated with progressive display changes, data ramp timing, backplane voltage, area brightness, and electro-optical transmission functions. . In other examples, the display panel includes at least two sub-panels related to different color components, and the memory system is configured to store two correction values of 87230 200421229 color components. In the case of additional targets, the interconnect is paired with # to send positive values to the memory. "Configured for display interconnection includes a flexible cable, and _note, 丨 A, attached to the display, display crying phase x gauge 14 wrapped and configured for storage use: two related weight value In other examples, the flexible electrical configuration is configured to convey at least two color components, and the configuration system is configured to store the values of the and .... In other examples, the flexible electrical transmission = The correction associated with the knife is attached to the attached memory. See ... The method used to transfer the correction value to Xuzhong has included storing the correction value related to a display device into a memory, and Ya The memory is attached to the display. In the storage package, including storage and at least two, the correction value associated with the color center component. In the case of 巳 歹 1, the attachment includes fixing the memory to / These and other features and advantages will be explained with reference to the accompanying drawings. [Embodiment] The important LCD test table for testers, test spots, 0 | 丨 θ > : .These test and measurement results can be delivered to-嶋 Display Product Service Technicians' to reduce or eliminate the need for additional liquid crystal displays 31. The present invention provides a method and system for compensating for individual changes in liquid crystal displays and devices, and the use of such systems and methods: No combination of devices. Although the examples described are about polycrystalline silicon ~ core H ', other examples are related to the cathode guard, which can be values directly related to pixel values, or can be used to calculate, interpolate or obtain pixel values within 87230 200421229. The parameters are related. For example, the correction values include individual correction values of primes or functional values used to calculate such values. As mentioned in this article, positive values are associated with a specific liquid crystal display. Several indicators are related. The associated value or universal correction value is called a preset value. A liquid crystal display: The panel may include areas ("sub-panels") associated with individual color components, such that, for example, by combining the images of these sub-panels And get a full with a single panel: * members σσ or 'operable-LCD panel with single-pixel area' in order to produce column display, frame order or other order color display Device. ~ Tea Test Figure 1 'A LCD display system 100 includes a LCD display assembly 105 and a display controller 14〇, which includes a field programmable gate array 120 (FPGA). ^^ a ^ ^ The mounting device 105 includes a liquid crystal display display module li0, which is connected to the display controller 14 () through a dissipative electrical switch 13 (). The liquid crystal display display mode includes liquid crystal displays 114 and 116 associated with red, green, and blue color components. The display controller 14 may include an application specific integrated circuit (ASIC), a DSP processor, discrete logic or similar semiconductor components to replace or supplement the field programmable gate array 12G. Alternatively, at least some functions of the field programmable array 120 may be implemented in accordance with computer-executable instructions stored on a computer-readable medium, and the instructions are configured to be executed by a processor, such as a personal computer or a network computer. , Handheld computer related general-purpose processor or special-purpose processor. The display controller 140 is configured to provide video data for the display m ', which may be, for example, a personal computer video card or other video driver. The present 87230 -10- 200421229 Veyron ^ array 120 series is configured to retrieve from the _ electron erasable and programmable = or other memory attached to the flexible electric, € 13 (): 2: correction value. This calibration value is usually completed during the manufacturing process of the display assembly. However, the display control 11140 and the field programmable can be configured to store the calibration value in the electronic display personalizable read-only memory 16 at other times. . The flexible battery is fixed to the display H assembly of the ==, so that the stored correction value can be associated with a specific display assembly according to the characteristics of the specific fluid. In addition, the programmable read-only memory 16 can be erased and it can also be configured to store the calibration parameters of the factory-installed parts. For a three-color display module, if the display group can provide a correction value for each of the three color components, the handle can be electronically erased and the programmable read-only memory 16 includes non-volatile memory. Memory, usually as small as 8 characters of memory, enough to store the correction value ^ Larger or smaller memory can also be used. Because the display 11 () can determine the appropriate correction value to correct, compensate or cancel the changes in _ ^, and these values are stored in mine; i & electronically erasable and programmable read-only memory Body 16o. The display system 100 is configured so that when the display assembly m is activated, the on-site programmable array m2G is read and stored in the electronic erasable and programmable read-only memory! The value in 60 and load it into the field programmable idle; 120 in the appropriate form or register. As mentioned above, the values that are misplaced in the electronically erasable and read-only memory 160 can be changed by the manufacturer or the end user, and if needed, the on-site free array tables or temporary The value in the register. Calibration data can also be stored in r〇 ^ 87230 200421229 EPROM, RAM or other computer-readable media. In one example, these LCD monitors! 12, i 14, i 16 are based on the so-called line scan sampling and hold (this is scan sample and h oid; LSSH) design-based on the LCD image-the image values of all pixels in the column are based on the sampled input The image values are determined, and these are sent to individual row comparators to control the application of a data ramp signal to the pixels. Such systems are described, for example, in the pCT publication WO 02/0581. Figure 5 illustrates part of an LSSH display. Typical correction values for this type of display can be associated with: changes in area brightness in the display, changes in the display electro-optical response, values related to the generation of data ramp signals (conveniently stored in the —data ramp table), rows Non-consistent correction value (conveniently stored in the order correction table; ^), timing adjustment value based on one or more values stored in a data slope ENABLE register, a backplane (bottom plate) ) Offset the bottom plate voltage value stored in the register. Therefore, the electronically erasable and programmable read-only memory may include array data, including a data slope table ’s row correction value; the voltage and timing value X and area used for flicker adjustment are positive again. Data sets are usually provided for each color component. Based on such a correction value, the display controller 14G can determine the corrected image data: 'and transfer the corrected image data to the display ιι〇. For example, a specific liquid crystal display can be installed for a green color component, and it is recognized as a green display for the display system. The display controller 14 is configurable to retrieve green-related correction values from electronically erasable and programmable read-only memory. It should be noted that alternative configurations can also be used. For example, field programmable gate array 87230 -12-200421229. Row 120 can be connected to display m 'using flexible ㈣13G or other electronic viewing or interconnection or can be located at the display 110 or fixed In a one-turn electrical winding. Other configurations are possible. . . Fig. 2 is a schematic block diagram 'illustrating additional features of the field programmable gate array 120 and the display 110. Provide—group 26 () electronic erasable programmable read-only memory 261 to 264 'each for each color channel (261 to 263), plus a board preset electronic erasable for preset values Programmable read-only memory plus ^ instead of a single electronic erasable programmable read-only memory 16G for a group of displays. Because the value stored in the electronically erasable programmable read-only memory 2 64 is not specific to a specific LCD display or a group of liquid crystal displays, the electronically erasable programmable read-only memory 264 may be located at The display controller 140. The field programmable gate array 120 can be configured to include a micro-sequencer block 210, an internal I2C interface 220, and a micro-memory (block size 8 mm)]%. The field programmable gate array 120 may also include additional components not shown in the drawing. The components implemented in the field programmable gate array 120 can communicate with each other through buses (e.g., representative buses 232, 234). The data buses 235, 236 'Magic 7' are also used for communication within the field programmable gate array 120 and are described below. The microsequencer 210 is a microcode engine including a predefined "program" that reads values from an electronically erasable programmable read-only memory 26 and writes them to the field programmable gate array 120 The address location, such as micro memory 23〇. Alternatively, the microsequencer 210 can read or write data through the external interface 240. The microsequencer 210 can be configured to load all electronic erasable and programmable read-only memory data into the corresponding register in the field programmable gate array 120, 2 87230 200421229 upon receipt of the external interface 24G. After the command, some or all of the temporary storage is written. The external interface includes a series of data (Exτ-SDA) line 242 and a series (EXT-SCL) clock line 244, and is usually used as one of the display controllers 14 A system-level microcontroller (not shown) controls it. In this example, the “1 C” (or “I2C”) bus is used for field programmable gate arrays and other display systems (such as display controller 14 and electronically erasable programmable memory 26G). Communication between them. The 12 < 3 bus can be a simple, bi-directional, first-line serial data (SDA) and serial clock (SCL) bus for communication between ICs. However, other types of control buses can be used. And I2C interface Figure 3 is a block diagram illustrating the operation of the I2C interface 220, the microsequencer 210, and the bus mode 3 1 0. The figure shows the micro-memory block ram23 0, the auto-load logic 330 and the connection to the internal field programmable gate array bus. These connections include an 8-bit address bus 235 and an 8-bit data bus 236, a 6-bit page bus 237, and an i-bit write strobe 324. The I2C plane 220 performs several functions. It monitors the command sequence of the external interface 24, including the correct main address of the on-site programmable gate array. When it detects this type of command sequence as part of a write sequence, it de-serializes the incoming data on the address and data buses 235, 236. It also sends a properly timed signal on the write strobe line 324. When the I2C interface 22 reads the commander's command as part of a read sequence, it serializes the data on the lean bus 236 and sends it back to the external I2C connection 240. 0 87230 -14- 200421229 The I2C plane 220 also decodes the data appearing on the page bus 237. The page data is decoded according to the content of an indirect page register (not shown) in the I2C interface 220. As shown in FIG. 3, 64 pages of 256 characters can be used. In addition, 71 functions can be used to decode additional functions, for example, you can control the operation of the microsequencer 210. When actuated by an MSTR signal sent from the control register 34 to an input 342, the I2C interface 22 and microsequence 2 10 become the bus master controller for the external I2C connection 240. Under this condition, the I2C address and data can be written to other components on the external I2C connection 24o. In this example, the electronically erasable and programmable read-only memories 261 to 264 all have the same I2C address. This requires multiplexing of serial data lines 251, 252, 253, 254 (outside of microsequencer 21o and I2C interface 22o). These data lines can connect the on-site programmable gate array] 2 to the liquid crystal display 丨 丨 2, U4, 116 (shown in Figure 2). Send the clock signal D-SCL255 to all the displays 112, 114, 116 and all the electronically erasable programmable read-only memories 261 to 264. The multiplexing operation is performed by a bus multiplexer 31. The bus multiplexer 310 includes a control register 340 and an offset register 350. Controlling the temporary storage state 3 4 0 allows the selection of a particular electronically erasable programmable read-only memory in the group 2 60 for the microsequencer 210 to access. The bus multiplexer 3 10 can also multiplex the addresses between the I2C interface 220 and the microsequencer 210. The bus 235, the data bus 236, the page bus 237, and the write gate 324. In addition, the bus multiplexer 310 can demultiplex and process the data from this group of 26 electronically erasable programmable read-only memories, and use the offset register 350 to deserialize the data to the data stream On row 236. The bus multiplexer 3 10 is connected to 87230 • 15- 200421229 I2C interface 220 through bus 371, 372, 373 and data lines 342, 3 74. The bus multiplexer 3 10 is connected to the microsequencer 21 through a bus 375, 3%, and lines 378, 379, and 380. There are other microsequencers. Figure 4 shows a simplified block diagram of the microsequencer 21o. Micro-sequencing world magic 0 Executive 1: stored in the field programmable queue 丨 command to read and write evening ^ electronically erasable sequences on programmable read-only memory 261 to 264. The micro-sequencer 210 can also transfer the data to a specific address, or can transfer the lean material from the field programmable gate array 12 through an external interface: 240. The microsequencer magic 0 can be viewed as a custom microprocessor for managing an I2c interface. π Table 1 lists an instruction 隼 of the microsequencer 210 in a representative example. The instructions are in the form of 16-bit characters, with the lower 7 bits = code and flags. The higher 9 bits include the data to be output, the operation unit, the address of the address register 4U or the page register 414, or the program bit = cry 416 or the branch bit of the transmission loop count register 418. site. In the table, the higher 9 bits are calculated ^ The value of the placeholder _ Instruction Explanation
——主要位址N——Main address N
將N+1個字讀_電子可抹除可程式化唯讀記憶體 列，開始於先前由盤入仿 87230 -16 - 200421229 ---——一~~__ 命令設置的位址與頁面Read N + 1 words _ electronically erasable and programmable read-only memory row, starting from the previously copied imitation 87230 -16-200421229 ------- address and page set by a ~~ __ command
il η 13 從傳送記憶體冑資料寫入現場可程式閉p車列資料匯 流排 表1·微定序器指令集 一寫入位址暫存器422、一寫入微 —“7中所列的「虛設」I2C「開始」序列為一冗餘開始 :令’用於開始從電子可抹除可程式化唯讀記憶體讀取。 二個旗標可附著於此等指令的一部分。可設定—「閒置」 旗標，通常使用無操作指令’且用於決定所命令的操作何 時完成。「保存返回位址於分支上」旗標可用於標記執行— 分支指令後一程式中的位置。「使用ACK」旗標決定是否在 傳送操作上發送ACK脈衝（發信指示資料已成功接收卜 寫入位元組直接暫存器426以及一傳送記憶體42〇有利於藉 由透過外部I2C介面240所發送的命令直接控制微定序^ 210。將一位址寫入至該寫入位址暫存器迫使程式計數器 416到該位址。一寫入微碼直接暫存器用於迫使一 η位 元值進入指令解碼器436以解碼與執行。將一位元組寫入一 寫入位元組直接暫存器426可透過該I2C鏈路將該位元組發 87230 -17- 200421229 迗至該等電子可抹除可程式化唯讀記憶體26〗至264之一或 多個。 傳廷記憶體420為一 32位元組暫存器檔案，其可透過平常 傳运指令（見表1)從電子可抹除可程式化唯讀記憶體組 載入’或藉由平常寫入循環從外部I2C介面240寫入。一傳 送私令可用於從一電子可抹除可程式化唯讀記憶體依順序 讀取高達256個位元組，並將資訊寫入至現場可程式閘陣列 120中的順序位址。傳送記憶體42〇亦可用於將資料發送至 外部I2C介面240上的其他元件。例如，資料可以32位元組 的貧料塊形式從電子可抹除可程式化唯讀記憶體（通常為 板預设電子可抹除可程式化唯讀記憶體264)讀入傳送記憶 體420。 " 麥考圖3，然後控制暫存器34〇可致動將來自傳送記憶體 420的信號MSTR與資料輸送至外部I2C介面24〇。此類特徵 可用於配置外部元件’如類比至數位（A/D)轉換器、鎖相迴 路、解碼器以及可包括的其他組件。使用I2C介面22(^及微 定序器210)作為一匯流排主控器可允許簡化或省去視訊投 影系統中常有的微控制器。 回到圖4,微定序器21〇具有一條件分支邏輯單元432，其 由外部信號MSTRJEN控制，並使微定序器21〇可執行其程 式的一區段或跳過該區段。此外，外部信號決定 微定序器210是否當作匯流排主控器，以執行如上所述之配 置功能。一自動載入向量區塊43〇提供一内部「啟動開始 (p〇wer-〇n-Start)J信號，其迫使程式計數器416轉向一預定σ 87230 -18- 200421229 的向1C ’猎此觸發自會^兹；^哉λ Λ s’x自動耘式載入。一般而言，載入程式的 一分支指令位於此向量位址處。 工 圖4顯示微定序器21〇的其他組件，包括多工器，如多 ，438…輸出串列器及狀態機44()，以及回位址:存 為442。其他組件雖從圖4中省去，但亦可包括。 表2顯示一範例指令序列。該序列選擇外部電子可抹除可 程式化唯讀記憶體16〇的位址，並將2位元組傳送至現場可 程式閘陣列120中所選的暫存器。{括號}中所示的指令為透 過外部I2C介面24G從電路板14G接收的命令，且斜體所示的 指令係從微儲存器區塊R A M 2 3 〇中讀取。範例序列假定在微 ^^jJ^RAM230中有一指令序列，開始於位址U3 目前位址 操作碼 指令 運算元 Μ ' Κ 旗標 石π诅址113。 註釋 0 -- {寫入分 支至113} 從電路板140接收 113 WDI 寫入立即 控制 129 遥擇綠色電子可 抹除可程式化唯 讀記憶體160 114 WPA 寫入頁面 001 將頁面暫存器414 設定為1 115 WAD 寫入位址 012 將位址暫存器412 設定為12 116 ------ SSB 發送I2C 開始及主 要位址 160 發送 要位址=160(寫入 ) 117 SBT 發送I2C 位元組 000 次要I2C次要位址 較高位元組==〇 118 SBT 發送I2C 位元組 103 次要I2C次要位址 較低位元組= 103 87230 -19- 200421229 Π9 ^^_ SPB 發送I2C 虛設開始 及主要位 址 161 —----( 發送I2C虛設開始 及主要位址（讀取 ) 、 12〇 TRA 傳送2位 元組 002 從電子可抹除可 程式化唯讀記憶 體位址000103傳 送1位元組至現場 可程式閘陣列12〇 ’然後從電子可 抹除可程式化唯 讀記憶體位址 〇〇01〇4傳送1位元 組至現場可程式 閘陣列120，在頁 面1位址13 121 ^^_ STO 發送I2C 停止 -- 發送停止序列 122 RET 返回 了 返回至分支位址 + 1 NOP 無操作 -- 閒置 寺待另一命令 表2 ·範例指令序列 唯珠一範例中，約450個指令用於將一電子可抹除可程式化 浐，圮憶體的内容完全讀入現場可程式閘陣列12〇中。整個 :序，時約1秒鐘。-簡單微碼組合器可用於簡化代碼開發 v、維護。 ♦、、員不系統可配置用於儲存、擷取及校正儲存於—或多個 吕己憶體中的校正值，該笔# ;卜立M 罢田 θ 寺。己丨思月豆配置用於伴隨一相關聯的 _不器。此類顯示系統可包括顯示器裝配件，其所包括的 87230 -20- 200421229 一記憶體具有校正值的儲存值。此等系統使投影系統製迭 商可安裝或更換顯示面板’而不需決定用於該更換面板的 校正參數。此點可大幅減少生產投影機或其他產品 時間與資源。 而、 應明白，可改變所述之代表性具體實施例的配置與細節 ’而不致脫離本發明的原理。本發明主張包㈣隨附中請 專利範圍中的一切。 月 【圖式簡單說明】 圖1為與-電路板連接的液晶顯示器顯示“之區塊圖。 圖2為配置用於儲存與擷取顯示校正值的一現場可程式 閘陣列及電子可抹除可程式化唯讀記憶體之區塊圖。1 圖3為配置具有一 I2C介面、一微定康哭 口口 倣疋序态及一匯流排多工 杰的現場可程式閘陣列之區塊圖。 圖4為圖3之微定序器的區塊圖。 圖5為基於一線掃描取樣與保持的液晶顯示器之一部分 的區塊圖。 ^ 【圖式代表符號說明】 100 105 110 112 114 116 120 液晶顯示器系統 液晶顯示器裝配件 液晶顯示器顯示模組 液晶顯示器 液晶顯示器 液晶顯示器 現場可程式閘陣列 87230 -21 - 200421229 130 撓性電纜 140 顯示控制器 160 電子可抹除可程式化唯讀記憶體 210 微定序器區塊 220 内部12 C介面 230 微儲存器（區塊RAM) 232 ^ 234 代表性匯流排 235 、 236 、 237 匯流排 240 外部介面 242 争列貧料線 244 串列時脈線 251 、 252 、 253 、 254 串列資料線 255 時脈信號〇_8<^ 260 電子可抹除可程式化唯讀記憶體組 261至264 電子可抹除可程式化唯讀記憶體 310 匯流排多工器 324 寫入選通線 330 自動載入邏輯 340 控制暫存器 350 偏移暫存器 342 、 374 資料線 371 、 372 、 373 、 375 、 376 ^ 377 匯流排 378 、 379 、 380 線 87230 -22- 200421229 412 位址暫存器 414 頁面暫存器 416 程式計數器 418 傳送迴路計數暫存器 420 傳送記憶體 422 寫入位址暫存器 424 寫入微碼直接暫存器 426 寫入位元組直接暫存器 430 自動載入向量區塊 432 條件分支邏輯單元 436 指令解碼器 438 多工器 440 輸出串列器及狀態機 442 返回位址暫存器 87230 -23-il η 13 Data is written from the transfer memory to the field. Programmable closed car data bus. Table 1. Microsequencer instruction set-Write address register 422, Write to micro-"7 The "virtual" I2C "start" sequence is a redundant start: Let's start reading from electronically erasable, programmable, read-only memory. Two flags can be attached to part of these instructions. Can be set—The “Idle” flag is usually used with no operation command and is used to determine when the commanded operation is completed. The "Save return address on branch" flag can be used to mark the position in the program following execution of the branch instruction. "Use ACK" flag to determine whether to send an ACK pulse on the transmission operation (the transmission indicates that the data has been successfully received, the write byte direct register 426, and a transmission memory 42 are beneficial through the external I2C interface 240 The command sent directly controls microsequencing ^ 210. Writing a bit address to the write address register forces the program counter 416 to the address. A write microcode direct register is used to force an n-bit The byte value enters the instruction decoder 436 for decoding and execution. Writing a byte into a write byte direct register 426 can send the byte 87230 -17- 200421229 through the I2C link to the Etc. Can erase one or more of the programmable read-only memory 26 to 264. Passing memory 420 is a 32-bit temporary register file, which can be transmitted through ordinary instructions (see Table 1) Load from Electronically Erasable Programmable Read-Only Memory Set 'or write from an external I2C interface 240 through a normal write cycle. A transmit private order can be used to erase from an Electronically Erasable Programmable Read-Only Memory Read up to 256 bytes in sequence and write information to the field Sequential address in the program gate array 120. The transfer memory 42 can also be used to send data to other components on the external I2C interface 240. For example, data can be erased from the electronics in the form of 32-byte lean blocks Programmable read-only memory (usually the board's preset electronic erasable and programmable read-only memory 264) is read into the transfer memory 420. " McCaw Fig. 3, and then control the register 34 to activate the The signals MSTR and data from the transfer memory 420 are transmitted to the external I2C interface 24. Such features can be used to configure external components such as analog-to-digital (A / D) converters, phase-locked loops, decoders, and others that can be included Components. Using the I2C interface 22 (^ and microsequencer 210) as a bus master allows to simplify or eliminate the microcontrollers commonly found in video projection systems. Returning to Figure 4, the microsequencer 21 has A conditional branch logic unit 432 that is controlled by an external signal MSTRJEN and causes the microsequencer 21 to execute or skip a section of its program. In addition, the external signal determines whether the microsequencer 210 acts as Bus master to execute The configuration function described above. An automatic load vector block 43 provides an internal "start-on (Start) J signal, which forces the program counter 416 to a predetermined σ 87230 -18- 200421229. To the 1C 'hunting this trigger ^^; ^ 哉 λ Λ s'x automatic loading. Generally speaking, a branch instruction of the loader is located at this vector address. Figure 4 shows the microsequencer. Other components of 21〇, including multiplexers, such as multiple, 438 ... output serializer and state machine 44 (), and return address: save as 442. Although other components are omitted from Figure 4, it can also include . Table 2 shows an example instruction sequence. This sequence selects an external electronic erasable address of the programmable read-only memory 16 and transmits 2 bytes to the selected register in the field programmable gate array 120. The instructions shown in {parentheses} are commands received from the circuit board 14G through the external I2C interface 24G, and the instructions shown in italics are read from the micro memory block R A M 2 3 0. The example sequence assumes that there is an instruction sequence in the micro ^^ JJ ^ RAM230, which starts at address U3, the current address, opcode instruction, operand Μ ′ Κ flag stone π curse address 113. Note 0-{write branch to 113} receive 113 WDI from circuit board 140 write immediate control 129 remote select green electronics erasable programmable read-only memory 160 114 WPA write to page 001 save page register 414 Set to 1 115 WAD Write address 012 Set address register 412 to 12 116 ------ SSB send I2C start and main address 160 send wanted address = 160 (write) 117 SBT send I2C Byte 000 Minor I2C Minor Address Higher Byte == 〇118 SBT Send I2C Minor Byte 103 Minor I2C Minor Address Lower Byte = 103 87230 -19- 200421229 Π9 ^^ _ SPB Send I2C dummy start and main address 161 —---- (Send I2C dummy start and main address (read), 12〇TRA Send 2 bytes 002 E-eraseable Programmable Read Only Memory Address 000103 sends 1 byte to the on-site programmable gate array 120 ′ and then sends the 1 byte to the on-site programmable gate array 120 from the electronically erasable programmable read-only memory address 0001 04, on page 1 Address 13 121 ^^ _ STO Send I2C Stop-Send Stop Sequence 122 RET returned to the branch address + 1 NOP No operation-Idle temple waits for another command Table 2 · Example instruction sequence Only one example, about 450 instructions are used to program an electronically erasable and programmable, The content of the memory body is completely read into the on-site programmable gate array 12. The entire sequence is about 1 second.-A simple microcode combiner can be used to simplify code development and maintenance. ♦ The system can be configured For storing, retrieving and correcting correction values stored in one or more Lu Jiyi's bodies, the pen #; 普 立 M 田田 θ 寺. Si Yuedou is configured to accompany an associated _ not Such a display system may include a display assembly, which includes 87230 -20- 200421229 memory with a stored value of correction values. These systems allow projection system manufacturers to install or replace the display panel without the need for Decide on the calibration parameters for the replacement panel. This can greatly reduce the time and resources for producing a projector or other product. However, it should be understood that the configuration and details of the representative specific embodiments described can be changed without departing from the invention Principle The present invention claims to include everything in the scope of the attached patents. [Simplified Description of the Drawings] Figure 1 is a block diagram of the LCD display connected to a circuit board. Figure 2 is configured for storage and retrieval display A block diagram of a field programmable gate array and electronically erasable programmable read-only memory for correction values. 1 Figure 3 is a block diagram of an on-site programmable gate array equipped with an I2C interface, a micro-Dingkang crying imitation sequence, and a bus multiplexer. FIG. 4 is a block diagram of the microsequencer of FIG. 3. Fig. 5 is a block diagram of a part of a liquid crystal display based on one-line scanning sampling and holding. ^ [Illustration of Symbols] 100 105 110 112 114 116 120 LCD Display System LCD Display Assembly LCD Display Module LCD Display LCD Display LCD Programmable Gate Array 87230 -21-200421229 130 Flexible Cable 140 Display Control Device 160 electronic erasable programmable read-only memory 210 micro sequencer block 220 internal 12 C interface 230 micro memory (block RAM) 232 ^ 234 representative bus 235, 236, 237 bus 240 external Interface 242 Race line 244 Serial clock line 251, 252, 253, 254 Serial data line 255 Clock signal 0_8 < ^ 260 Electronic erasable and programmable read-only memory groups 261 to 264 Electronic Programmable read-only memory 310 Bus multiplexer 324 Write strobe line 330 Auto load logic 340 Control register 350 Offset register 342, 374 Data line 371, 372, 373, 375, 376 ^ 377 bus 378, 379, 380 line 87230 -22- 200421229 412 address register 414 page register 416 program counter 418 transfer Loop Count Register 420 Transfer Memory 422 Write Address Register 424 Write Microcode Direct Register 426 Write Byte Direct Register 430 Auto Load Vector Block 432 Conditional Branch Logic Unit 436 Instruction Decoder 438 Multiplexer 440 Output serializer and state machine 442 Return address register 87230 -23-