TW200426560A - Optimization of clock network capacitance on an integrated circuit - Google Patents

Abstract

A method of optimizing clock network capacitance of an integrated circuit (IC) including identifying any crossover points between clock traces and signal traces and reducing clock trace to reference trace capacitance at identified crossover points. Each clock trace is shielded by ground traces routed on either side of the clock traces. The reducing of clock trace to reference trace capacitance may include narrowing the reference traces at identified crossover points. Narrowing of the reference traces at a crossover point reduces capacitance to compensate for additional capacitance between the clock trace and the signal trace. Narrowing may be performed by trimming or notching at the crossover points. Such capacitive compensation provides clock traces of the clock network with substantially uniform capacitance per unit length.

Description

200426560

This patent application claims US priority, whose application number is: 10 / 464,782, and the application date is May 21, 2003. All the contents and purposes of this patent are incorporated herein. μ Qingzhu [Technical Field to which the Invention belongs] The present invention relates to an integrated circuit (1C) layout (wiring) meter, and more specifically, to an integrated circuit clock network 2 ^ optimization. [Prior Art] of Phenomen Valley Today's digital integrated circuits can incorporate millions of transistor elements in a small area. These components control and complete their functions at each gate based on the boundary information of the core clock signal. Recently, the core clock signal frequency has exceeded two / gigahertz (GHz) threshold. The higher the clock frequency, the more difficult it is to control the core clock capacitance. At that time, when the pulse routing is inevitable, the capacitive coupling of the signal routing on the upper and lower layers of the clock routing layer becomes more sensitive. The traditional technology for controlling capacitors is to shield the two cables that are located on the same sound. The clock runs between the lines. Figure 1 is a partial top view of the integrated circuit (1C) 100, which shows ::, the traditional method of controlling the capacitance of the trace. As can be seen in w, the clock trace ι〇ι re! & On layer 107, the ground trace 1 0 3, 1 0 5 is routed relative to the clock trace 1 0 1 and so on, and two Width ground trace 2 / trace 1 〇1 ′ between 〇〇3 and 〇〇5 can make this clock trace and its on the same layer 1 〇7, WM 彳 j such as mother-to-ground trace The width of 103 and 105 is' and the distance between the signal trace 01 and each ground trace is " d ". The capacitance of the ground terminal of the clock trace is the ground trace 1 0 3, 1 0 5

H51〇twf .ptd 200426560 V. Description of the invention (2) The function of the width w and the distance between each ground trace 103, 105 and the clock trace 〇. By using equal-width ground traces 103 and 105, and placing ground traces 103 and 105 at equal distances on both sides of the clock trace 丨 〇1, for lower clock frequencies, A relatively uniform unit length capacitor can be obtained for the clock trace, that is: C1 = C2 = C3 = C4. At lower clock frequencies, such as below 1GHz, traditional techniques are sufficient to control the clock signal capacitance. However, with the emergence of scaling technology, when the device is allowed to run at higher frequencies, the content of the clock trace 101 will be inevitably routed at the clock trace1. 1 More influence of up and down signal routing. This effect is caused by the clock traces ιιι and; the capacitance between the signal traces 109 crossing the signal trace 109 on the other layer 1 11 and at the crossover point 11 3 from the clock trace 丨 〇 丨C5, ⑶. The capacitance to ground of the three-way clock trace 101 at contact 11 is greater than that of the clock trace 丨: The opposite point capacitance at other points. In particular, at the crossover point 113:,, C2 + C5 > C1, and C4 + C6 > C3. The problem of capacitance at higher clock frequencies is because the second force is seen at the jumper such as jumper point 113: the resistance-capacitance (眈) network characteristics of the electrical wiring 101 will change significantly, resulting in rise time. Increase, delay, and ^ = skew internal clock signals. The relative distortion of the first order is now referred to FIG. 2, which shows the problem shown in FIG. The block diagram does not include two consecutive fry 201 ^^ 2 02 ^ f ^ ^ In this type of circuit, the data together with the internal clock that assumes synchronous operation =.

11510twf.ptd Page 7 200426560 V. Description of the invention (3) LCLK1 204 and LCLK2 20 5 are synchronized from one logic block 201 to the next logic block 202. With the help of data bus 2 0 3, data is provided from logical block 1 2 0 1 to logical block 2 2 0 2. It is assumed here that the data bus 2 0 3 is valid and should be latched into the logic block 2 2 0 2 at point A. At point B, the data is no longer valid on the data bus 203. For ease of description, the signal LCLK2 20 5 is described as delayed, so it is not kept relatively synchronized with the operation of the signal LCLK 1 2 04. LCLK2 20 5 clock skew is caused by the capacitor non-uniformity caused by the crossover of the buffer logic (not shown) near LCLK2 204. In this way, the rise and fall time of the main% pulse distribution signal (not shown in the figure) will increase, so that the buffer logic will generate an internal clock signal LCLK2 205 as the LCLK1 204 delay type. At point c, the signal l (: lk2 205 has a latching edge, which can latch up the invalid data on the second. The situation shown in Figure 2 is only caused by the distribution of the clock. A typical example of the different timing problems of multiple modes caused by pulse skew. Therefore, 'What is currently needed is an ancient and earthy 4m ^ including running on the older days,' ^ ^ and also prepared ', its purpose is [ Circuit,) mention the long r electric: line circuit and ㈣ ^ [contents of the invention] P and electric equipment according to the implementation form of the present invention product optimization method includes identifying the clock wiring gate two network capacitors most recognized crossover point When admiral ^, the crossover point between the traces is at the value. Each clock trace is masked by the reduced trace capacitance to the reference trace capacitance. Decrease clock trace capacitance; low to reference trace capacitance operation can include 11510twf.ptd Page 8

ZUU4Z030U V. Description of the invention (4) At the identified crossover point, the steps include finding the clock trace 1 and examining the trace width. This method can also go to the clock trace and the signal bit length valley to find the identified jumper capacitance. The additional capacitance between the identified two capacitors needs to be calculated to offset the additional amount. The reference trace should be used at the layout point of the integrated circuit to edit the control file or application program ^ 〇 The clock network optimizer can be used during the implementation of the clock trace included in the first layer according to the present invention === one The method from the circuit to the integrated circuit includes ground wiring, determine the clock connection, and the crossover points of the first and second connection (winding), and reduce the two between the signal traces on the "irir" layer. Ground trace wiring day; "5th and second ground trace widths. The distances are also approximately equal. Also, the distances are approximately the same, and the clock traces are in accordance with the implementation form of the present invention, with reference to the traces. Moreover, the circuit of the sand bar body includes the first and second pulse traces, and the time reference traces across the first layer of approximately equal distances are divided by the signal traces; and the traces. Every-approximately equal width. In addition to the narrowing of I, Y, and junctions, they have the media 'iL :; code' incorporated to 'run in the circuit wiring library'; used to calculate the time with at least one jumper: the second of the length capacitor The program code is used to calculate the third program stone horse caused by the additional capacitance across each corresponding ^ trace: Calculate the corresponding reference path required to offset the additional capacitance at each crossover point

200426560

5. Description of the invention (5) The fourth program code of the line width reduction amount. The media can also be programmed with five codes to modify the circuit routing database to reduce the reference trace width by including the first reduction in width. The calculation of the media is as follows: "The above and other purposes, characteristics, and advantages of the book are easy to understand." A preferred embodiment is given below, and it is also explained in more detail as follows: π7 口 a 'Details [Implementation] The following The purpose of description is to make the application field of this field and its requirements to use the present invention smoothly. However, modifications have been made to the definition, and the 贝 t-bezier form as defined here is an application form. Therefore, this bamboo shoot is not just: ^

Form, but applicable to a wide range of specific implementations described here. 〃 本 ... 达 Principle and novel features Phase I The inventor recognized that the clock signal side is maintained% The junction capacitance fluctuation compensation is shown in Fig. 3. The integrated circuit (IC) is a circuit according to the embodiment of the present invention. / ^ View, the core clock signal is provided on the clock signal to complete the completion of the t signal to the length of the mother's early bit, the signal trace 10 is wired on the layer 丨 " on the line = 1.7 to form a crossover point ⑴ . And integrated circuit, the method shown in “1” and “2”, C6 remains substantially unchanged. The values of Cl, C3, C5, and C are considered. The term “crossover point” is used.

11510twf.ptd Page 10 200426560 V. Description of the invention (6) (crossover p〇 signal line crosses or crosses with the vertical plane, below, left int) 丨 The force product crosses, and the right wire is ten. Settlement examples, components. Or higher printed electrical signals refer to the clock signals being parallel to each other-some medium capacitors, jumpers and multiple jumpers are connected at a lot of rates as shown in the figure (for example, a similar electrical circuit of a circuit pack is at 107 and 111). The length of the memory bit length is one clock point and one real transistor as shown in the figure. 1GHz includes the path 'there are additional phases in the middle of this phase or multiple phases; it usually refers to such a location where the electricity is charged.' The theory of line-to-line; has nothing to do with a specific reference plane or direction (such as: superior). The same signal traces can intersect words, and multiple different signal traces can also cross the fixed number traces. The integrated circuit 300 is relatively low. The clock trace 101 in a small area carries the core clock signal (which has a typical clock frequency). However, the PCBs used in the present invention or using a certain operating frequency means that the crossover point can guide the signal at this frequency. Additional capacitance is created over the line length. Layers, and possibly adjacent ones, although the interlayers (one or more layers) considered in the present invention, in these middle gates they change the ^ along the given clock trace. Reference reference line 3 0 3 and 305 are wired in The signal traces are on both sides of 〇1, and the wiring is similar to that of ground traces 103 and 105. "Reference trace π can carry any appropriate reference potential and includes ground traces. The reference traces 303 and 305 in the figure have the same width W and both keep approximately the same distance D from the signal trace 丨 〇1, as in the case of the ground traces 103 and 105 as shown in Figure 1. It is usually possible to obtain equal uniform unit length capacitors ㈡ and ，, where C1 = C3. A jumper point 1 1 3 usually results in a jumper position that includes two additional jumper points 3 007 a and 3 0 7 b, at which signal traces 1 009 are jumpered respectively.

1151〇twf.ptd Page 11 200426560 V. Description of the Invention (7) Refer to traces 303 and 305. The reference traces 303 and 305 become narrower at their respective junctions 307a and 3 0 7b, and their width values become the new value "W2,". In the configuration shown in the figure, the reference traces are engraved with an arc or an arc. Slots 309a and 3 009b. These two grooves are symmetrically distributed on both sides of the reference tracks 3 〇3 and 305, so as to obtain new widths at the crossover points 307 a and 3 0 7 b. The value ψ 2. Notches 3 0 9a and 30 9 b are used to reduce the width of the reference traces 3 03 and 305 respectively, so the capacitance at the junction points 3 07a and 30 7) will be correspondingly correspondingly increased. And C4 are reduced to C7 and ⑶, respectively. In particular, the reduced capacitance c? Is used to offset the additional capacitance C5, the purpose is to maintain the unit length capacitance value, ie. C7 + C5 = C1. In a similar way The reduced capacitance C8 is used to offset the additional capacitance C6, the purpose is to ensure that the unit length capacitance value is ㈡, that is: = =. In short, at the crossover point μ related to the crossover point 113. And: test: Second, engraving grooves on the production lines 303 and 305 can reduce the clockwise gas-rich electrical valley (for example: reduce a to c? And u to cs) so that j 饧% pulse- Adjacent signal trace capacitance (For example: C5 and ⑶), * Crossover 1 1 3 clock traces 1 〇1 Capacitance in essence, 疋 network uniform unit length capacitance. Λ Bei specializes in the desired clock — symmetrical placement and symmetry The shape of the arc-shaped groove provides — valley compensation and the simplicity of reducing the width of the conductive traces. 仃 Electrical power = a few biases to maintain electrical and mechanical and trimming the traces) are sufficient to achieve the required shape. At this time, the square $ 'J can be used, and any desired result appears. The angle of the arc groove will cause the angle and side of the square groove to be changed to round%. Consider ::: Turn ^ so that the V trace is open

H51〇twf.ptd Page 12 200426560, description of the invention (8) a single groove to achieve the required wiring treasure _ side groove notch method for each groove = = 'Ran': a when the sound began to say white It is also possible to use a smaller size. In order to achieve the ^ # ten pieces, the size of a single arc groove on one side needs to be larger than expected; To reduce the length of the arc, a smaller arc radius can be used, but the side sample The result may cause the edge of the trace to be sharpened. The flow chart of the 4th Λ Λ using Λ to optimize the capacitance of the clock network capacitance according to the present invention = ί 〇 As described in the first block 401 1 ° Let's talk about the circuit description of f * ~ integrated circuit. The circuit description can be provided in any of many formats well-known to those skilled in the art, such as any appropriate hardware description. Language (hdl). The hardware description language (HDL) does not include, for example, the register transfer level (rtl), verii is called hardware description language 4. As shown in a block 403 below, the register transfer level hardware description language The encoded file has been improved by Xiao Yuyi ’s input of the input map and the net list program. Uses circuit diagram input and network list tools such as the master graphics software (Mentor Graphics) to provide a database and a network list program to generate a database and a network ^ The database describes the components of the circuit. The network list describes Element 2 = 2 link (111 ^ 1 ^ 〇111 ^ (^ 1〇11). Circuit diagram input and network list II 1: Use any appropriate format such as Ascu code (American Standard Code for Information Interchange) or similar Yttrium Tian Tian 2 described in the next box 40 5, circuit diagram input and network list database one or two diagrams and wiring tools for wiring the chip. Drawing and wiring tools for

Page 13 1 Example is the virtuos〇R series of ^ 9 drawing tools provided by Cadence Design System Company. The reason why they are effective is that they contain all the design project offices 200426560 V. Invention description (9) Various polygons required. These design projects include Stacked photomask layers, transistors, interlayer conductive interconnects, or vias. Auto-routing tools or other similar tools can be used to design interconnects such as Cadence Custom Chip Assembly Router. As shown in block 407, the drawing and routing tool provides a wiring library output eaves case, also called tape output (t a p e 〇 u t) ". The wiring library archive may conform to an industry standard format such as GDS II or similar. The G D S I I = slot format is also called the Kay code stream (c a 1 m a s t r e a m) π format. This format was first developed by the Kay code branch of General Electric Company. The format right is now vested in c a d e n c e Design Systems. Additional processing steps, such as a design rule inspection program, can also be used to determine if the wiring information file is consistent with the design product provided by the wafer fab. Wiring information = The file can be "changed" or modified to ensure that the design rules used are met. : -Block 409 ′ The final wiring library right case is sent to the factory for confirmation of the photomask, and the final wiring and wire resource groove case finally generates crystal 4. In the integrated circuit design process, the corresponding clock network optimizer function is used. The implementation form of the invention is the function of the optimizer. It is used as the control file. I, 'is most commonly used by the pulse network to interpret the selected form or all forms of the program and coding tools. 'Broadcast case 411 incorporates certain functions' such as: in the case of the present invention; how the tool implements a special crossover point to reduce the reference trace width, and how to make a groove on the identified. The control file 411 includes the test wiring or the reference wiring coding and the maintenance of the program of the clock pulse wiring and the white pulse wiring jumper.

ZUUH-ZOJOU V. Description of the invention (10) " ------- Decrease phase with each crossover point As another embodiment, the program code of the reference track width is self-coded. The program 4 1 3 or a similar program to report the clock network optimizer function can be used as an application, the purpose is to identify / contact poor, it modify the entire wiring database file to substantially keep every clock go and reduce The corresponding reference trace width is small, so that it has a uniformity capacitance of 2 each before it is sent to the factory. Wiring Database File Figure 5 shows the best clock network: Also? change. The optimizer application program 413 _ bucket & state control file 411 or clock network type coding can be used for any suitable // flat code f-like function flow chart 50. The disk drive, floppy disk, etc.), the optical media office such as: magnetic media (tape, magnet, etc.), electronic media (random disk drive: memory, optical disc drive the media he now knows or later invented) Buying memory, etc.), etc., or it identifies or recognizes one or more crossover blocks 501. It can be sure that there is at least one crossover point clock routing sheet f $ 50 3, and Ye Suanju is in the next block. 505. Calculate the cross-capacity (1 such as C3 and C5 and C6). In the next block 5 0 7, find :, check the additional power ^ (for example: reduce the reference trace width related to the crossover point, the home is ^ reduce the width, trim the trace, and connect the groove: r For wiring block 50 9, use the parameter for reducing the width of the wire for the purpose of setting a square compensation. The box 50b 5 0 9 can be connected to your storage every time to achieve the electric power. Operational wiring library has been identified in the two; or, please refer to Figure 6 and block diagram 6. Now, it means that the reference signal trace opening history according to the present invention how to eliminate the "h" way With internal clock

11510twf.ptd Page 15 200426560

V. Description of the invention (11) Timing related to skew. The block diagram 6 0 0 shows two consecutive logical blocks, a logical block 16 1 and a logical block 2 600 2 ′, both of which are part of a pipelined data circuit. As in the embodiment described in connection with Figure 2, data is transferred from logic block 601 to the next logic block 602, and is transferred in synchronization with the internal clock signals LCLK 1 604 and LCLK2 605, which are supposed to be synchronized. Data is transferred from logic block 16 0 1 to logic block 2 600 2 through the data bus 6 03. At this time, it is assumed that the data bus 6 0 3 is valid and the bus should be latched at point A: double single 2 6 0 2. At point b, the data is no longer valid on the data bus 6 0 3. For ease of description, the signal LCLK2 60 5 is described as accelerated because the traces are notched at the jumper points according to the present invention. In this way, there is an ascending boundary of the interlocking data at point A. In contrast to the case of point C, the situation of point C is shown by the dashed line in the figure. The non-compensated internal clock routing has an ascending boundary. As a result of applying the present invention to a clock distribution signal (not shown) near a buffer circuit (not shown) of the signal LCLK2 605, its operation is synchronized with the signal LCLK 1 604. Therefore, at point B605, the effective data can be latched before the second row 60 3 can clear the effective lean material. Fig. 6 is not only one embodiment of many different implementation forms of the present invention, and is used to detect and correct the timing problem of the integrated circuit caused by the non-uniform clock capacitance. According to the following example, after the clock network capacitor is optimized, the benefits can be improved. At this time, the clock running at the crossover point can be modified to obtain the clock signal going 1 ;;: "Additionally, the additional capacitance of the signal wiring is cancelled. At the clock frequency, the clock routing; the early length capacitor. At higher cores it will Significantly changed, the door endurance road characteristics will not increase significantly at the modified crossover point when rising. In this way,

200426560 V. Description of the invention (12)-f At a higher clock frequency, the core clock signal exhibits more uniform capacitance characteristics per unit length as the clock speed increases. In addition, because the negative capacitance effect is eliminated or controlled, the designer is more free to implement the routing work of the signal traces across the clock traces. Although the present invention is described in detail, specific preferred implementation forms are adopted, but other forms or changes may also be implemented and should be included in the scope of the present invention. For example, in addition to automatic changes or computer people including control software, applications, etc.-changes The invention is also suitable for circuit designers to manually change the square i 22, 52. The invention also considers reducing the reference trace to achieve capacitance compensation ... the type and size of the groove, or the simplest of the conductive trace; ί trace It is expected that the signal will be routed along the signal line. II. Finally, those skilled in the art should understand that, within the scope of God and God, they can use this example as a basis for completing the same specific examples as the present invention. Implementation :: and changes, so the scope of protection of the present invention is the other. Declaring the scope of the patent Although the present invention has been limited to the present invention by preferred embodiments, anyone familiar with this skill y 〇, but it is not used for: warm; internal 'should make some changes; and Runjin not = invention The spiritual yoke is defined by the scope of the attached patent application: Protection of the invention

IS 1151〇twf.ptd Page 17 ml

Brief description of the JUU diagram _ Body circuit (will not be used to describe the product of the traditional method of controlling the clock routing capacitance) The illustration on the local area of the circle Figure 3 shows a partial top view of the integrated circuit (ic). The method of the integrated electrical example is made. In the core flow chart of each unit length, the V product is based on the electric circuit book, which is used in the embodiment. The integrated circuit design of the s-Gangluo Electronics also integrates the optimization of the capacitance of the clock network. Optimization ;: Equation 2 ^ ^ describes the functional flowchart. And the drawing does not properly chart the pipelined system according to the present invention. [Schematic description] 100, 300: Integrated circuit '1〇1: Clock trace layer, log, 5: Ground trace, 107, 111: Ground trace, 1 0: Signal Routing, 113, 30 7a, 307b: jumper, 20 0 :: block diagram, 201, 202: compilation block 1, compilation block 2 20 3 ·· data bus, 20 4, 20: Internal clock signals LCLK1, LCLK2, 30 3, 30 5 ·· Reference traces, 309a, 30gb: Notch, 4 0 0: Integrated circuit design program, 401: Circuit description of integrated circuit,

200426560 Schematic description 4 0 3: Circuit diagram input and network list, 4 0 5: Drawing and wiring tools, 4 0 7: Integrated circuit wiring database, 4 0 9. · Send the final wiring database of integrated circuit to Chip manufacturer, 4 1 1: Clock network optimizer control file, 4 1 3: Clock network optimizer application, 5 0 0: Clock network optimizer application 4 1 3 General function flow chart of program coding, 5 0 1: Identify jumper, 5 0 3: Calculate capacitance of unit length of clock trace with jumper, 5 0 5: Calculate additional capacitance of unit length at jumper , 5 0 7: Calculate the corresponding reference trace width reduction parameters required for capacitance compensation, 5 0 9: Apply the calculated reference trace width reduction parameters to the wiring database file, 600. · Block diagram , 601, 602: logic block 1, logic block 2, 60 4, 605: internal clock signals LCLK1, LCLK2, 6 0 3: data bus

Cl, C2, C3, C4, C5, C6: Capacitance, D: Distance between signal trace and ground trace, W: trace width, W2: width at the crossover point.

11510twf.ptd Page 19

Claims (1)

-------- Application scope of patent _ 1 · An integrated circuit (I 〇_ includes:) 4-pulse network capacitor optimization method, including identifying clock traces and four-edge clock strikes Shiji; ~ Any crossover points between traces, where each clock alignment is masked by the reference traces on both sides of the spring that can be routed at that time; in order to identify the crossover points The value of Rifeng capacitor will be given. Inch-pulse routing, spring power valley is reduced to the reference trace setting F 申 Declares that the integrated circuit clock network electrical power described in item 1 of the patent $ li, q clock trace capacitance is reduced to the reference trace The capacitor 1L is included at the identified crossover point to reduce the width of the reference trace. _ # / +. According to the integrated circuit clock network electrical method described in item 2 of the scope of patent application, wherein the method of reducing the width of the reference trace includes trimming the electrical reference trace. Jade —4 • The method for optimizing the clock network t of the integrated circuit as described in item 3 of the scope of the patent application, wherein the method of trimming the reference wiring includes grooving a reference line. 5 · The method for optimizing the lightning capacity of the integrated circuit clock network as described in item 2 of the scope of the patent application, further including: obtaining the unit of the clock line with the identified crossover point and signal line Length capacitance; find the additional capacitance between the clock trace and the signal trace at the identified crossover point; find the reference trace that needs to be used at the identified crossover point to offset the additional capacitance The amount by which the width of the line is reduced; 200426560 VI. The scope of the patent application is reduced by the reference at the identified crossover point 6. As described in item 5 of the scope of the patent application; 2 optimization methods, including: The program receives the integrated circuit wiring knowledge formula is to identify the jumper point, and then calculate the unit length capacitance of the applied pulse trace, calculate the additional capacitance when the jumper is identified, and calculate the reference trace. The amount of width reduction "Subtraction between ports: the application program modifies the wiring database to complete the reference trace width capacity optimization method: the clock circuit of the integrated circuit described in the 5th item performs a wiring When wiring, the wiring tool is the wiring database of the body and the road; the control file of the clock network capacitance; and the control file for optimizing the integrated circuit is used to perform the ^ don't cross ^ points The unit of long-term clock routing "," L rejuvenation "has the additional capacitance to identify the jumper :::: Calculate the clock routing and signal routing The control channel I cloth: 丄: routing The amount of width reduction; and small. And the wiring device to reduce the width of the reference trace_ The method of adding the first- and power-receiving circuits to the integrated circuit includes: both sides; a ground trace is wound to the clock trace on the first layer The crossover point of the line; the pulse of the line and the winding, the letter on the second layer! H51〇twf .ptd between tiger tracks Page 21 200426560 VI. Patent application scope Reduction of the first and the first-Jishan respectively 9. If the width of the first joint of the patent application scope. The above method 'wherein the winding method includes adding to the integrated circuit wires such that they have approximately equal widths and =;-equal to the second ground path. The distance of the giant's holographic line is approximately I. If the method on the eighth road of the scope of the patent application, the method further includes: 1. Adding a circuit to the integrated circuit to generate a circuit wiring database; The library performs the coding operation; the coding can determine the jumper point, repair, and reduce each of the-and second ground traces = negative material library to be at the jumper point II · as in the patent application method , Where the executive editor 2 = added to the case of integrated electric clock network optimizer control rights _: = Fang ^ includes: executive application 12. If the scope of the patent application for the tenth household; described 『雷 、 = tool. The method on the road, where the method of performing coded wrestling :: Add to the integrated circuit has completed two distributions:% ㈣-The most clockwise method of the clock network, where the reduction goes separately: add the circuit to the integrated The to-side of each of the electrical and second ground traces includes: notching at the nth position as described in item 8 of the scope of the patent application. The method on the road further includes: · circuit /〗, add to the integrated circuit to find the unit length capacitance along the clock line; find the additional power between the clock line at the crossover point Page IblOtwf.ptd 200426560 6. The scope of the patent application; and the reduction of the width of the first and second ground traces required at the crossover point to offset the additional capacitance. 15 · — a kind of integrated circuit, including ... a clock trace located on the first layer, the distance between the clock trace and the first and second reference traces is approximately equal; a signal trace located on the second layer Above, the signal trace crosses this clock trace; and the first and second reference traces, in addition to the reduced width, • if the patent application 1 and the second reference trace are • if the patent application has approximately 16 17 18 kinds of pulse lines are incorporated into the carrier, where the program code is a first program code * point, the unit length capacitance of the first private code line and the corresponding winding at that time; an additional capacitance caused by a third program code line A fourth program code has approximately the same phase range as the 15th item. They have a uniform unit length when the range is 15th. ^ 亍 In the circuit cloth includes: 'Identification signal' is calculated with the ###### Line equal width. In the integrated circuit, a groove is formed at the place where the first pulse is routed. The integrated circuit, wherein the time capacitance. Line database program. At least one crossover between the media trace and the clock trace of the clock trace. ΛΛ ^ The second clock point of the clock trace—the second reference trace—is calculated in each and the count of the nose. In order to offset a crossover point, additional capacitance should be passed at each of the crossover points to signal the signal. 200426560 6. Reduction of the width of the corresponding first and second reference traces required by the patent application 19 · The media incorporated in the circuit wiring database program code as described in item 18 of the scope of the patent application, wherein the program code further includes: a fifth program code, modifying the circuit wiring lean database to The calculated width reduction is used to reduce the respective first and second reference trace widths. 2 0 The media incorporated in the program code of the circuit wiring database as described in item 19 of the scope of the patent application, wherein the fifth program code is the corresponding first and second reference path at each crossover point. The line arrangement is notched. 11510twf.ptd Page 24