200418184 玫、發明説明 【發明所屬之技術領域】 是關二一種半導體裝置以及其製造方法，特別 電二：：可緩和發生於實際動作領域最外周之溝渠底部 法。-木中’並抑制耐壓惡化之半導體裝置及其製造方 【先前技術】 屬氧^2^顯示以溝渠構造之1"通道型功率则FET(金 菊虱化+導體場效電晶體）為例之習知半導體裝置。 之沒型料導體基板21上設置由N型外延層所構成 么° 7頁域22，在其表面設置P型通道層24。通道層24 :在整個實際動作領域均以相同深度形成，在實際動作領 立或夕卜的诵;替爲 。 、層24周端部，則設有確保耐壓用之p+型領域 设置貫穿通道層24且到達至汲極領域22之溝渠2?， 法閘極氧化肤3 1覆蓋溝渠27之内壁，並設置由充填至溝 木27之多晶矽所構成的閘極電極33。在鄰接溝渠27 道層24夺而r 」逍 〆成有N -型源極領域3 5，在彼此相鄰的兩單 兀之源極領域35間的通道層24表面上形成p+型主㉟ 領域。另夕卜/、s 丑ί安觸 、 在通這層24則由源極領域3 5沿著溝渠π形成 通逼領域（無圖示）。以層間絕緣膜36覆蓋閘極電極33，並 °又置接觸源極領域35以及主體接觸領域34之源極電極 蒼照第13圖至第]8圖，係顯示以溝渠構造之Ν通 315154 200418184 型功率MOSFET為例之習知半導體裝置製造方法。 在第13圖中，係在N+型半導體基板21上積層…型 外延層亚形成汲極領域22。在實際動作領域外之預定通道 層24周端部植入擴散高濃度之p型雜質，以形成h型領 此外，又於整面以摻雜量1 0】3注入等雜質後， 擴散形成P型的通道層24。 第1 4圖至第1 5圖係顯示形成溝渠之步驟。 ^产為^ Μ圖中’藉由CVD(化學氣相成長）法全面形成厚 二 ^ : A 之 NSG(N〇n-d〇Ped Silicate Glass)的 CVD 氧化 26 Μ亚以光阻膜所形成之料覆蓋除了作為溝渠開口部 Η 的部分’ #由乾蝕刻去除部分之CVD氧化膜25， 形成通_域24外露之溝渠開Ml 乳膜200418184 Description of the invention [Technical field to which the invention belongs] This is a semiconductor device and a method for manufacturing the same, in particular Electric 2: It can relax the trench bottom method that occurs at the outermost periphery of the actual operation field. -Munaka 'and a semiconductor device that suppresses deterioration of withstand voltage and its manufacture [prior art] belongs to oxygen ^ 2 ^ shows a channel-type power FET (golden chrysanthemum + conductor field effect transistor) with a trench structure Examples are known semiconductor devices. A conductive substrate 21 made of an N-type epitaxial layer is provided with an N-type epitaxial layer, and a P-type channel layer 24 is provided on its surface. Channel layer 24: It is formed at the same depth throughout the actual action field, and leads or chants in actual action; instead, it is. At the end of the layer 24, a p + -type area for ensuring pressure resistance is provided. A trench 2 through the channel layer 24 and reaching the drain area 22 is provided. The gate oxide skin 3 1 covers the inner wall of the trench 27 and is provided. The gate electrode 33 is made of polycrystalline silicon filled into the trench 27. In the adjacent trench 27, the channel layer 24 captures r ", and there is an N-type source region 35. A p + type main region is formed on the surface of the channel layer 24 between two adjacent source regions 35. . On the other hand, on the 24th layer, the source area 3 5 forms a through-force area along the trench π (not shown). The gate electrode 33 is covered with an interlayer insulating film 36, and the source electrodes in contact with the source area 35 and the main contact area 34 are arranged in accordance with FIGS. 13 to 8], which show the ditch structure of the N-pass 315154 200418184 A conventional method for manufacturing a semiconductor device is described as an example of a power MOSFET. In FIG. 13, the N-type semiconductor substrate 21 is laminated with a... Type epitaxial layer to form a drain region 22. A high-concentration p-type impurity is implanted at the 24-peripheral end of the predetermined channel layer outside the actual operation field to form an h-type collar. In addition, after the impurity is implanted on the entire surface with a doping amount of 10] 3, P is diffused to form P. Type of channel layer 24. Figures 14 to 15 show the steps for forming a trench. ^ Production is ^ In the Μ picture, the thickness is formed by CVD (chemical vapor growth) method. ^: A of NSG (Nondium Ped Silicate Glass) CVD oxidizes 26 Μ sub-photoresist film. Cover the part except the trench opening Η '#The part of the CVD oxide film 25 is removed by dry etching to form the exposed trench 24 M1 emulsion film
在第15圖中，以CVD氧化膜25 系或HBr系翁麵斜、蓉玉 、〇作為遮罩亚赭由CF 蝕刻，以形成二 開口部％白勺石夕半導體基板進行乾 .渠27。 貝牙通通層24且深度達到沒極領域22的溝 層二，係進行假氧化而於溝渠27内壁與通道 曰Μ表面形成氧化 ^^^^^^# ^? ^^^^^ ^^^^^ 之後，形成閘極氧化膜3即羊^與咖氧化膜25。 厚度_百入1“《3/王面進行熱氧化以形成 第1 7圖係形成埋設於溝；巨 在整面上附著無摻雜的多晶吩層”之::極電極33。亦即： 车化’並形成問極電極33。之後在無遮罩的 315154 200418184 並殘留埋設 十月況下對附著於整面之多晶矽層進行乾蝕刻 於溝渠2 7内之閘極電極3 3。 第1 8圖係藉由光阻膜所構成的冷 曰 μ 力乂的遮單選擇性地以摻雜 置1 〇 —離子植入硼，並於形成p +型 丄 < 主體接觸領域3 4後， 去除光阻膜PR。 ν之後，以新的光阻膜伙作為遮罩使預定的源極領域 以及閉極電極33露出，以摻…〇15離子植入石申，並 在與溝渠27鄰接的通道層表面24上形成ν+型源極領域 J 5後，去除光阻膜。 然後，藉由 CVD 法使 BPSG(B〇r〇nPh〇sph〇rusSiiicate 阻::層附著於整面，以形成層間絕緣膜％。之後，以光 、二遮罩至少在閘極電極33上殘留層間絕緣膜36。 二_錢裳置使紹全面附著，以形成與源極領域35以及 :虹接觸領域34接觸之源極電極37。藉此，可在實際動 作領域中配置多數個M〇SFE丁28。 ' 士口此’在習知溝渠槿土告 苒木構以之MOSFET中，設於實際動作 域，溝渠27以及助咖T28的深度幾乎全部均一 如’芩照專利文獻1 )。 在㈣渠構造的高耐塵MOSFET中，於源極電極與汲 电極之間’施加以汲極電極為正電慶之電源電塵的狀態 _對間極电極施力σ閾值電壓以上之驅動電塵日寺，合在、、八 :溝渠的通道層形成通道領域，電流即透過通道領^產2 *動，而使MOSFET呈現導通狀態。 另-方面’於源極電極與汲極電極之間，施加以汲極 315154 7 200418184 電極為正電壓之電源電壓的狀態了，當施加於閘極電極的 驅動電壓在閾值電壓以下時，M0SFET會呈現關斷狀態。 (專利文獻1) 〜 曰本特開平9-2705 12號公報（第1〇頁，第23圖 【發明内容】 Θ (發明所欲解決之課題） 在習知清渠構造的高耐壓M〇SFE丁中，在關斷狀態 下耗k層會如第1 2圖虛線所示從反向偏壓的通道層24 與及極領域22界面之pN接合處開始擴展。將此耗盡層設 定為施加驅動電壓v〇時的耗盡層。因為汲極領域 外，層的雜質濃度& p型通道層24之雜質濃度低，因此 夕數的耗&層會向汲極領域22方向延伸，並保持汲極電 壓。 在此狀悲下’因為最外周溝渠27a之底部邊緣，與實 際動作領域内之、巨 + + _ 、 ^ <溝渠27之底部邊緣栢比較具有最大的電 /昜強度， 故在此會發生電場集中。 以下說明其原因。 首先各溝渠底部邊緣的電場強度E可以下列公式表 y"J\ 。 E = VO/d 在上遠公式中，d為從各溝渠的底部邊緣到最接近的 /及極領域側的耗盡層端之距離，如第]2圖所示，在最外周 溝木—7a中距離為d ]卜在實際動作領域的溝渠2 7中則為 8 315154 200418184 dl2 〇 力汗，在汲極領域 盡層連成-體，但擴展於通道層24的：：岸5與鄰接之耗 有絕緣膜的溝渠27内部，故可藉由溝：層不會擴展至設 重““ h I J猎由溝渠27分離。在實 乍項域中，由於係藉由各溝渠27分 皙、、1疮α、 雖且通道層24的雜 貝/辰度比汲極領域22之雜質濃度高， 94古人加 又耗姐層在通道層 方向擴展的情況較少，而是往極極 屏。X + A A 22方向大幅擴 展另—方面在最外周溝渠的外側，直至 24 A u ^ 且主P +型領域 一，係以20心程度的距離充分 渠27的限制，因此耗告 由於/又有溝 域…J 層在通運層24側會比實際動作領 =更谷易擴展。此外’在岐之施加電塵v。㈣況下， =Γ::分的耗盡層的寬度d。係、在實際動作領域内 ，、外圍皆為大致均一的寬度。 亦即，在最外周溝渠⑺的外側，耗盡層容易往通道 =4側擴展的部分，耗盡層往沒極領域％側的擴展係比 員際動作領域内少。因此，底部邊緣至耗盡層的距離會比 溝七27窄（dl2>dll)。另外，在實際動作領域内，由於溝 渠27係以等間隔配置，且耗盡層呈均等擴展，所以只有最 外周的溝渠27a到耗盡層的距離dn較短。 亦即’各溝渠的底部邊緣之電場強度E係以最外周溝 渠27a最強，而在此產生電場集中。因此，會使汲極源極 間（在IGBT中則為集極射極間）的而十慶惡化，且高溫時會發 生名員足值下滑的問題。 具體來况，第]9圖為表示集極射極間耐壓（vces)與 315J54 9 200418184 溫度（叫的特性圖。根據本圖，場集中，周圍溫度 在75度以上日"CES值會下降，而成為負的溫度特性。因 此無法改善特性…電場集中而產生之集極射極間的财 壓惡化情形也會造成相當大的問題。 (解決課題之手段） 本發明係鑑於上述課題而創作者，帛i樣態係具備 有：設於基板表面之雜質領域；設於該雜質領域周端部之 南濃度雜質領貫穿前述雜質領域之多數個溝渠構造的 弟1電晶冑；以及在前述第i電晶體外周與前述高濃度雜 質領域料，且設置在比前述第1電晶體更深之位置的第 第2樣態係具備有配列多數個第i電晶體單元的實P 動：領域^第U晶體單元係由：設於半導體基板表面 之弟1雜貝領域；設於丽述第i雜質領域周端部之高濃度 雜質領域；貫穿前述第1雜質領域之溝渠；至少覆蓋前二 •溝渠内之絕緣膜；由埋設於前述溝渠内之半導體材：： 鄰接設置於前述溝渠之第2雜質領域所構成； 周與前述高濃度雜 體更深之位置的第 具備有在前述實際動作領域最外 質領域接近’且設置於比前述第1帝曰 ^ 丄电日日 2電晶體。 心丨;六 、 ％日日股平7L的實際 動作領域，單W由：設於作為波極領域之—導電型半導 體基板表面之逆導電型雜質領域的通道層；設於前述通首 層周端部之高濃度雜質領域；貫穿前 ，， 、 牙刖述通逗層之溝渠；至 315154 10 200418184 >、復孤幻述溝、内之絕緣膜；由埋設於前述溝渠内之半導 月豆材料所構成之電極；及由在前述通道層表面與前述溝渠 鄰接設置之一導電型源極領域所構成， 且具備有在前述實際動作領域最外周與前述高濃度 才隹貝7員域接近，且设置於比前述第1電晶體更深之位置的 第2電晶體。 另外’本發明之特徵為前述第2電晶體與前述高濃度 雜質領域的間隔距離，俏μ B . 知比則述弟1電晶體彼此間的間隔 距離短。 _ 卜本么月之捋徵為：前述第2電晶體係設置於t| 前述高濃度雜質領域更淺之位置。 另外，本發明之特糌 试為構成前述第2電晶體之前述^ 渠開口寬度係比構成前诚楚，$ 弟1黾晶體之前述溝渠的開口 | 度寬。 另外，本發明之特科 4、，、、* 又為在前述第1電晶體的外周以及 為知述弟2電晶體的内@ 前述第1電晶體深之第 _ ^ _ 設有比前述第2電晶體淺但比 電晶體。 另外，本發明之特種丈 溝渠開口寬度，係比構& 寬度寬，而比構成前述$ 窄。 為：構成前述第3電晶體之前述 前述第1電晶體之前述溝渠開口 2電晶體之前述溝渠開口寬度 第4樣態係使用開D ώ 見度不同的遮罩，並藉由於同一 步驟中在第1溝渠與該窠]$ ^ 溝知外周形成比該第1溝渠更 深之第2溝渠。 π 315]54 200418184 第5樣態係具備有：在半導體基板表面形成第1雜質 領域之步驟；形成貫穿前述第1雜質領域之多數個第1溝 渠的步驟；同時在該第1溝渠最外周形成比該第1溝渠更 深之第2溝渠的步驟；在前述第1以及第2溝渠内壁形成 絕緣膜之步驟；在前述第1以及第2溝渠埋設半導體材料 之步驟；及與前述第1以及第2溝渠相鄰接而形成第2雜 質領域的步驟。 第6樣態本發明為具備有：在作為汲極領域之一導電 型半導體基板表面形成逆導電型通道層之步驟；形成貫穿 前述通道層之多數個第1溝渠的步驟；同時在該第1溝渠 最外周形成比該第1溝渠更深之第2溝渠的步驟；在前述 第1以及第2溝渠内壁形成閘極絕緣膜之步驟；形成由埋 設於前述第1以及第2溝渠之半導體材料所構成之電極的 步驟；及在前述通道層與前述第1與第2溝渠相鄰接而形 成一導電型源極領域的步驟。 > 另外，本發明之特徵為在前述第1以及第2溝渠形成 步驟中，前述第2溝渠係形成比前述第1溝渠更寬之遮罩 開口。 另外，本發明之特徵為在前述第1以及第2溝渠形成 步驟中，在前述第1溝渠外周以及前述第2溝渠内周同時 形成比前述第1溝渠深但比前述第2溝渠淺之第3溝渠。 另外，本發明之特徵為前述第3溝渠的遮罩開口寬 度，係比前述第1溝渠之遮罩開口寬度寬，比前述第2溝 渠之遮罩開口寬度窄。 315154 200418184 【實施方式】 以下以溝渠構造之N通道型功率m〇SFET為例詳細說 明本發明之實施例。 首先，參知、弟1圖至第8圖，說明本發明第1實施例 之半導體裝置。 第1圖為本實施形態之半導體裝置之剖視圖。具有第 1電晶體8以及第2電晶體8a之半導體裝置，係由：半導 體基板1、2、通道層4、高濃度雜質領域4a、溝渠7、”、 間極氧化膜11、閘極電極13、源極領域15與金屬電極17 所構成。 千等體暴板係在In FIG. 15, a CVD oxide film 25-based or HBr-based Weng plane oblique, sapphire jade, and 〇 are used as masks to etch the CF substrate to form a two-portion Shi Xi semiconductor substrate for channel 27. The bayonet pass through layer 24 and the trench layer 2 reaching the depth area 22 are pseudo-oxidized to form oxidation on the inner wall of the trench 27 and the surface of the channel ^^^^^^ # ^? ^^^^^ ^^^ ^^ After that, a gate oxide film 3, that is, a sheep film and a coffee oxide film 25 is formed. Thickness_Hundreds of 1 "<3 / King surface is thermally oxidized to form Fig. 17 Figure 8 is formed to be buried in a trench; giant an undoped polycrystalline phen layer is adhered to the entire surface" :: electrode 33. That is, it is turned into a car 'and the interrogation electrode 33 is formed. Afterwards, the polycrystalline silicon layer attached to the entire surface was dry-etched in the gate electrode 3 3 in the trench 27 under the condition of 315154 200418184 without remaining buried in October. Fig. 18 is a photoresist film composed of a cold μ-force mask, which is selectively doped with 10-ion implanted boron, and forms a p + -type 丄 < main contact area 3 4 After that, the photoresist film PR is removed. After ν, a new photoresist film is used as a mask to expose the predetermined source region and the closed electrode 33, implanted with Shi 15 ions, and formed on the channel layer surface 24 adjacent to the trench 27 After ν + source region J 5, the photoresist film is removed. Then, a BPSG (BoronPhosphorusSiiicate resist :: layer is adhered to the entire surface by a CVD method to form an interlayer insulating film%. After that, at least the gate electrode 33 is left with light and two masks. Interlayer insulating film 36. Second, Qian Sangzhi makes full attachment to form the source electrode 37 in contact with the source area 35 and the rainbow contact area 34. By this, most MoSFEs can be configured in the actual operation area. Ding 28. 'Shikou this' is set in the actual operating area in the MOSFET of the known trench trench structure, and the depth of the trench 27 and the helper T28 is almost the same as that of the 'Shao Patent Patent Document 1'. In a high-dust-resistant MOSFET with a trench structure, a state in which a power source dust with a drain electrode as a positive electrode is applied between a source electrode and a drain electrode. Dust Temple, together in the channel layer of the trench, the channel field is formed by the channel layer, and the current flows through the channel channel, and the MOSFET is turned on. On the other hand, between the source electrode and the drain electrode, a state in which the drain electrode 315154 7 200418184 is a positive voltage is applied. When the driving voltage applied to the gate electrode is below the threshold voltage, the M0SFET will Turns off. (Patent Document 1) ~ Japanese Unexamined Patent Publication No. 9-2705 12 (Page 10, Figure 23 [Contents of the Invention] Θ (Problems to be Solved by the Invention) High-pressure-resistant MoSFE Ding, which is known for clear channel structures In the off state, the k-consuming layer will expand from the pN junction of the reverse-biased channel layer 24 and the polar region 22 as shown by the dotted line in Fig. 12. This depletion layer is set to apply driving. Depletion layer at voltage v0. Because the impurity concentration of the layer & p-type channel layer 24 is low outside the drain region, the consumption & Drain voltage. In this state, 'because the bottom edge of the outermost trench 27a has the largest electric / 昜 strength compared to the bottom edge of the trench 27a in the actual action field, so Electric field concentration will occur here. The reason will be described below. First, the electric field intensity E at the bottom edge of each trench can be expressed by the following formula y " J \. E = VO / d In the Shangyuan formula, d is from the bottom edge of each trench to The distance between the depletion layer end closest to the polar field side, as shown in Fig. 2 It is shown that the distance is d in the outermost ditch wood—7a.] In the trench 27 of the actual action area, it is 8 315154 200418184 dl2 〇 Lihan, it is connected to the body in the drain area, but extends to the channel layer. 24 :: shore 5 and the adjacent trench 27 with an insulating film, so it can be separated by the trench: layer will not extend to the setting weight "" h IJ hunting is separated by the trench 27. In the real project domain, due to the system With 27 points in each trench, 1 sore α, although the impurity concentration of the channel layer 24 is higher than the impurity concentration of the drain region 22, it is less common for the 94 ancient people to consume the sister layer to expand in the direction of the channel layer. , But towards the polar screen. The X + AA 22 direction greatly expands the other side-on the outside of the outermost ditch, up to 24 A u ^ and the main P + type field 1 is a distance of 20 cores to fully limit the limit of 27, Therefore, due to the fact that there is / and there is a ditch ... J layer will be easier to expand on the transport layer 24 side than the actual operation collar. In addition, 'electric dust is applied to Qi's v. In this case, = Γ :: minute is exhausted The width of the layer d. The width is approximately uniform in the actual operation area and the periphery. That is, in the outermost groove On the outer side of the ridge, the depletion layer easily expands toward the channel = 4 side, and the depletion layer expands less toward the% side of the nonpolar area than in the interpersonal action area. Therefore, the distance from the bottom edge to the depletion layer will be greater than the groove. 7 27 narrow (dl2> dll). In addition, in the field of actual operation, since the trenches 27 are arranged at equal intervals and the depletion layer expands evenly, only the outermost trench 27a has a short distance dn to the depletion layer. That is, the electric field intensity E at the bottom edge of each trench is the strongest at the outermost trench 27a, and an electric field concentration occurs here. Therefore, it will worsen between the source of the drain (between the collector and the emitter in the IGBT), and the problem of a decline in the full value of a famous person at high temperatures. Specifically, the first] Figure 9 shows the voltage between collector and emitter (vces) and the temperature of 315J54 9 200418184 (called the characteristic chart. According to this figure, the field concentration, the ambient temperature is above 75 degrees, and the "CES value will be It decreases and becomes a negative temperature characteristic. Therefore, the characteristics cannot be improved ... The deterioration of the financial pressure between the collector and the emitter due to the concentration of the electric field also causes a considerable problem. (Means for Solving the Problems) The present invention is made in view of the above problems. As a creator, the 帛 i system has: an impurity field provided on the surface of the substrate; a south-concentration impurity collar provided at the peripheral end of the impurity field runs through most of the trench structures of the aforementioned impurity field; and The second aspect of the outer periphery of the i-th transistor and the high-concentration impurity region, and disposed deeper than the first transistor is provided with a real P operation arranged with a plurality of i-th transistor units: field ^ The U-th crystal unit consists of: the first impurity region on the surface of the semiconductor substrate; the high-concentration impurity region on the periphery of the i-th impurity region; the trench that runs through the first impurity region; covers at least the first two • Insulation film in the trench; semiconductor material buried in the aforementioned trench :: It is composed of the second impurity region adjacent to the aforementioned trench; the second one is located deeper in the periphery of the aforementioned high-concentration impurity in the aforementioned actual operation field The most exoplasmic field is close to and is set more than the above-mentioned first emperor ^ 丄 日 日 日 心 2 transistor. Heart 丨; VI,% Japan-Japan shares flat 7L actual action field, single W: set as the wave pole field -The channel layer in the field of reverse-conductivity impurities on the surface of the conductive semiconductor substrate; the high-concentration impurity area provided at the peripheral end of the first layer; before, through, the trenches through the passivation layer are described; to 315154 10 200418184 >, an insulating film inside the complex ditch, and an electrode composed of a semiconducting moon bean material buried in the aforementioned trench; and a conductive source field provided adjacent to the aforementioned trench on the surface of the aforementioned channel layer It has a second transistor that is close to the 7-member high-density shell in the outermost periphery of the actual operation area and is located deeper than the first transistor. In addition, the present invention It is characterized by the distance between the aforementioned second transistor and the aforementioned high-concentration impurity region, which is very small. The ratio of the distance between the first transistor and the second transistor is short. _ The sign of the month is: The transistor system is set at a shallower position in the aforementioned high-concentration impurity region. In addition, the special test of the present invention is to form the aforementioned ^ channel opening width of the second transistor, which is greater than that of the former. The opening of the aforementioned trench | degree is wide. In addition, the special section 4 ,,,, * of the present invention is on the outer periphery of the aforementioned first transistor and on the inner side of the aforementioned transistor 2 @The aforementioned first transistor deep The _ ^ _ is provided to be shallower but larger than the aforementioned second transistor. In addition, the opening width of the special trenches of the present invention is wider than the width of the structure and narrower than that of the aforementioned $. In order to form the aforementioned trench opening of the aforementioned first transistor and the aforementioned trench opening of the aforementioned first transistor, the fourth aspect of the aforementioned trench opening width of the transistor is to use a mask with different visibility, and use the same step in the same step. The first ditch and the 窠] $ ^ know that the outer periphery forms a second ditch deeper than the first ditch. π 315] 54 200418184 The fifth aspect includes: a step of forming a first impurity region on the surface of the semiconductor substrate; a step of forming a plurality of first trenches penetrating the aforementioned first impurity region; and forming at the outermost periphery of the first trench A step of a second trench deeper than the first trench; a step of forming an insulating film on the inner walls of the first and second trenches; a step of burying a semiconductor material in the first and second trenches; and the steps of the first and second trenches Steps in which trenches are adjacent to form a second impurity region. A sixth aspect of the present invention includes: a step of forming a reverse conductive channel layer on the surface of a conductive semiconductor substrate that is one of the drain regions; a step of forming a plurality of first trenches penetrating the channel layer; and simultaneously in the first A step of forming a second trench deeper than the first trench on the outermost periphery of the trench; a step of forming a gate insulating film on the inner walls of the first and second trenches; and forming a semiconductor material embedded in the first and second trenches An electrode step; and a step of forming a conductive source region on the channel layer adjacent to the first and second trenches. > In the present invention, in the first and second trench forming steps, the second trench is formed with a mask opening wider than the first trench. In addition, in the present invention, in the first and second trench forming steps, a third trench deeper than the first trench and shallower than the second trench is simultaneously formed on the outer periphery of the first trench and the inner periphery of the second trench. ditch. In addition, the present invention is characterized in that the mask opening width of the third trench is wider than the mask opening width of the first trench and narrower than the mask opening width of the second trench. 315154 200418184 [Embodiment] In the following, an embodiment of the present invention will be described in detail using a trench-structured N-channel power mMOSFET as an example. First, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 is a cross-sectional view of a semiconductor device according to this embodiment. A semiconductor device having a first transistor 8 and a second transistor 8a is composed of a semiconductor substrate 1, 2, a channel layer 4, a high-concentration impurity region 4a, a trench 7, a ", an interlayer oxide film 11, and a gate electrode 13. , Source region 15 and metal electrode 17. The isotope plate is
， ，，—入 X | 牙百 XI - /J 外延層以形成汲極領域2。 9 ，道層4為選擇性地在沒極領域2表面植入p型·^ 、擴政領域。在與該通道層4之冓 成iS、# β /荐木7鄰接的領域上，男 风通逼領域（無圖示）。通道層，，， — 入 X | 百 百 XI-/ J epitaxial layer to form the drain region 2. 9, track layer 4 is selectively implanted in the surface of the non-polar area 2 p-type ^, expansion area. In the area adjacent to the iS, # β / recommend wood 7 of the channel layer 4, the male style is in the area (not shown). Channel layer
之實際私从 4係在配置有M〇SFET8、S 、不動作領域全面形成相同的 — 外之通、s 又且在貫際動作領i 、遏層4周端部，設有用以確 薄沮Ί n〜— 隹保耐壓之P +型領域4a 木、7 a係貝牙貫際動作領域的i甬、者昆 極領域2,—般而言係在半導 、層4且物 是條肤。奋 绔版基板上圖案化為格子狀5 ，'際動作領域内設有多數個溝-:巨7 — 有比溝渠7更深之溝渠b另外，溝二7’在其外心 比溝渠7寬。藉此，如後述—般 V的開口寬心 溝渠7”a。但是，該溝"a只 ：形亡深度不同έ 在其他步驟中藉由改變蝕刻條件等來形：：·即可’亦' 315154 13 200418184 閘極氧化膜U至少係設於與通道層4相接的溝渠7、 7a内壁’並配合驅動電壓設定為數百A的厚度。因為閘極 氧化膜U為絕緣膜’而形成由設置於溝渠7、乃内之閘極 電極13與半導體基板所夾持之M〇s構造。 閘極電極13係由埋設於溝渠7、7a之多晶石夕所構成， 在該多晶石夕中導入有用以實現低電阻化之p型雜質。· 極電極13係延伸至包圍半導體基板周圍之閑極連姓電極 無圖示），ϋ與設於半導體基板上之開極焊墊電極相連 結。 源極領域為在鄰接溝渠7、7a之通道層4表面植入 ^型雜質後之擴散領域，與覆蓋實際動作領域的金屬源極 電極17相接觸。另夕卜，在鄰接之源極領域15間的通道層 4表面D又置P+型雜質擴散領域之主體接觸領域} 4，以杏 現基板電位之穩定化。 € 層間絕緣膜16為使源極電極17與閉極電極Ο絕接， 鑀設置時至少需覆蓋閘極電極13，而將其中—部分= 渠開口部。 爲 源極书極1 7係對紹等進行激鐘而圖案化為所希望的 形狀’並覆蓋於實際動作領域上，而與源極領域15以： 體接觸領域1 4相接觸。 錯此，可在實際動作領域内藉由溝渠7配置多數個 1MOSFET8,第2M〇SFET8a係藉由溝渠八配 】.M〇SFET8的外周。第2助咖心係設置成比第^晶 體8深且比p +型領域4a淺。 宅曰日 315154 14 200418184 此外，如後所詳述一般，第2M〇SFET8a係與P +型領 域4a接近配置。具體來說，第2]\4〇8?£丁8&與？ +型領域 4a間的間隔距離W2，係比第1MOSFET8彼此間的間隔距 離，或是第1MQSFET8與第2M〇SFET8a的間隔距離（也就 是單元節距）W1短。另外，P +型領域4a與第2MOSFET8a 亦可相接。 在該溝渠構造的高耐壓MOSFET中，係於源極電極與 汲極電極之間，在施加以汲極電極為正電壓之電源電壓的 狀態下，對閘極電極施加閾值電壓以上的驅動電壓時，在 沿著溝渠形成的通道層上會形成通道領域，電流係透過通 道領域進行流動，而MOSFET則形成導通狀態。 另一方面，在源極電極與；及極電極之間，在施加以ί及 極電極為正電壓之電源電壓的狀態下，當施加於閘極電極 的驅動電壓在閾值電壓以下時，MOSFET會呈現關斷狀 態。 本發明之特徵，係在第1MOSFET8的外周設置比第 1MOSFET8深且比P +型領域4a淺之第2M〇SFET8a，並與 P +型領域4a形成接近配置。 在上述溝渠構造的高耐壓MOSFET中，耗盡層係在關 斷狀態下，如第1圖虛線所示從反向偏壓之通道層4與汲 極領域2界面之PN接合處進行擴展。以此耦盡層作為施 加驅動電壓Vo時之耗盡層。汲極領域2之N-型外延層， 相較於P型通道層4其雜質濃度較低，故大多數之耗盡層 會往〉及極領域2方向延伸’並保持汲極電壓。 315154 200418184 在本實施形態中，除τ μ 1示了叹置弟2M〇SFET8a並盥Ρ +刑 領域4 a接近配置之外盆 八他構成要素皆與先前相同。此如 施加相同的驅動電壓V〇眸，紅杳昆人 土 v〇 %，耗盡層會如第12圖所示一 擴展，耗盡層整體的厚度也會形成與先前相同之d。。又 但是’在本實施形態中，f 2m〇sfet 1MOSFET8深，比p +形顏埒/ ^ 不比弟 1項域4a次，且與P +型領域4 近配置。由於通道層4 #伽· 丨 、 、眉4係與P +型領域4a相連接，且p I領域4 a較 >米之故，耗禽声-， 7现層會如圖所不一般沿著p + 4a與沒極領域2的界面 ^ I展在此，猎由將第2M〇SFETh 與P +型領域4a的間隘拓絲、以 巨雔W2设定成其他m〇SFEtThe actual private line 4 is completely the same in the field configured with MOSFET8, S, non-action — outside the pass, s, and at the end of the four-week end of the continuous action collar i, containment layer, is provided to confirm Ί n ~ — 隹 pressure-resistant P + type field 4a wood, 7 a is the shell tooth interstitial motion field i 甬, the kunji field 2, generally speaking in the semiconducting, layer 4 and the object is a bar skin. The Fenban version of the substrate is patterned into a grid-like pattern 5, and there are a plurality of trenches in the field of interactivity-: Ju 7-there are trenches deeper than trench 7 b. In addition, trench 2 7 'is wider than trench 7 in its outer center. With this, as will be described later-the opening V wide-centered trench 7 "a. However, the trench" only: the depth of death is different. In other steps, it can be shaped by changing the etching conditions, etc. :: "You can also 315154 13 200418184 The gate oxide film U is provided at least on the inner walls of the trenches 7 and 7a connected to the channel layer 4 and is set to a thickness of several hundred A in accordance with the driving voltage. The gate oxide film U is an insulating film and is formed by The Mos structure sandwiched between the gate electrode 13 and the semiconductor substrate provided in the trench 7. The gate electrode 13 is composed of polycrystalline stones buried in the trenches 7 and 7a. A p-type impurity is introduced to reduce the resistance. · The electrode 13 extends to the electrodes surrounding the semiconductor substrate (not shown), and is connected to an open-pad electrode on the semiconductor substrate. The source area is the diffusion area after implanting ^ -type impurities on the surface of the channel layer 4 adjacent to the trenches 7 and 7a, and is in contact with the metal source electrode 17 covering the actual operation area. In addition, in the adjacent source area The surface D of the fifteen channel layers 4 is provided with a P + type impurity diffusion collar. The main contact area} 4, the potential of the substrate is stabilized. € The interlayer insulating film 16 is to isolate the source electrode 17 from the closed electrode 0, and at least the gate electrode 13 needs to be covered during installation, and- Portion = channel opening. Patterning the Shao and other clocks for the source book 17 series and patterning it into the desired shape 'and covering the actual action area, and the source area 15 with: Body contact area 1 4 In this case, a plurality of 1MOSFETs 8 can be arranged through the trench 7 in the actual operation field, and the 2MMOSFET8a is configured through the trench.] The outer periphery of the MOSFET8. The second helper heart is set to be higher than the ^^ The crystal 8 is deeper and shallower than the p + -type field 4a. House 315154 14 200418184 In addition, as will be described in detail later, the 2MOSFET8a is close to the P + -type field 4a. Specifically, the second 2] \ 4 〇8? The distance W2 between the + type field 4a is shorter than the distance between the first MOSFETs 8 or the distance between the first MQSFET8 and the second MOSFET 8a (that is, the cell pitch) W1. In addition, the P + -type area 4a and the second MOSFET 8a may be connected. The height of the trench structure is high. A voltage MOSFET is formed between a source electrode and a drain electrode, and a driving voltage equal to or higher than a threshold voltage is applied to the gate electrode when a power supply voltage with a positive voltage applied to the drain electrode is applied. On the channel layer, a channel field is formed, current flows through the channel field, and the MOSFET is turned on. On the other hand, between the source electrode and the electrode, a positive voltage is applied to the electrode and the electrode. In the state of the power supply voltage, when the driving voltage applied to the gate electrode is below the threshold voltage, the MOSFET will be turned off. A feature of the present invention is that a second MOSFET 8a is provided on the outer periphery of the first MOSFET 8 which is deeper than the first MOSFET 8 and shallower than the P + -type region 4a, and is arranged close to the P + -type region 4a. In the above-mentioned trench structure high-withstand voltage MOSFET, the depletion layer is extended from the PN junction at the interface of the reverse-biased channel layer 4 and the drain region 2 as shown by the dotted line in FIG. 1. This decoupling layer is used as a depletion layer when the driving voltage Vo is applied. The N-type epitaxial layer in the drain region 2 has a lower impurity concentration than the P-type channel layer 4, so most of the depletion layer will extend in the direction of "> and the pole region 2 'and maintain the drain voltage. 315154 200418184 In this embodiment, except that τ μ 1 shows that the 2MMOSFET 8a is used and the P4 area is close to the configuration, the other components are the same as before. For example, if the same driving voltage V0 is applied, the soil of Hongying Kun people v0%, the depletion layer will expand as shown in Figure 12, and the entire thickness of the depletion layer will be the same as before. . However, in this embodiment, f 2m0sfet 1 MOSFET 8 is deeper than p + shape face / ^, which is 4a times less than the first term domain, and is arranged near the P + type domain 4. Because the channel layer 4 #Ga, 眉, and Mei 4 are connected to the P + type field 4a, and the p I field 4 a is more than> meters, the bird's sound is consumed, and the 7 current layer will not follow the general The interface between p + 4a and Promise Sphere 2 is shown here. The hunting will be based on the extension of the 2M SFETh and the P + type 4a, and the W2 will be set to other mSFEt.
間隔距離W1以下，怂描#斤J 攸構成第2M〇SFET8a之溝渠7a的底 部邊緣擴展到汲極領域？ 6 _ 項兑2的耗盡層會以往p+型領 推之形態擴展。藉此，在彳 一 仕保符有與先則相同之耗盡 d 〇的實際動作領诚闲^ ^ 刀μ錢周&部，從構成第2M〇SFET8a之 7a的底部邊緣到擴張到汲 ' 貝-乂〜之耗进層邊緣的距 ft比先前的dU(參照第12圖）更大。亦即，第！圖所 不之取外_^溝# 73之底部邊緣的電場強度E2( = V()/d2)會 小於先前之最外周滏 巨 曰 门溝木27a底部邊緣的電場強度 E 1 (二Vo/d 1 1) ’而得以绥知# ^ #电％木中。错此可抑制汲極源極 間的耐壓惡化’並大幅降低高溫時之額定值下滑的問題。 第2圖顯示具體之集極射極間耐塵與周圍溫度的特性 (VCES ITa h H ：)。貫線為本實施形態之半導體元件的特 性’虛線為先iil技術之特性 ^^ ^ Ά 根據此圖係错由採用本發明 之構造，使周圍溫廑（丁，m押产旧丄％ + 又（ia)保彳寸在取大額定溫度之150度的 315154 16 200418184 範圍内而VCES為正的溫度特性。相較於先前周圍溫度在 75度以上就會成為負的溫度特性，其特性已有大幅的改 善。 另外’在本發明實施形態中係以MOSFET為例進行說 明’但在IGBT中，本發明之構造也適用並可獲得同樣的 效果。 接著利用第3圖至第8圖說明本發明之半導體裝置製 造方法。 本發明之半導體裝置製造方法，係包括：在形 領域之一導電型半導體基板表面形成逆導電型通道層之步 驟；形成貫穿通道層之多數個第1溝渠，同時在第1溝渠 外周形成比第1溝渠更深之第2溝渠的步驟；纟第i以及 苐2 >冓渠内壁形成閘極絕緣膜之步驟；形成由土里設於第工 以及第2溝渠之半導體材料所構成之電極的步驟；在通道 層與弟卜苐2溝渠相鄰接而形成導電型源極領域之步驟。 本發明第1步驟如第3圖所示，係在作為汲極領域2 之-導電型半導體基板表面形成逆導電型的通道層4。 在N+型矽晶半導體基板i積| N，外延層以形成汲 極領域2。在實際動作領域外之預定通道層4周端部，植 入^農度P型雜質，以擴散形成p +型領域h。接著，全 面以接雜量心植入棚等雜質後，擴散形成？型通道岸4。 外证^卜，為1哪時，若在P +型石夕半導體基板設置心 2層，再：其上積層"-型外延層而形成集極領域，即可 ^ 步風貫施後序步驟。 315154 17 200418184 如第4圖至第5圖所示，本發明之第2步驟係形成貫 穿通道層之多數個f 1溝渠，並於第】溝渠最外周同時形 成比第1溝渠深之第2溝渠。 本步驟為本發明之特徵，係使用溝渠開口部之開口寬 度不同的遮罩而在同一步驟中形成深度不同的第玉溝渠7 與第2溝渠7a。 弟4圖中，係全面藉由CVD法形成厚度為數千A的 灸 NSG(N〇n-d〇Ped Silicate Glass)的 CVD 氧化膜 5。然後於 形成溝渠開π # 26以外的部分覆蓋由光阻膜所形成之遮 罩，並藉由乾蝕刻去除部分之CVD氧化膜5，以形成通道 領域4露出之溝渠開…、“。此時，若為同一独刻條 件’則利用開口部寬度越大溝渠深度越深的特性，並使用 具有實際動作領域最外周之第2溝渠開口部&的開口寬度 大於實際動作領域内之第2溝渠開口部6之開口寬度之圖 案的遮罩進行曝光。具體而言，假設第1溝渠開口部6為 >〇,5/^左右，則第2溝渠開口部^則為1_〇/^左右。另. 外’第2溝渠形成第2溝渠開口部&，俾充分接近卜型 領域^近。亦即’使第2溝渠開口部6a與P +型領域4a 的㈣㈣W2 ’比實際動作領域则冊的單元節距， 亦即* 1溝渠開口部6彼此間或是第1溝渠開口部6與第 2溝渠開口部6a間的間隔距離W】短。 在第5圖中，枰r, ^ ，、义CVD氧化膜5為遮罩並藉由cF系 或ΗΒ]·系氣體1虫刻第】、第2溝渠開口部6、6a之石夕半導 ^基板’以形成溝渠7、7a。此時，如前述—般因最外周 315154 200418184 之開口覓度較覓’故會形成卜裳1、盖泣 曰化成比乐1溝渠7更深之第2溝渠 7a。亦gp ’ 一次的蝕刻會形力兩種深度不同的溝 7、乃。 藉此，在之後的步驟中於溝泪 ’、 々、屏木内埋，又閘極電極】3時， 和實際動作領域最外周夕μ & + & /、盘$ ” ^隹士备 卜周之閑極電極（溝渠7a)底部邊緣的電 %集中現象。 拆岁。A奴形成淥度不同的溝渠，必須增加用以 = 步驟，本發明中係藉由使用變更開口寬 度的遮罩而在同一 j> ^ , v ^中同時形成深度不同的溝渠。亦 即，只要變更溝渠蝕刻 再卞 n ^ j的^罩圖案，便可利用先前的製程 未緩和溝渠7a底部邊緣的電場集中現象。 本發明之第3步驟‘楚< m .；,7 Ί加抵 ^私如弟6圖所示，係在第i、第2溝 木7、7a内壁形成閑極絕緣膜。 進行假氧化以在第巨 ^ J% 4 β- iSi ^ λ ^ /木、弟2溝渠7a内壁與通道 層4表面形成氧化膜（益圖示 蝕刻損傷，之後，再拉、，去除乾蝕刻時所造成的 5。 S虫刻去除該氧化膜與CVD氧化膜 接著 王面進行敎氧化，计麥 厚度為700A > 、、 亚對炙驅動電壓而形成例如 八之間極氧化膜丨！。 如第7圖所+ , ^ 1以及第2、、t $ $明之第4步驟係形成由埋設於第 /冓渠之半導體材料所組成之命搞。 使無推雜之多晶矽層附著於入电° 的磷以達到古道+ 、王面，植入並擴散高濃度 巧V电率化，並形成 罩之情況下蝕列— 甲°笔極1 3。之後在無遮 |挪刻附者於全面 夕曰 1溝渠7、第ο夕日日石夕層，而留下埋設於第 弟2溝渠7a之問極電極]3。 315154 19 200418184 如第8圖所示，本發明之第5步驟係在通道層4 1、第,2溝渠7、7“目鄰接而形成-導電型源極領域二 罩使基板定化，藉由光阻膜所構成的遮 罩适擇性地以#雜量_離子植人辦雜質，並於形成ρ + 型主體接觸領域1 4後，去除光阻膜。 …，後，使用新的光阻膜，並以可露出預定之源極領域 14閘極電極13的方式加以覆蓋，並以摻雜量1()】5離子 ，植入石申’而在與第！、第2溝渠7、7a鄰接之通道層4表 面形成N+型源極領域15後，去除光阻膜。 接著，藉由CVD法於全面附著BpsG(B〇· Phosphor Silicate Glass)層，以形成層間絕緣膜μ。之 後，以光阻膜為遮罩並至少在閘極電極13上留下層間絕緣 膜16。之後藉由麟裝置使紹附著於全面，形成與源極領 域1 5以及主體接觸領域i 4接觸之源極電極1 7。 接著，參照第9圖至第u圖說明本發明之第2實施 ^列。第2實施例係設置位於第iM0SFET8之外周且第 2MOSFET8a 之内周的第 3M〇SFET8b。第 3M〇sFETsb 係 比第1M0SFET8深，而比第2M0SFE丁8a淺。 第9圖係第2實施例之構造。 第2實施例之溝渠型功率M〇SFET係由半導體基板 1、2、通道層4、溝渠7、7a、7b、閉極氧化膜η、閘極 電極1 3、源極領域]5與金屬電極丨7所構成。 另外，由於溝渠7、7a、7b以外的構成要素係與第】 實施例相同，故省略詳細說明。 315154 20 200418184 、，在^導體基板i上的沒極領域2表面設置通道層4, 並在通迢層4的周端部設置P +型領域4a。 、溝渠7係貫穿通道層4到達汲極領域2，一般而言係 在半導體基板上以格子狀或是條紋狀圖案化。 數巧的1 Λ "" U ’位於貫際動作領域最外周附近之複 數周的溝渠’係設置成越向最外周溝渠深度越深的形態。 =相較於實際動作領域内的，丨溝渠7， =周的第2溝渠7a較深。此外，比第2溝渠 而比第1溝渠7深夕楚q、、蓉、、Η 且 y糸7b係設在第1溝渠7的外周 ’ * &的内周。亦即，溝渠係在實際動作領域最外 周附近，即在本實施形態之笋 取1 .取外周與其内側之2周中，形 成冰度逆漸變深的構造。該 寺冰度之例子可列舉，第1溝 木7一、、勺2.5# m，第3溝渠7b=約2 一 約3"m左右。關於 · 弟2溝渠 n ^ #木7a，係與第1實施形熊相 冋，比P+型領域4a淺且與p +刑与a / ) 、相 „ 土項域4a形成接近配置。 ，第J溝渠7b的開口寬 卜卜穿。i ^ 度係比弟1溝渠7寬， 弟2屢^: 7 a窄。藉此如 的溝竿7 後述一般，可同時形成深度不同 h再木/、7 a、7 b。但是，太 且清泣 只要溝渠7b比溝渠7深， 1溝木7a比溝渠7b深即可 姓刻條件而形成。 亦可在其他步驟中藉由變更 =所有的溝渠7、7b'7a内壁中設置問極氧化膜⑴ "里。又夕晶石夕以形成閘極電 、 5, , m 免極13。該閘極電極1 3係延伸 至j包圍半導體基板周圍之間 认、上、治1 逆、、、口電極（热圖不），而盥設 + V體基板上之閘極焊塾帝 一 又兒極（無圖示）相連結。 315]54 21 200418184 在鄰接溝渠7、7b、7a的通道層4表面植入N+型雜質， 並設置與覆蓋實際動作領域之金屬源極電極1 7相接觸之 源極領域1 5。此外，在鄰接之源極領域1 5間的通道層4 表面，設置P +型雜質擴散領域之主體接觸領域1 4，以使 基板電位穩定化。 層間絕緣膜1 6為使源極電極1 7與閘極電極1 3間絕 緣，至少必需覆蓋閘極電極1 3，而於溝渠開口部留下其中 一部分。 源極電極1 7係藉由進行鋁等之濺射而圖案化為所希 望的形狀。並覆蓋實際動作領域上，與源極領域1 5以及主 體接觸領域1 4相接觸。 藉此，在實際動作領域内可藉由溝渠7配置多數個第 1MOSFET8，第 2M〇SFET8a則是藉由溝渠7a配置於第 1MOSFET8的外周。另外，在第1MOSFET8外周且為第 2M〇SFET8a内周的部分，配置有比第1MOSFET8深但是 鲁比第2MOSFET8a8淺的第3M〇SFET8b。第2M〇SFET8a係 比第1電晶體8深，而比P +型領域4a淺。 另外，第2MOSFET8a係與P +型領域4a形成接近配 置。具體而言，第2M〇SFET8a與P +型領域4a的間隔距離 W2，係設定成比其他MOSFET8之間（或是第1與第 3MOSFET)的間隔距離W1短。第2M〇SFET8a亦可與P + 型領域4a相接。 在本實施例中’係以虛線表不在關斷狀悲下’攸她加 驅動電壓Vo時形成反向偏壓的通道層與汲極領域界面的 3]5154 200418184 7接合處開始擴展的耗盡層。耗盡層的擴展以及耗盡 覓度do與先前相同，故 、 包日日體8b之底部邊緣至耗 ^層的距離d3會形成dl>d3>d2。亦即電場強度⑴也會形 、E2<E3<E1，而得以使電場強度的變化緩和。 " 藉此可抑制汲極源極間的耐壓惡化，並 時所發生之額定值下滑的問題。 皿 另外’本發明之實施例係以M〇SFET為例 但亦適詩咖丁，並可獲得相同的效果。 接著以第10圖、第u圖以及第 之半導體裝置的製造方法。另外，除了第…:2… 成步驟以外均盥第i奋 ’、 v -之溝渠形 ^ 、弟1貝施例相同，故省略其詳細說明。 第1步驟：係在作為汲極領域2之—導電型半導 板表面形成逆導電型通道 月且土 成型領域4a。 …"在通-層4的周端部形 置N =延二了的情況下’若在。+ 型碎半導體基板設 再於其上積層N-型外延層以形成集極領域 的蛞，即可在同一步驟中實施後序步驟。 / 2步驟：同時形成逐漸往實際動作領域最外周變深 之弟1、第3、第2溝渠的步驟（第1〇、u圖）。 本步驟係本發明之特徵，係使用溝渠開口 度不同的遮罩在同-步驟内形成第1溝渠7、第，、[巨 第3溝渠7b。 “薄知7a、 在第1 0圖中，係全面获出r d、本：^ Λ、 丁王囟糟由LVD法形成膜厚為數 之 NSG(N〇n‘d〇ped Silicate G 丨 ass)的 CVD 氣化脰 孔化犋。之後在 315154 23 200418184Below the separation distance W1, it is suggested that the bottom edge of the trench 7a constituting the 2MOSFET 8a extend to the drain region? The depletion layer of 6 _ item 2 will be expanded in the form of the previous p + lead. In this way, the actual action of depletion of d 〇 is the same as that of the first rule. ^ ^ The knife μ Qian Zhou & Department, from the bottom edge of 7a constituting the 2M SFET8a to the expansion to the drain. The distance ft from the edge of the shell to the layer is greater than the previous dU (see Figure 12). That is, the first! The electric field intensity E2 (= V () / d2) at the bottom edge of the outer edge of the figure is not smaller than ^ 沟 # 73 will be smaller than the electric field intensity E 1 (two Vo / d 1 1) '而 可以 催 知 # ^ # 电 ％ 木 中. If this is done, the deterioration of the withstand voltage between the drain and source can be suppressed, and the problem of lowering the rated value at high temperatures can be greatly reduced. Fig. 2 shows the characteristics of dust resistance and ambient temperature between specific emitters and emitters (VCES ITa h H :). The line is the characteristics of the semiconductor device in this embodiment. The dotted line is the characteristic of the first iil technology. ^^ ^ Ά According to this figure, the structure of the present invention is adopted to make the surrounding temperature 廑 (ding, m 产 production old 丄% + and (Ia) The temperature characteristics of VCES in the range of 315154 16 200418184, which is 150 degrees of the large rated temperature, and VCES is positive. Compared with the previous ambient temperature above 75 degrees, it will become a negative temperature characteristic. Significant improvement. In addition, 'the MOSFET is described as an example in the embodiment of the present invention', but in the IGBT, the structure of the present invention is also applicable and the same effect can be obtained. Next, the present invention will be described using FIGS. 3 to 8. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to the present invention includes the steps of forming a reverse conductive channel layer on the surface of one of the conductive semiconductor substrates in the field of forming; forming a plurality of first trenches penetrating through the channel layer; The step of forming a second trench deeper than the first trench on the periphery of the first trench; a step of forming a gate insulating film on the inner wall of the second trench; i and i2; forming a gate insulating film on the inner wall of the trench; and A step of forming an electrode made of a semiconductor material of 2 trenches; a step of forming a conductive source field in a channel layer adjacent to a dip 2 trench. The first step of the present invention is shown in FIG. Pole field 2-a conductive semiconductor substrate surface is formed with a reverse-conducting channel layer 4. A N + -type silicon semiconductor substrate is formed with an N | epitaxial layer to form a drain region 2. A predetermined channel layer 4 outside the actual operation field Around the end, P-type impurities are implanted to diffuse to form the p + -type field h. Then, the impurities are implanted into the shed and other impurities to form a? -Type channel bank 4. Foreign evidence, When is 1, if 2 cores are provided on the P + -type Shixi semiconductor substrate, and then: the "-type epitaxial layer is laminated on it to form the collector field, then the subsequent steps can be performed in one step. 315154 17 200418184 As shown in FIGS. 4 to 5, the second step of the present invention is to form a plurality of f 1 trenches penetrating the channel layer, and simultaneously form a second trench deeper than the first trench at the outermost periphery of the first trench. It is a feature of the present invention that a cover having a different opening width of a trench opening is used. In the same step, the first ditch 7 and the second ditch 7a with different depths are formed in the same step. The figure 4 shows that a moxibustion NSG (Nondop Silicate Glass) with a thickness of several thousand A is formed by CVD. CVD oxide film 5. Then, a portion of the trench opening π # 26 is covered with a mask formed by a photoresist film, and a part of the CVD oxide film 5 is removed by dry etching to form a trench opening exposed in the channel area 4 ... "". At this time, if the conditions are the same, the characteristics of the larger the opening width and the deeper the trench depth are used, and the opening width of the second trench opening & having the outermost periphery of the actual operation area is larger than the actual operation area. A mask with a pattern of the opening width of the second trench opening portion 6 inside is exposed. Specifically, it is assumed that the first trench opening 6 is about > 0,5 / ^, and the second trench opening ^ is about 1_0 / ^. In addition, the outer 2nd ditch forms the opening of the 2nd ditch, which is sufficiently close to the Bu-shaped area. That is, 'make the second trench opening 6a and + W2 of the P + type area 4a' than the unit pitch of the actual operation area, that is, * 1 trench openings 6 between each other or the first trench openings 6 and the first The distance W] between the two trench openings 6a is short. In Fig. 5, 枰 r, ^, and CVD oxide film 5 are masks, and cF-based or ΗB] · system gas 1 is engraved], and the second trench openings 6 and 6a are semiconductive. ^ Substrate 'to form trenches 7, 7a. At this time, as mentioned above, because the outermost periphery 315154 200418184 is more open, it will form Bu Chang 1, Gai Wei, and it will become the second ditch 7a deeper than Le 1 ditch 7. Also gp 'once etch will form two grooves with different depth. In this way, in the following steps, the trench tears 々, 屏, Pingmu are buried, and the gate electrode] 3 o'clock, and the outermost area of the actual action area μ & + & /, disk $ "^ 隹 士 备 卜The concentration of electricity% at the bottom edge of the weekly electrode (ditch 7a). Demolition. A slaves can form trenches with different degrees, which must be added to = steps. In the present invention, a mask is used to change the width of the opening. Trenches with different depths are simultaneously formed in the same j > ^, v ^. That is, as long as the mask pattern of the trench etch and n ^ j is changed, the electric field concentration phenomenon at the bottom edge of the trench 7a can not be mitigated by the previous process. In the third step of the present invention, "Chu <m.;, 7", as shown in Fig. 6, the idler insulating film is formed on the inner wall of the i-th and second trenches 7, 7a. An oxide film is formed on the inner wall of the ditch ^ J% 4 β- iSi ^ λ ^ / wood, brother 2 ditch 7a and the surface of the channel layer 4 (the etching damage is shown in the figure, and then pulled and removed to remove the 5 caused by dry etching The S etch removes the oxide film and the CVD oxide film, and then performs the radon oxidation on the king surface. The thickness of the wheat is 700A & g t, ,, and sub-pairs drive voltage to form, for example, an eight-pole oxide film 丨! As shown in Figure 7 +, ^ 1 and 2, and t $ $ The fourth step of the Ming is formed by buried in the / / 冓In the case of the semiconductor material composed of the channel, the non-doped polycrystalline silicon layer is adhered to the phosphorus at the electric angle to achieve the ancient road +, the king surface, and the high-concentration V-type is implanted and diffused to form a cover. Eclipse column — A ° pen pole 1 3. Later, in the uncovered | move the encloser to the full eve of the ditch 7, the first day of the day, and the eve of the day, leaving the interrogated electrode buried in the second channel 7a] 3. 315154 19 200418184 As shown in FIG. 8, the fifth step of the present invention is formed on the channel layer 41, the second, the trench 7, and the "7" mesh-the conductive type source field two covers fix the substrate, The mask formed by the photoresist film is selectively doped with # impurity amount ions to implant impurities, and the photoresist film is removed after the ρ + type body contact area is formed.…, And a new one is used. The photoresist film is covered so that the gate electrode 13 of the predetermined source region 14 can be exposed, and implanted with a doping amount of 1 () 5 ions, and implanted in Shishen ' First, after the N + -type source region 15 is formed on the surface of the channel layer 4 adjacent to the second trench 7, 7a, the photoresist film is removed. Then, a BpsG (B. Phosphor Silicate Glass) layer is fully attached by CVD to An interlayer insulating film μ is formed. After that, a photoresist film is used as a mask and at least an interlayer insulating film 16 is left on the gate electrode 13. After that, the substrate is attached to the entire surface by the Lin device, and the source region 15 and the main body are formed. The contact area i 4 contacts the source electrode 17. Next, a second embodiment of the present invention will be described with reference to FIGS. 9 to u. The second embodiment is provided with a 3MOSFET 8b located on the outer periphery of the iMOSFET8 and the inner periphery of the 2MOSFET8a. The 3MMOSFETsb is deeper than the 1MMOSFET8 and shallower than the 2MMOSFET 8a. Fig. 9 shows the structure of the second embodiment. The trench-type power MOSFET of the second embodiment is composed of a semiconductor substrate 1, 2, a channel layer 4, a trench 7, 7a, 7b, a gate oxide film η, a gate electrode 1 3, a source region] 5 and a metal electrode.丨 7. In addition, since the constituent elements other than the trenches 7, 7a, and 7b are the same as those in the first embodiment, detailed description is omitted. 315154 20 200418184. A channel layer 4 is provided on the surface of the non-polar region 2 on the conductive substrate i, and a P + type region 4a is provided on the peripheral end portion of the through layer 4. The trench 7 passes through the channel layer 4 to reach the drain region 2 and is generally patterned in a grid or stripe pattern on the semiconductor substrate. The number 1 Λ " " U ‘The ditch of a plurality of weeks, which is located near the outermost periphery of the inter-action area, is arranged in a form where the trench depth is deeper toward the outermost periphery. = Compared to the actual action area, the trench 7 is deeper than the second trench 7a of the week. In addition, q,, Rong,, and y 糸 7b are deeper than the second ditch 7 and are located on the inner periphery of the first ditch 7 '* &. That is, the ditch is near the outermost periphery of the actual action area, that is, the bamboo shoots of this embodiment take 1. The outer periphery and the inner two weeks of the trench form a structure that gradually reverses the depth of ice. Examples of the temple's ice degree can be listed as follows: the first ditch 7-1, the spoon 2.5 # m, and the third ditch 7b = about 2 to about 3 " m. About · Di 2 ditch n ^ # 木 7a, which is similar to the first embodiment, is shallower than P + type field 4a and forms a close configuration with p + penalty and a /), and the soil item field 4a., J ditch 7b The width of the opening is wide. The degree is wider than that of the ditch 1 and the ditch 2 and d 2: 7 a. This is similar to the ditch rod 7 described later, which can form different depths at the same time. 7 b. However, if the ditch 7b is deeper than the ditch 7, and 1 ditch 7a is deeper than the ditch 7b, the condition can be formed. It can also be changed in other steps by changing = all the ditch 7, 7b ' An interlayer oxide film 设置 is provided in the inner wall of 7a. A spar stone is used to form a gate electrode, 5, m, and 13. The gate electrode 13 is extended to j to surround the semiconductor substrate. The upper, lower, and upper electrodes are not connected (the heat map is not shown), and the gate electrodes on the toilet + V body substrate are connected to each other (not shown). 315] 54 21 200418184 In the adjacent trench N + -type impurities are implanted on the surface of the channel layer 4 of 7, 7b, 7a, and a source region 15 is provided in contact with the metal source electrode 17 covering the actual operation region. In the source region 15 of the channel layer 4 surface, the main contact region 14 of the P + -type impurity diffusion region is provided to stabilize the substrate potential. The interlayer insulating film 16 is for the source electrode 17 and the gate electrode. The 13 insulations must cover at least the gate electrode 13 and leave a part of the trench opening. The source electrode 17 is patterned into a desired shape by sputtering of aluminum or the like. In the operation area, it is in contact with the source area 15 and the body contact area 14. In this way, in the actual operation area, a plurality of first MOSFETs 8 can be arranged through the trench 7, and the second MOSFET 8a is arranged in the trench 7a. The outer periphery of the first MOSFET 8. In the outer periphery of the first MOSFET 8 and the inner periphery of the second MOSFET 8a, a third MOSFET 8b deeper than the first MOSFET 8 but shallower than the second MOSFET 8a8 is arranged. The second MOSFET 8a is a transistor that is smaller than the first It is 8 deeper and shallower than P + -type region 4a. In addition, the second MOSFET 8a is in close proximity to P + -type region 4a. Specifically, the distance W2 between the second MOSFET 8a and P + -type region 4a is set to be proportional Between other MOSFETs 8 (or 1st and The 3rd MOSFET) has a short separation distance W1. The 2MMOSFET 8a can also be connected to the P + -type field 4a. In this embodiment, 'it is indicated by a dotted line to indicate that it is not turned off.' When the driving voltage Vo is applied, a reverse voltage is formed. The depletion layer at the junction of the biased channel layer and the drain domain interface] 5154 200418184 7 begins to expand. The expansion of the depletion layer and the degree of depletion do are the same as before. Therefore, the distance d3 from the bottom edge of the sun-bodied body 8b to the depletion layer will form dl &d; d3 > d2. In other words, the electric field strength ⑴ will also be shaped as E2 < E3 < E1, so that the change of the electric field strength can be eased. " This can suppress the deterioration of the withstand voltage between the drain and the source, and the problem that the rated value drops at that time. In addition, the embodiment of the present invention uses MoSFET as an example, but it is also suitable for Shijiading, and the same effect can be obtained. Next, the semiconductor device manufacturing method of FIG. 10, FIG. U, and FIG. In addition, except for the first step: the second step, the second step, the second step, the first step, the second step, and the first step are the same. Therefore, detailed descriptions are omitted. The first step is to form a reverse conductive channel on the surface of the conductive type semiconducting plate which is the second of the drain area 4a. … &Quot; In the case where the peripheral end portion of the through-layer 4 is N = extended, it is' if there is. The + -type broken semiconductor substrate is provided with an N-type epitaxial layer laminated thereon to form a ytterbium in the collector field, and the subsequent steps can be performed in the same step. / 2 steps: At the same time, the steps of forming the first, third, and second ditches that gradually become deeper toward the outermost periphery of the actual action area (picture 10 and u). This step is a feature of the present invention, and a mask having a different opening degree of the trench is used to form the first trench 7, the first, the third trench 7b in the same step. "Bozhi 7a, in Fig. 10, rd, Ben: ^ Λ, Ding Wang, and Dang Wang, who formed a film thickness of NSG (N〇n'd〇ped Silicate G 丨 ass) by the LVD method. CVD gasification of pores and pores. After that, 315154 23 200418184
形成溝渠開口部AA 。丨以外的部分覆蓋由 並藉由乾餘刻去除部分之cvd氧 膜所形成之遮罩， 露出之溝渠開口部。此 、以形成通道領域4 開口部寬度越大則溝虫刻條件，則可利用 作領域最外周之第;if越：的特性 弟屢木開口部6a開口寬 圍之第3溝渠開口寬度 ·：匕配置灰其内 宮泠4沉班 弟3溝渠開口部6b之開 口寬度比配置於更内周之第！溝渠開口 之圖案的遮罩進行曝光。（6<6b<6a) 具體而言，將第〗溝渠開…的開口寬度例如形成 將二t右’將第3溝渠開口寬度⑼形成°.5心，而 ILt:部6a形成°.86…右的寬度。另外，形 成弟2溝^^開口部6a使第2、、鲁卩巨π I” ift 使弟2溝木付以與p+型領域“充分 接近。亦即’第2溝渠開口部64Ρ +型領域心會彼此接 近’而其間隔距離W2會比其他溝渠開口部彼此的間隔距 離W1小。 φ 在第11圖中，係以CVD氧化膜作為遮罩，並利用CF 系以及HBr系氣體對第i、第2、第3溝渠開口部6、化、 6b之矽半導體基板進行乾蝕刻，同時形成深度不同的溝渠 7、7a、7b。此時，如前述一般，因開口寬度會逐漸變寬， 故會形成比第1溝渠7更深的第3溝渠7b，以及比第3溝 渠7b更深的第2溝渠7a。亦即，可以一次的蝕刻形成3 種深度不同的溝渠7、7a、7b。之後，如在溝渠埋設閑極 電極1 3，即可使實際動作領域最外周的閘極電極（溝竿 底部邊緣的電場集中變化緩和。 315)54 24 ζυυ4ΐ»ΐδ4 —般而， 變更蝕刻欠"，如欲形成深度不同的溝渠，必須增加用以 縮小開件等之步驟，但是在本發明中係藉由階段性地 渠。亦即見度：而在同-步驟中同時形成深度不同的溝 可運用先緊可提供一種只要變更溝渠蝕刻的遮罩圖案，即 導I#梦¥ ^之製程緩和溝渠7a底部邊緣之電場集中的丰 置之製造方法。 如膜：係全面進行熱氧化並對應驅動電壓形成例 ^ A之閘極氧化膜11。（參照第6圖） 弟4步驟··係形成由埋設於 閑極：極丨3。(參照第7圖） 4構成之 極領域15，並：在通道層4鄰接溝渠7形成-導電型源 全面：二=間絕緣膜16。之後藉由_裝置使链 以形成與源極領域以及主體接觸領 觸之源極電極…而獲得如第9圖所示之最後構造。14接 h如上所述，藉由使则FET的深度形成階段性〜 :有效地緩和電場集中。此時，階段性地加深設置： 弟3、第2M〇SFET8部分的遷移領域係如前述一 ^水的 =逐漸使開口部變寬而在同—步驟中形成深度^同可藉 、。亦即’可與先前之製程相同，藉由一 /的溝 程來形f’因此在製程上可階段性地形成到光：：成製 :。但是’其目的若是在緩和電場集中，則只 〜的界 實施例所示之2階段程度即可。 /、而到第2 25 3)5]54 200418184 另夕卜，本實施型態係顯示於第1以及第2MOSFET8、 8a之間進行第3M〇SFET8b之一周配置的情形，但亦可配 置成複數周。另外，設置成複數周時，第3MOSFET8b之 深度無須全部相同，只要是具有比第1MOSFET8深且比第 2M〇SFET8a淺白勺深度，亦可設置成於其中階段性力口深的形 式。 (發明之功效） 根據本發明，第 2M〇SFET8a之溝渠深度係比第 1MOSFET8深，且與P +型領域4a接近酉己置，因此可緩和 實際動作領域之周端部之溝渠底部邊緣的電場集中。藉由 抑制電場集中可實現抑制汲極源極間（IGBT則為集極射極 間）之耐壓惡化的半導體裝置。 亦即，可抑制汲極源極間（IGBT則為集極-射極間）的 耐壓惡化，並大幅減少高溫時所產生之額定值下滑的問 題。 另外，根據本製造方法，可在同一蝕刻步驟中同時形 成深度不同的溝渠。亦即，不需增加製造步驟，即可利用 與先前相同的製程緩和底部邊緣的電場集中。亦即，具有 可輕易地提供一種可抑制汲極源極間（IGBT則為集極射極 間）的耐壓惡化，並抑制高溫時所產生之額定值下滑之導體 裝置之製造方法的優點。 另夕卜，係在第1MOSFET8與第2MOSFET8a之間，設 置具有兩FET之間之深度的第3M〇SFET8b，並針對實際 動作領域最外周附近之複數周溝渠進行階段性加深，如此 26 315154 200418184 一來，相較於只將最外周加深的情形，更能夠緩和電場集 中。此製程亦可藉由階段性地將最外周與外周的溝渠開口 寬度擴大，而形成在同一溝渠形成步驟中逐漸加深的溝 渠。 【圖式簡單說明】 第1圖係本發明之半導體裝置之剖視圖。 第2圖係本發明之半導體裝置之特性圖。 第3圖係本發明之半導體裝置製造方法之剖視圖。 第4圖係本發明之半導體裝置製造方法之剖視圖。 第5圖係本發明之半導體裝置製造方法之剖視圖。 第6圖係本發明之半導體裝置製造方法之剖視圖。 第7圖係本發明之半導體裝置製造方法之剖視圖。 第8圖係本發明之半導體裝置製造方法之剖視圖。 第9圖係本發明之半導體裝置之剖視圖。 第1 0圖係本發明之半導體裝置製造方法之剖視圖。 第1 1圖係本發明之半導體裝置製造方法之剖視圖。 第1 2圖係習知半導體裝置之剖視圖。 第1 3圖係習知半導體裝置製造方法之剖視圖。 第1 4圖係習知半導體裝置製造方法之剖視圖。 第1 5圖係習知半導體裝置製造方法之剖視圖。 第1 6圖係習知半導體裝置製造方法之剖視圖。 第1 7圖係習知半導體裝置製造方法之剖視圖。 第1 8圖係習知半導體裝置製造方法之剖視圖。 第〗9圖係習知半導體裝置之特性圖。 315154 200418184 21 1-12 >及極領域 4、 4a、24a P +型領域 5、 6 n 6a N 6b、26 溝渠開口 部 7 第 1溝渠 7a 7b 第 3溝渠 8 8a 第 2MOSFET 8b 11、31 閘極氧化膜 13、 14、34 主體接觸領域 15、 16、36 層間絕緣膜 17 27 溝渠 28 MOSFET 3 7 源極電極 27a 32 25 B曰 N+型矽晶半導體基板 通道層 CVD氧化膜 第2溝渠 第 1MOSFET 第 3MOSFET 3 3 閘極電極 35 源極領域 金屬電極（源極電極） 矽層 315154 28A trench opening AA is formed. The parts other than 丨 cover the mask formed by removing the part of the cvd oxygen film by dry etching to expose the trench openings. Therefore, in order to form the channel area 4, the larger the opening width is, the ditch engraving condition can be used as the outermost perimeter of the area; if more: the characteristics of the third ditch opening width of the opening width 6a: The configuration of the dagger is gray, and the opening width of the opening part 6b of the ditch 3 is lower than that of the opening 6b! The mask of the trench opening is exposed. (6 < 6b < 6a) Specifically, the opening width of the first trench is formed, for example, to form the second trench right, and the third trench opening width is formed to be. Right width. In addition, the opening 2a is formed so that the 2nd and the second largest Lu π I ”ift makes the 2nd groove“ close enough to the p + type region ”. That is, the "second trench opening 64P + type center will be close to each other", and the distance W2 will be smaller than the distance W1 between the other trench openings. φ In Figure 11, the CVD oxide film is used as a mask, and the CF semiconductor and HBr-based gases are used to dry-etch the silicon semiconductor substrates of the i-th, second, and third trench openings 6, 6b, and 6b. Trenches 7, 7a, 7b of different depths are formed. At this time, as described above, since the opening width gradually becomes wider, a third trench 7b deeper than the first trench 7 and a second trench 7a deeper than the third trench 7b are formed. That is, three types of trenches 7, 7a, and 7b having different depths can be formed in one etching. After that, if the idle electrode 13 is buried in the trench, the gate electrode (the electric field concentration change at the bottom edge of the ditch rod at the outer periphery of the actual action area can be moderated. 315) 54 24 ζυυ4ΐ »ΐδ4 — Generally, the etching defect is changed. ; If you want to form trenches with different depths, you must add steps to reduce openings, etc., but in the present invention, the trenches are staged. That is, visibility: while simultaneously forming trenches of different depths in the same step can be applied first. It can provide a mask pattern that can be etched by changing the trench, that is, the process of conducting I # 梦 ¥ ^ can ease the electric field concentration at the bottom edge of the trench 7a. Fengzhi's manufacturing method. Such as a film: the gate oxide film 11 is formed by performing thermal oxidation on the whole and corresponding to the driving voltage. (Refer to Figure 6.) Step 4: The formation is buried in the idle pole: pole 3. (Refer to FIG. 7) A pole region 15 composed of 4 is formed in the channel layer 4 adjacent to the trench 7-a conductive type source. Overall: two = inter-insulating film 16. Then, the device is used to form a chain to form a source electrode that is in contact with the source area and the main body, and the final structure shown in FIG. 9 is obtained. As described above, by forming the depth of the FET stepwise as described above: The electric field concentration is effectively alleviated. At this time, gradually deepen the settings: Brother 3, the 2MMOSFET8 part of the migration field is as described above ^ water = gradually widen the opening and in the same step to form the depth ^ same can be borrowed. That is, ′ can be the same as the previous process, and f ′ is formed by a 1 / ditch process, so it can be formed into light in stages :: 成 制:. However, if its purpose is to alleviate the concentration of the electric field, it is only necessary to limit it to the two-stage level shown in the embodiment. /, And to the second 25 3) 5] 54 200418184 In addition, this embodiment mode is shown in the case where the 3MMOSFET8b is arranged one week between the first and second MOSFETs 8 and 8a, but it can also be configured as a plurality week. In addition, when set to multiple weeks, the depth of the third MOSFET 8b does not need to be all the same, as long as it has a depth that is deeper than the first MOSFET 8 and shallower than the second MOSFET 8a, it can also be set in the form of a stepped depth. (Effect of the Invention) According to the present invention, the trench depth of the 2MMOSFET 8a is deeper than that of the first MOSFET 8 and is close to the P + -type area 4a. Therefore, the electric field at the bottom edge of the trench at the periphery of the actual operation area can be relaxed. concentrated. By suppressing the concentration of the electric field, a semiconductor device that suppresses deterioration of the withstand voltage between the drain source and the collector and emitter can be realized. In other words, it is possible to suppress the deterioration of the withstand voltage between the drain and the source (the collector to the emitter is the IGBT), and to significantly reduce the problem of a drop in the rating caused by the high temperature. In addition, according to this manufacturing method, trenches having different depths can be simultaneously formed in the same etching step. That is, the electric field concentration at the bottom edge can be mitigated using the same process as before without adding manufacturing steps. That is, there is an advantage in that a manufacturing method of a conductor device that can easily suppress a deterioration in withstand voltage between a drain source (an IGBT is a collector and an emitter) and suppress a drop in a rated value generated at a high temperature is provided. . In addition, the 3MMOSFET8b with a depth between the two FETs is provided between the first MOSFET8 and the second MOSFET8a, and the ditch is gradually deepened for a plurality of weeks near the outermost periphery of the actual operation area, so 26 315154 200418184 1 Compared with the case where only the outermost periphery is deepened, the electric field concentration can be more relaxed. This process can also gradually increase the width of the trench openings on the outermost periphery and the outer periphery in stages to form trenches that are gradually deepened in the same trench formation step. [Brief Description of the Drawings] FIG. 1 is a cross-sectional view of a semiconductor device of the present invention. Fig. 2 is a characteristic diagram of the semiconductor device of the present invention. Fig. 3 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 4 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 5 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 6 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 7 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 8 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. Fig. 9 is a sectional view of a semiconductor device according to the present invention. FIG. 10 is a cross-sectional view of a method for manufacturing a semiconductor device according to the present invention. FIG. 11 is a sectional view of a method for manufacturing a semiconductor device according to the present invention. FIG. 12 is a cross-sectional view of a conventional semiconductor device. 13 are cross-sectional views of a conventional method for manufacturing a semiconductor device. FIG. 14 is a sectional view of a conventional method for manufacturing a semiconductor device. FIG. 15 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 16 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 17 is a cross-sectional view of a conventional method for manufacturing a semiconductor device. FIG. 18 is a sectional view of a conventional method for manufacturing a semiconductor device. Figure 9 is a characteristic diagram of a conventional semiconductor device. 315154 200418184 21 1-12 > and pole area 4, 4a, 24a P + type area 5, 6 n 6a N 6b, 26 trench opening 7 first trench 7a 7b third trench 8 8a second MOSFET 8b 11, 31 gate Electrode oxide film 13, 14, 34 Body contact area 15, 16, 36 Interlayer insulation film 17 27 trench 28 MOSFET 3 7 source electrode 27a 32 25 B is N + type silicon semiconductor substrate channel layer CVD oxide film second channel first MOSFET 3rd MOSFET 3 3 Gate electrode 35 Source area metal electrode (source electrode) Silicon layer 315154 28