TW200418136A - Method for forming a damascene structure - Google Patents

Abstract

A method for forming a damascene structure. An insulating layer is deposited on a substrate. A capping layer and a hard mask layer are successively formed on the insulating layer. Subsequently, the hard mask layer is etched to form at least one opening using the capping layer as an etching stop layer. A conformable metal layer is formed over the hard mask layer and the surface of the opening, and the metal layer is then anisotropically etched to form a metal spacer over the sidewall of the opening. Next, the capping layer and the underlying insulating layer under the opening are etched to form a trench therein. Next, the hard mask layer and the metal spacer are removed. Finally, the trench is filled with the conductive layer to complete the structure after the substrate is cleaned.

Description

200418136 V. Description of the invention α) ----———— Field of invention: The present invention relates to a method for manufacturing an integrated circuit structure, and particularly to a method for forming interconnections by using a damascene process. Prior art: In the manufacture of integrated circuits, a multilayer wire structure is often used to connect various regions of the device f or each device in the integrated circuit. Today, inlay technology has become a very useful way to form the above-mentioned wire structure and has been widely used in the semiconductor industry. The damascene process is a manufacturing process for interconnects, in which a trench is formed before an insulation, and then a metal is filled to form a wire layer. In order to further understand the background of the present invention, the following describes the conventional method of forming a mosaic structure with reference to FIGS. First, referring to FIG. 1 &, a substrate lj 0 ′ is provided, for example, a silicon wafer, which has a metal wire layer formed therein. Then, a capping layer, such as a silicon nitride layer, is formed on the substrate 100 to cover the metal wiring layer 102. Thereafter, a gold | intermetal dielectric (IMD) 106 and an upper cap layer 108 are sequentially deposited on the capping layer 104. The intermetallic dielectric layer 106 may be composed of a low dielectric constant (iww) material layer, such as spin-on glass (s0G), fluorine-doped silicon dioxide (FSG), hafnium-containing silicate (HSQ) ), Fluorine-doped polyarylene ether jFLARE), and aromatic hydrocarbons (SiLK). In addition, the upper layer 108 is used to protect the metal interlayer dielectric layer 〇〇6, which may be composed of silicon oxide: Then, a hard mask layer 丨 〇 is formed on the top cap layer 〇 08, as if chaotic A silicon layer and a photoresist layer having a trench pattern formed thereon

200418136 V. Description of the invention (2) 112 The photoresist layer 112 is used as a mask to engrav the hard mask layer 110 with anisotropic money, and an opening 1 1 4 pattern is formed therein. Next, after the photoresist layer 112 is stripped off, the next step is to remove the upper cap layer i08 exposed under the opening 114 by reactive ion etching (RIE) to expose the insulating layer 1. 6 surface.

Unfortunately, due to the poor etching selection between the hard mask layer 110 and the upper cap layer 108 and the interlayer dielectric layer 106, the hard mask layer 丨 10 is gradually tapered, as described in Section 1. lb picture. When using the gradually refined hard mask layer 110 as a mask, the insulating layer 106 is engraved to form the trench 11 6 ', which forms an inclined profile (p r 0 f i 1 e). That is, the critical dimension (CD) of the undesired trench 116 will cause the electrical characteristics of the device to change. The area enclosed by the dotted line in the figure represents the desired outline of the hard cover layer 110. Next, after the "clear reference 1c figure" is removed, the gradually-decreasing hard mask layer 110 is removed, and the cover layer 108 is also lost, especially in the area 11 7 between the denser trenches 116.

Finally, referring to Figure 1d, a standard pre-cleaning step is performed by an inductively coupled plasma (ICP) process (eg, argon ion sputtering etching) to remove the native oxide layer or polymer residue Things (not shown). Next, a conductive layer, such as a copper metal layer, is formed on the upper cap layer 108 and filled in the trench 116. In general, before filling the conductive layer, a barrier layer (not shown) is formed on the top of the cap layer 108 and the surface of the trench 116 to conform to it, such as a nitride layer or a nitride layer. Tantalum (TaN) layer. After that,

Structure of the square paste (ICP 200418136 V. Description of the invention (3) Chemical mechanical polishing (OMP) removes the excess conductive layer and barrier layer above the cover sound 108 to form a mosaic structure. However, it is located in the trench The partially overlying upper cover layer between the slots 1 and 16 is formed after the CMP process, and a metal bridging is formed after the CMP process, which reduces the reliability of the component. In order to solve the above problems, it is suggested to use a metal hard cover For example, barrier materials such as Nitride or Nitride can be used to increase the I-etching selection ratio between the capping layer and the interlayer dielectric layer. This is indeed true for trenches with vertical contours. Unfortunately Ground, during the pre-cleaning process, the Qin atoms or group atoms in the hard curtain are sputtered out by argon ions and deposited on the inner wall of the CP reaction chamber, causing the I CP reaction chamber to fail and become unusable. SUMMARY OF THE INVENTION: In view of this The object of the present invention is to provide a method to prevent the low-dielectric material layer from being erroneously etched, changing the key pattern size (CD) of the structure, or preventing the metal frame X. And further improve the reliability of the element. Π ridging), France, to avoid after pre-cleaning procedure, resulting in inductive coupling qe) etching reaction chamber failure. 11 According to the above object, the present invention provides a forming method. First, an insulating layer is deposited on a substrate, and then the structure is formed as follows: an upper cap layer and a hard cover layer are formed. Then, the hard mask layer is etched by the etching stop layer on the edge layer, the edge layer, the edge layer, and the ^^ 盍 layer is formed as an opening. then,

200418136 V. Description of the invention (4) After the metal is etched in the hard cover layer, the grooves are engraved, and then decoupling is performed. After the substrate is cleaned, the above insulating cover layer can be made of non-doped, and hard , Gold nitride and other barriers. In order to make the following special features of the hair better: upper and open layers, the following is the hard removal type (ICP: the groove layer contains debris, the glass cover curtain belongs to the gap surface of the gap material conforms to form a metal layer, not A metal barrier wall is formed on the side wall of the opening. The upper cover layer and the sloping edge layer below it form a trench cover curtain layer and a metal barrier wall. Finally, by performing argon ion sputtering etching in a reaction chamber to A conductive layer is filled in the clear to form a mosaic structure / a low dielectric constant (1 ow k) material layer. The undoped silicon glass (USG) layer can be composed of nitrided stone or carbonized stone. The wall can be made of Shao The above-mentioned purpose, features and advantages of Fan Ming, which is composed of metal or composed of titanium nitride or is composed of 100 to 5000 angstroms, can make the embodiments more obvious and easy to understand. The description is as follows: The method of forming a damascene structure according to the embodiment of the present invention will be described with reference to Figures 2a to 2e. First, please refer to Figure VII to provide a substrate 200, such as a silicon wafer, with a metal layer 2 formed therein. 2. Metal layer 2〇 Series 2 serves as the lower V-line layer and can be composed of copper metal or aluminum metal. Next, a hafnium layer 204, such as a silicon nitride layer, is formed over the substrate to cover the metal layer 202. Then, It By conventional deposition techniques such as chemical vapor deposition

200418136

ic = c: vrordeposltlon, CVD), a dielectric layer 206 is formed on the sealing layer 204 above the substrate 200. In the present invention, the dielectric layer 206 is an intermetal dielectric layer (IMD). This metal interlayer dielectric layer is composed of a low dielectric constant material such as SOG, HSQ, FSG, FLARE, SiLK, or black diamond (black • d). Further, a better metal The thickness of the interlayer dielectric layer 206 is in the range of 4000 to 1000 angstroms. Next, by a conventional deposition technique, such as CVD, an overlying cap layer 208 and A hard mask layer S2i0. In the present invention, the upper capping layer 20 may be made of silicon oxide, such as undoped silicon oxide (USG), to protect the interlayer dielectric layer 206 and serve as a subsequent CMP The thickness of the polishing stop layer in the process is in the range of 1000 to 15,000 angstroms. Furthermore, the hard mask layer 2 10 may be composed of silicon nitride or silicon carbide, and the thickness is 100 to 1 A range of 50 Angstroms. Subsequently, a photoresist layer 2 1 4 having a groove pattern is formed over the hard mask layer 210. In addition, the photoresist layer 2 1 4 and the hard mask layer 210 may be selectively formed. An anti-reflective layer (ARC) 2 1 2 is formed between the layers, such as silicon oxynitride, to reduce the standing wave effect and optical proximity. Optical proximity effect (OPE). Next, the anti-reflection layer 212 above the capping layer 208 and the hard mask layer 210 below it are anisotropically etched by reactive ion etching (RI EE), so as to form a hard mask An opening 2 1 6 is formed in the layer 21〇. Next, 'clearly refer to Figure 2b to 2d', which will release the key steps of the present invention. In Figure 2b, the photoresist is removed by an oxygen plasma or a suitable solvent. Floor

200418136 V. Description of Invention (6) --- 2 1 4 The text is protected by the upper cover layer 208, and the dielectric layer 206 is not damaged. Next, a metal layer 218 is conformably formed over the anti-reflection layer 212 and the surface of the opening 216. In the present invention, the thickness of the metal layer 218 is in the range of 1000 to 1 500 angstroms, and it may be made of aluminum metal or a commonly used barrier material, such as titanium nitride or hafnium nitride. . Furthermore, the physical layer 2 1 8 can be formed by physical vapor deposition (PVD) or CVD. Preferably, the metal layer 218 is formed by ionized physical vapor deposition (ionized PVD, I-PVD). Next, please refer to FIG. 2C. The metal layer 2 丨 8 is anisotropically etched, for example, reactive ion etching is used to form a metal spacer 220 on the sidewall of each opening 2 丨 6. In addition, if the metal layer 218 is formed using PVD, the subsequent non-specific money engraving to form a metal spacer can be performed by in-situ argon ion sputtering etching. As a result, process steps can be reduced and productivity can be increased. Next, referring to FIG. 2d, the cap layer 208 below the opening 2 1 6 and the dielectric layer 206 below it are etched to form a trench 222 in the dielectric layer 20β. After the etching process is performed, the anti-reflection layer 212 is completely removed and a part of the hard mask layer 2 1 0 and the metal spacer 2 2 0 are consumed. Compared with the conventional technology, since the metal partition wall 2 2 0 in the present invention can protect the side wall of the hard cover curtain layer 2 1 0 during the engraving, a groove 2 22 having a vertical contour can be obtained to prevent The key graphic size (CD) changes. In addition, the top cover layer 2 08 is also protected by the hard cover curtain layer 2 10 and the metal partition wall 2 2 0 during the engraving, which is beneficial to the subsequent CMP manufacturing process. Finally, please refer to FIG. 2e, remove the hard cover curtain layer 210, and simultaneously

0702-8996twf (nl); 91P63; SPIN.ptd page 11 200418136 V. Description of the invention (7) Remove the metal spacer 2 2 0 left on its side wall. Then, similarly, a standard pre-cleaning process is performed by an induction co-plasma (I CP) process (argon ion sputtering etching) to remove the native oxide layer or polymer residue (not shown). Next, a conductive layer, such as a copper metal layer, is formed over the cap layer 208, and is filled into the trench 222. Generally speaking, before filling in the conductive layer, an early barrier layer (not shown), such as a titanium nitride layer or a nitride button, is formed on the surface of the upper cap layer 208 and on the surface of the trench 2 2 2. Floor. Thereafter, by using a conventional polishing technique, such as chemical mechanical polishing (CMP), the excess conductive layer and the barrier layer above the cap layer 208 are removed to form a damascene structure 224. .... According to the method of the present invention, before the pre-cleaning process is performed, the metal partition wall 22 formed of the barrier material or the aluminum metal can be removed together with the hard cover curtain layer. Therefore, no source of contamination will be deposited inside the ICP chamber, which will cause the problem of failure. Furthermore, located in the trench: upper 盍 = 208 was protected before the implementation of CMP, which could not effectively prevent the problem of metal bridging, thereby improving the component's capability. Although the present invention has been disclosed above in a preferred embodiment, iron 1, To limit the present invention, anyone who is familiar with this technology, within the scope of Asia and Africa, can make changes: within the scope of the patent application attached without departing from the essence of the invention; Scope of protection

〇702-8996twf (nl); 91P63; SPIN.ptd page 12 200418136 Brief description of the drawings Figures 1a to 1d are cross-sectional views of the conventional method for forming a mosaic structure. Figures 2a to 2e are schematic cross-sectional views illustrating a method of forming a mosaic structure according to an embodiment of the present invention. Explanation of symbols: Conventional 100 ~ substrate; 102 ~ metal wire layer; 104 ~ capping layer; 106 ~ metal interlayer dielectric layer; 108 ~ overcap layer; 110 ~ hard cover layer; 112 ~ photoresist layer; 11 4 ~ Openings; 11 6 ~ grooves; 1 1 7 ~ the area between dense grooves; 118 ~ mosaic structure; 120 ~ metal bridge. 200 ~ substrate of the present invention; 202, 218 ~ metal layer; 204 ~ capping layer; 206 ~ metal interlayer dielectric layer; 208 ~ upper cover layer; 210 ~ hard mask layer; 212 ~ antireflection layer; 214 ~ photoresist layer 21 6 ~ openings; 2 2 0 ~ metal spacers; 2 22 ~ grooves; 224 ~ mosaic structures.

0702-8996twf (nl); 91P63; SPIN.ptd page 13

Claims (1)

Scope of Liushen Patent ^ A method of forming a mosaic, including at least the following steps: sinking a m-insulation layer on a substrate; # 4, sequentially forming an overlying cap layer and a hard cover layer on a marginal layer; d The capping layer is used as a stop layer to etch the hard mask layer to form at least one opening; the etching layer forms a gold-wide gap wall on the side wall of the opening; and the layer below the opening and the insulating layer below to form A trench; removing the 忒 hard mask layer and the metal spacer; and filling a _ conductive layer in the 忒 trench to form a mosaic structure. Method 2. The steps of forming a damascene structure as described in item 1 of the scope of patent application, before filling the conductive layer in the trench, further includes cleaning the substrate 0, 3. As described in item 2 of the scope of patent application The method of forming a damascene structure 'wherein the cleaning step is an argon ion sputtering etching performed in an inductively coupled plasma reaction chamber. u ^, 4. The method for forming a damascene structure as described in item 丨 of the patent application scope, wherein the insulating layer includes a layer of a low dielectric constant material. 5. The method of forming a damascene structure as described in item 1 of the scope of the patent application, wherein the cap layer is an undoped silica glass. 6. The method of forming a mosaic structure as described in item 5 of the scope of the patent application, wherein the thickness of the cap layer is in the range of 1000 to 1500 angstroms. 7. The method of forming a mosaic structure as described in item 1 of the scope of the patent application ', wherein the hard mask layer is a nitrided layer or a carbonized layer. 0702-8996twf (nl); 91P63; SPIN.ptd Page 14 200418136 VI. Application for patent scope 8. As for the scope of patent application ^ method, where the hard cover curtain entry forms the inlay structure 9. · As applied Patent range = thickness in the range of 1000 to 15 °. Method, before the step of forming the inlay structure described in the hard mask 1 = item-anti-reflection layer step / before, it is further included on the hard mask curtain layer 10 The layer formation method described in the layer item, 1 1 β: system-silicon oxynitride layer. 11. As described in the patent application, the method of forming a mosaic structure described in item # + π Λ, "A target", wherein forming the metal partition wall includes at least the following steps: the structure is on the hard cover curtain layer. And an compliant layer on the surface of the opening; and anisotropically etching the metal layer with a metal to gap the sidewall of the opening. Li-Metal Metal Room 11 2 · The method of forming a damascene junction as described in item 11 of the scope of the patent application, wherein the thickness of the metal layer is in the range of 1 Q0 to 500 Angstroms. Fang 0702-8996twf (nl); 91P63; SPIN.ptd Page 15 1 3 4 5 6 7 8 · The method of forming a damascene structure 2 as described in item 11 of the scope of patent application, wherein the metal layer is titanium nitride or nitride Button 3 and other barrier material layers 3 14 · As described in the scope of application for patents, the formation of the mosaic structure 9 structure 4 method 'where 5 layers of the square by physical vapor deposition or chemical vapor deposition. w | form the metal 6 1 5 The method of forming a damascene junction 7 as described in item 11 of the scope of patent application, wherein the anisotropic etching is reactive ion etching. " Party 8 1 6. The method of forming insert 9 as described in item 11 of the scope of patent application, wherein the metal layer is formed by ionized physical vapor deposition. The method of forming a damascene structure according to item 11 in the scope, wherein the anisotropic etching is an in-situ argon ion sputtering etching. 1 8. The method for forming a mosaic structure according to item 1 of the scope of the patent application, wherein the metal spacer is an aluminum metal spacer and has a thickness in the range of 100 to 500 angstroms. 19. The method for forming a damascene structure as described in item 1 of the scope of the patent application, wherein the conductive layer is a copper metal layer. 0702-8996twf (nl); 91P63; SPIN.ptd page 16