TW200408107A - Electrostatic discharge protection device - Google Patents

Abstract

The present invention provides an electrostatic discharge protection device, which is formed on a substrate including a plurality of p-type and n-type transistors; wherein, the p-type transistors have a plurality of gate fingers, a plurality of drain gate areas commonly coupled to the first node, and a plurality of source gate areas commonly coupled to the third node. The n-type transistors have a plurality of gate fingers with vertical direction to the p-type transistor gate fingers, a plurality of drain gate areas commonly coupled to the first node, and, a plurality of source gate areas commonly coupled to the second node. The lengths of gate fingers of n-type transistors are more than twice of the lengths of gate fingers of p-type transistors.

Description

200408107

-Species ί: ί: There is a kind of electrostatic discharge protective equipment, especially about the use to discharge static electricity: electricity? The electrostatic protection device s can avoid the phenomenon of lowering the anti-sagging performance due to back) ^ < Λ Λ Λ ^ ^-Γ ^ ^ ^ ^ ^ & N Shengjin oxygen half field effect transistor (NM0SFET) is an effective electrostatic discharge protection device of h minutes. To Fumen Fork, You & Ding Dao, Huan Zhi Ju 1;

As an example, MimeiM7T π m eight gates are connected to a gate drive signal, " Example of pull-down in a complementary metal-oxide-semiconductor (CMOS) buffer (pul i example, NM 0 SFET can & de_ φ + source sink When the battery is not damaged by static electricity, it protects an input pin or electricity in the "^ electrostatic discharge event of the formula", a integrated circuit pin is connected to a positive electrostatic discharge voltage of ~, and a low potential VSS power supply The pins are at zero potential (ground potential). The protection of the electrostatic discharge of the NM0SFET is to draw a large amount of electrostatic discharge current between its drain and source due to "snap back". At the beginning of this electrostatic discharge process, the impact ionization caused by a large electric field located on the non-polar junction will generate both a majority and a minimum of carriers. The minority carriers will be Collected at the drain, most carriers flow through the contact window (conntact) in the f-well or P-well zone to form a local potential in the p-well zone. When the local potential of the substrate is higher than the adjacent N + source potential. · At 8 V, a forward bias is formed on the source junction The source junction of forward and backward will / mainly enter minority carriers · into the p-well region. Some of the injected minority carriers are recombined in the substrate, while others reach the drain junction further Ground strengthens the phenomenon of impact ionization. As a result of this cycle,

200408107 V. Description of the invention (2) The NM0SFET will enter a low-impedance tripping state, and begin to conduct a large amount of electrostatic discharge current. As shown in Figures 1A and 1B, in the structure of an electrostatic discharge device with multiple gate fingers, not all of the gate fingers can jump through during an electrostatic attack. This is because a small number of gate fingers may have quickly entered a low-impedance trip state, causing the voltage difference between the drain and source to fall below the threshold trigger voltage. This will prevent other gate fingers from conducting. Therefore, in the case that only a few gate fingers can conduct the electrostatic discharge current, the actual effective total gate width of the NMOSFET is reduced, and the protection ability of the electrostatic discharge is also reduced. When a gate finger is turned on due to an electrostatic attack, the entire gate finger is on. This is due to a cascading effect, which means that when a local source junction is in a forward bias, a large number of carriers will be injected into the substrate and flow to the drain junction. The large majority carriers flow back to the P-type guard ring and increase the potential of the adjacent p-well region. As a result, the n + / p well junction adjacent to the source region also has a forward bias phenomenon. It is through this chain effect that the entire gate finger enters a trip state. This example is also applicable to the case where the P-well area is a p-type substrate. It is known through experiments that in the electrostatic discharge in ps mode, when NM〇s has a longer gate finger (such as the two 丨 00μ ^ gate fingers shown in Figure 2), it will have a higher than 1A. In the picture, 10 20m gate electrodes have high electrostatic discharge protection capability. Among them, NM0S in Figure 2 and Figure 1A have the same total gate finger width, that is, 20 0 " m. This phenomenon is due to the fact that in a ps mode, an electrostatic discharge event, many and short gate fingers can cause only a few or part of the gates.

〇492.7917TWF (nl); 90-164TW2; Vincent.ptd page 6 200408107 V. Description of the invention (3) Pole refers to the phenomenon of tripping state Traditional MOSFET is mainly used, with self-static discharge protection < into the structure, generally Both have multi-fine M0S and cut 5 transistors. As shown in Figure 2 and 3B, the NMOS transistor used for pull-down will contain multiple idler elements A and gate signals connected to the output transistor, and some Connect the power bus of two VSS or ground points as the static protection structure of the input terminal. Similarly, the PM0SFET used for pull-up will also contain multiple components. Some are connected to the gate signal for the output transistor, and some are connected to the high-voltage VDD power bus as an input or output: Discharge protection structure. In this traditional electrostatic discharge protection method, the gate elements formed by crystalline silicon elements are generally each coupled to a ^ or power bus. · In order to solve the problem of reducing the electrostatic discharge protection caused by traditional short gate fingers, the present invention provides an electrostatic discharge protection device with a long gate ^ and its layout. The long gate fingers can be used. The advantages of interlocking ^ eliminate the disadvantages of the traditional structure. At the same time, part of the gates can be arbitrarily coupled to the signal source, and the other part of the gates can be coupled to a power bus two with similar short and many gate fingers and can be coupled with some gate fingers. Gate signal 'Remaining gate refers to the flexibility of coupling to the power bus. Although the long gate finger can strengthen the electrostatic discharge protection for N-type pull-down transistors, according to new experiments, the short gate finger has better electrostatic discharge for p-type pull-up transistors. Protection. This is because the electrostatic discharge in the PD mode (positive electrostatic discharge pulses to the VDD power bus) or the PS mode (positive electrostatic discharge pulses to VSS power bus)

200408107-V. Explanation of the invention (4) In the electrical event, the P-type transistor will borrow ^ to the VDD power bus) P + / n wel 1 junction surface (the amount of the drain region. Because of the f The distance between the edges of the miscellaneous area, so the two-pole V of the joint surface and the two-contact window 'long closed-pole finger' will instead increase the non-pole contact = pole. In this case, ΓΪΛ protection against electrostatic discharge. Type crystal pull-up crystals, the size of which remains at least equal to or has a symmetrical pull-up and pull-down response;

1.2 to u times of f transistor. Among them, Λ ϊN of the transistor means ':: the total channel width' is approximately equal to the length of each gate finger. Is the effective channel length, which is approximately equal to one gate electrode: the light doping source below and the extension length of the region. Due to the limitation of the size of the pull-down transistor, traditionally, the length of the pull-up P-type transistor = the length of the gate finger is usually longer than that of the pull-down N-type transistor: wide or equal. However, the traditional arrangement mentioned above reduces the J ESD protection performance, especially in pD mode. ^ Conversely, the present invention provides an improved layout with a longer gate finger in a down-converter and a sum of gates in a pull-up transistor. In a preferred embodiment, the N-type transistor has one or more gate fingers that are at least 45 // m long, and the p-type transistor has one or more gate fingers that are at most 40 long; or, N-type Transistor has ^ _

I1H 〇492-7917TWF (nl): 90-164TW2; Vincent.ptd page 8 200408 W7 V. Description of the invention (5) Ϊ ί ί τ " ^ Μ ^ # ^ 1 Ρ Because I body X = Γ " or the opposite side. In order to maintain the accuracy of the N-type transistors, the total number of N-type and N-type electrodes is kept at least or 3 times the N-type transistor gate index. ϋThis & gg-^ In this specification, there are different P-types, ㈣electric crystals 均 = all ^ In the traditional arrangement, N-type and P-type two electric and; and the position of m is imitated, The main bang tail enemy protection transistor is squared and the gate fingers are oriented in the same direction to facilitate the coupling between the pad and the drain of the two transistors. The quantity is different. In the present invention, in order to strengthen the two different lengths, the phases are: two: the area efficiency, the gates of N-type and P-type transistors are arranged in a perpendicular manner, and can be located on the same pad. The side or phase, the first purpose of this volume is to provide an electrostatic discharge protection device, formed on a substrate, including a plurality of p-type transistors, with a plurality of gate fingers, two less, one transferred to a first node. A drain region and at least one source region coupled to a second point; and a plurality of N-type transistors having a plurality of gate fingers perpendicular to the gate fingers of the type transistor, and at least one coupled to the first The non-polar region of the node and at least one source region coupled to a second node. Among them, the length of the gate fingers of the N-type transistors is more than twice the length of the gate fingers of the P-type transistors. A second object of the present invention is to provide an electrostatic discharge protection device formed on a substrate, including: a plurality of P-type transistors having a plurality of gates 0492-7917TWF (nl); 90-164TW2: Vincent.ptd page 9 200408107 V. Description of the invention (6) At least one coupled to a first finger means one less coupled to a source region of point; and a plurality of N-type transistors, which are straight gate fingers of a node, at least-coupled To this-: point: and polar region and at least-transfer to a source region of a second node. The number of gate fingers of the index ΐ-type transistor is more than twice the number of gates of the transistor.

The shape point, Ben Maoming, is used in the active area to form a second insulation area, and the two gates adjacent to each other on the second insulation area are too close to each other. The invention's electrostatic discharge protection device is equivalent to It has a long interpolar finger =, and the chain effect of the long gate finger can be used. At the same time, since the short pole fingers of the N pole finger and PM0S can be arranged in mutually perpendicular directions', the circuit area can also be effectively used. In the following, only examples of an electrostatic discharge protection device according to the present invention will be described with reference to the drawings. Examples Figures 4A, 4B, 4C and 4D show the static and discharge protection devices in the first embodiment of the present invention. Figures 4B, 4C, and 4D are cross-sectional views obtained by cutting along line BB and CC in Figure 4A, respectively. Please refer to Figures 4A, 4C, and 4D at the same time. The electrostatic discharge protection device in this embodiment is formed on the bottom 41, including a plurality of ρ-type transistors in parallel and a plurality of ν-type transistors in parallel. On the side of the P-type transistor, there are gate fingers 341 to 348 commonly coupled to node X, multiple drain regions 352 commonly connected to node 37, and multiple ones coupled to pad 31 via metal layer 32. Source region mi. On the side of the N-type transistor, there are gate layers 441 and 442 perpendicular to the P-type transistor gate fingers 341 to 348.

〇492-7917TWF (nl); 90-164TW2; Vincent.ptd page 丨 〇 200408107

The formed gate tie is commonly transferred to the drain region 451 of the fresh pad 31 through the metal layer 32 and the source region 4 52 connected to the node 46 2 in common. Among them, the length of the gate fingers composed of the gate layers 441 and 442 in the N-type transistor is twice or more than three times the length of the% gate fingers 3 4 1 to 3 4 8 in the p-type transistor. On the side of the P-type transistor, an insulating region 421 formed on the substrate 41, an active region 43 formed on the substrate 41 and surrounded by the insulating region 421, and an insulating region formed on the substrate 41 and surrounded by the active region 43 are further included. 422. Gates (conductors) 441, 442, 443 formed in the active region 43, an electrodeless region 451 formed in the active region 43 and one side of the gate 441, formed in the active region 43 and the gate 44 A source region 452 on the other side, a drain contact window 471 electrically coupling the drain region 451 to a node 461, and a source contact window electrically coupling the source region 452 to a node 4 6 2 4 7 2. Among them, the gate electrode 41 is connected to the node γ on one side, and one end thereof extends above the insulation region 421 (overlaps the insulation region 421), and the other end extends above the insulation region 422 (overlaps the insulation region 422). One end of the gate electrode 442 extends above the insulation region 421 (overlaps the insulation region 421), and the other end extends above the insulation region 422 (overlaps the insulation region 422). Both ends of the gate electrode 443 extend above the insulating region 4 2 1 (overlapping with the insulating region 4 2 1). The gate 4 4 3 is electrically coupled to the gate 44 2. The drain contact window 471 is located between the gate electrodes 441, 443 or 442, 443, and includes at least one row of contact windows parallel to the gate electrodes 441, 442, or 443. The drain and source contact windows 471 and 472 may be contact windows made of aluminum (A1 contact) or tungsten plugs (Tungsten plug). The gate 441 is coupled to a gate input signal, and the gate 442 can be coupled through a impedance 4 8 1 or directly connected to the node 4 6 2. The impedance 4 8 1 may be a resistive element. Gates 442, 443 can also be coupled via impedance 4 82 or

0492-7917TWF (nl); 90-164TW2; Vincent.ptd Page 11 200408107 V. Description of the invention (8) " " — ^ _________ Connect directly to node 46 1. The impedance 482 may be a capacitor. The gate 441 and the gate 442 are generally located in the :::: sensor. In addition, ^ ^, 私, 、, the drain region 451 and the source region 452 can be connected by the source-gate, and the electrode-gate junction surface, L-shaped. The gates 4 4 1, 4, 4 2, 4 4 3 are all composed of Shi Xi, a private technique, and 1 on the gate emulsified layer 4 9, which is called Shi Xi =. The gate electrode 443 separates the electrodeless region 451 and the other source region 4 5 3 located in the active region 43. Among them, the nodes X and Y are signal input nodes, and they may be the same node 0. In this embodiment, the insulation region 422 is completely surrounded by the active region 43 and completely separated from the insulation region 421. The node 461 may be a pad, and the node 462 may be a power bus. When the substrate is a p-type silicon substrate or an n-type well ^ where the 'rich source regions 452, 453, and the non-electrode region 451 are N-type heavily doped regions, the nodes 4 to 62 may be a low-potential VSS power bus; and When the source regions 452, 4 53 and the non-electrode region 451 are P-type heavily doped regions, the node 46 2 may be a high-potential VDD power bus. Gate In addition, the insulating region 42 2 may be made of a field oxide layer or other materials suitable for insulation in a integrated circuit, and may be formed using the same structure as the insulating region 4 2 1. According to the conventional technology, the field oxide layer may be formed by a method such as LOCOS or a shallow trench isolation layer. In addition to being an input protection device, the electrostatic discharge protection device of this embodiment can also be connected to the * gate input signal to form a larger output according to the current driving force of the output transistor. The transistor, and the gate 4 4 1 are coupled to the power bus to form a smaller input protection device. The total gate width of gates 4 4 1, 4, 4 2, 4, 4 3 must conform to the static

Η 0492-7917TW (nl); 90-164TW2; Vincent.ptd Page 12 200408107 V. Description of the invention (9) Requirements for electrical discharge specifications, such as forming the total gate of input and output transistors in 2KV human body electrostatic discharge The pole width must be at least 200 # m. Figures 5A, 5B and 5C show an electrostatic discharge protection device in a second embodiment of the present invention. Figures 5B and 5C are sectional views obtained by cutting along lines XX and γγ in Figure 5A, respectively. Please also refer to Figures 5A, 5B, and 5 (: Figures. The electrostatic discharge protection device in this embodiment and the electrostatic discharge edge protection devices in Figures 4A, 4B, 4C, and 4D have similar structures, and the difference lies in the drain electrode. The islands 50 surrounded by the drain region 451 are distributed in the area 45. For the sake of brevity, the same 7L parts in the two use the same symbols and will not be repeated. The way of forming the islands Reference can be made to the patent of the Republic of China No. 82〇94 No. 5721 439. ^ 4 arrays to form an array of islands with at least one island or island row, distributed at least in the drain region 451 And it is between the non-polar contact window 4 7 1 and the 4 1 AA 0 iio .. ”idle pole 441, 442, 443 or one of the insulation regions 422. The island 50 can be reported as a number of 庶 乂 疋The silicon element 501 formed on the oxide layer 51 is formed at the same time as the gate electrode 441 in a pattern of ^ ^ & 上 ^ ^ ^ ^ a,, y, 441. Drain pole contact chute 4 7 1 丨 J is composed of at least one contact eclipse— &w; soil. Insulation area 422, forming a single unit from the market ^ 1L ~ the first element group, the island array sentence includes a row located in the contact window array and the sign ^ .j,, g, wr · Λ ^ Jiudi a piece The islands 50 between groups. The presence of soap 50 can disperse the current in the horse-like polar region 4 5 1 to increase the uniformity of the electrostatic discharge performance in the long film Qiu region. Figures 6A, 6B, and 6C show the electrical protection device of the present invention. Figure 2 and Figure 6C are divided into two: electricity: cut section ®. Please also refer to Figures 6A, 6B, and 6C and its first cut.

200408107

The electrostatic discharge protection devices shown in Figures 5A, 5B, and 5C are similar, but their islands 50 are composed of a field oxide layer 502 (as shown in Figures 6β and 6 (see the figure). These islands 50 are more than It is preferably formed at the same time through the same process as the insulating region 421. The insulating region 421 can be formed by L0C0S or a shallow trench isolation layer (Shal low

Trench Isolation). Figures 7A, 7B and 7C show an electrostatic discharge protection device in a fourth embodiment of the present invention. Figures 7B and 7C are sectional views obtained by cutting along lines gg and FF in Figure 7A, respectively. Please also refer to the M, 7B and 7 (: diagrams, where the electrostatic discharge protection device is similar to the ESD protection devices shown in 5A, 5B, and 5 (: diagrams, except that the type of the insulation area 422 is different. To The description is succinct, and the same elements in the two use the same symbols and will not be repeated. Among them, the 'insulation region 422 is an extension of the insulation region 421 to the active region 43. Therefore, the insulation region 422 forms a An peninsula structure extending from the insulation region 421 and partially surrounded by the active region 43. Figures 8A, 8B, and 8C show the electrostatic discharge protection device in the fifth embodiment of the present invention. Figures 8B and 8C are respectively Figure 8A The cross-sections obtained by cutting along the middle line HH, and KK. Please also refer to Figures 8A, 8B, and 8C. The electrostatic discharge protection device is similar to the electrostatic discharge protection device shown in Figures 6A, 6B, and 6C. The difference is that The shape of its insulating region 4 2 2 and a gate 444 are added to the active region 43. For simplicity of description, the same components in both use the same symbols and will not be repeated. Among them, the gate 444 Formed in active area 4 In 3, the two ends of the gate electrode 443 respectively extend above the insulation regions 421 and 422 (the insulation regions 421 and 4 22 respectively).

〇492-7917TWF (nl); 90-164TW2; Vincent.ptd Page 14 200408107 V. Description of the invention (11) Overlapping) 'And the two ends of the gate 44 also extend above the insulating regions 42 1 and 422, respectively. In addition, the gates 44 1 and 44 2 are located approximately on a straight line, and the gates 443 and 4 44 are approximately located on another straight line. The gate 441 is connected to the gate 443, and the gate 44 2 is connected to the gate 444. One part of the drain contact window 471 is located between the gates 441 and 443, and the other part of the drain contact window 471 is located between the gates 442 and 444. The island array includes a group of scattered islands 50 into which the insulating region 42 2 extends. Fig. 9 shows an electrostatic discharge protection device in a sixth embodiment of the present invention. It is also similar to the electrostatic discharge protection device shown in Figures 6A, 68, and 吒. The difference is that the insulation area 422 extends to the island array, and the integrated static discharge is located at the pole. Even though the scope of the god and the fan protection is the same as the above, the electric protective devices are substantially the same. The chain effect long gate fingers refer to the present invention effectively. Within the scope of the present invention, the Dangdang invention provides a private notice. Headpiece e Hirosato Akihiro 5 with long gate fingers: Utilizing the formation of an insulating region in the active region, which can be shaped on a straight line and in this absolute γ μ = two gates isolated from each other on the peak region of the plant E A long gate finger structure, ^ _ Dan can use the above-mentioned static lightning to improve the electrostatic protection ability. The π1 on the 静 1, ^ Λ ^ knife can make the N-type thunder structure and the P-type transistor short. At the same time, you can use the fixed circuit area for layout. 1 It has been disclosed in the-preferred embodiment that if anyone is familiar with this technique, * ..., it is not intended to be used for a little bit more; 润 run; application that does not depart from the essence of the present invention # II stomach ^ Therefore, the armor Defined by the monthly profit-seeking range shall prevail.

200408107 Schematic illustrations Figures 1 A and 1 B show the structure of a traditional multi-gate finger electrostatic discharge device; Figure 2 shows the structure of a long-gate finger electrostatic discharge device; Figures 3A and 3B show traditional M0SFET-based I / O protection device structure with self-static discharge protection capability; Figures 4A, 4B, 4C and 4D show the electrostatic discharge protection device in the first embodiment of the present invention; Figures 5A, 5B and 5C show The electrostatic discharge protection device in the second embodiment of the present invention; Figures 6A, 6B and 6C show the electrostatic discharge protection device in the third embodiment of the present invention; Figures 7A, 7B and 7C show the fourth embodiment of the present invention Figures 8A, 8B and 8C show the electrostatic discharge protection device in the fifth embodiment of the present invention; Figure 9 shows the electrostatic discharge protection device in the sixth embodiment of the present invention. [Symbol description], 3 1 ~ rod 塾; 3 2 ~ metal layer; 33 ~ N-type well area; 341 ~ 348 ~ * gate finger; 41 ~ base; 4 2 1, 4 2 2 ~ insulation area;

0492-7917TWF (nl); 90-164TW2; Vincent.ptd Page 16 200408107 Simple illustration of 43 ~ active area; 441, 44 2, 44 3, 444 ~ gate; 3 5 2, 4 5 1 ~ drain Area; 3 5 1, 4, 5 2, 4 5 3 to source area; 37, 461, 462 to node; 3 6 2, 4 7 1 to drain contact window; 3 6 1, 4 7 2 to source contact Window; 4 8 1, 4 8 2 ~ resistance; 4 9 ~ gate oxide layer; 50 ~ island.

0492-7917TWF (nl): 90-164TW2; Vincent.ptd Page 17

Claims (1)

Na UJ7 A Tan #electrical discharge protection device is formed on a substrate with a P-type thunder crystal, including ... M pt electric solar heliospheres, having a plurality of gate fingers, a drain region of a knuckle point, and at least one main v coupled to The first and the third electrode is connected to the source region of the third node; the gate finger of at least one N-type transistor, the female s, and at least one light-to / first connected to the p-type transistor A source region of a second node "-Lang point non-polar region and at least-two of the body": the length of the -gate finger of the transistor is at least two of the length of the gate finger of the P-type transistors The private day 2 · As mentioned in item 丨 of the application scope of the kiss kiss patent, the length of the gate finger of the N-type transistor is at least three times the length of the p / electricity 'gate finger. One of the sun bodies includes 3. An electrostatic discharge protection device formed on a substrate, a first insulating region formed on the substrate; an active region formed on the substrate and covered by the first insulating region. A second insulating region is formed on the substrate and is surrounded by the active region. A first gate electrode is formed in the active region and has a first gate electrode. End = 'to the top of the first insulation region and a second end extending above the first insulation region; a second gate formed in the active region, the second gate having a second end extending to the first Above an insulation region and a fourth end extend above the second insulation region; * a drain contact window, electrically coupling the drain region to the first node and 4 200408107 6. Scope of Patent Application A source contact window is lightly connected to the second node. 4. The electrostatic discharge protection device as described in item 3 of the scope of patent application. The drain region is formed in the active region and the first side of the first gate, and the source region is formed in the active plaque and the second side of the first gate. 5. The electrostatic discharge protection device according to item 4 of the scope of the patent application, wherein the first and second gate electrodes are located on a straight line to form one of the gate fingers of the N-type transistors. 6. The electrostatic discharge protection device according to item 3 of the scope of the patent application, wherein the second insulation zone is completely hidden by the initiative. 7. The electrostatic discharge protection device according to item 3 of the scope of the patent application, wherein the first and second gate electrodes are each formed of a polycrystalline silicon layer that is located above a gate oxide layer. 8. The electrostatic discharge protection device described in item 3 of the scope of patent application, wherein one of the N-type transistors further includes / forms a second gate in the active region, and the third gate has a first gate. The fifth and sixth ends, each of the fifth and sixth ends extending above the first insulation region, and the drain contact window is located between the first and third gates, and the third closed electrode forms the One of the gate fingers of these N-type transistors. 9. The electrostatic discharge protection device according to item 8 of the scope of patent application, wherein the third gate electrode separates the non-electrode region and the other source region located in the active region. * 1 0 · The electrostatic discharge protection device according to item 8 of the patent application scope, wherein the third gate is electrically coupled to the / gate. 200408107 6. Scope of patent application '' A " 11 The electrostatic discharge protection device as described in item 8 of the scope of patent application, wherein the third gate is electrically coupled to the second gate. 1 2 · The electrostatic discharge protection device according to item 8 of the scope of the patent application, wherein the first gate system is coupled to a gate input signal, and the second gate system is connected to the second node. 1 3 · The electrostatic discharge protection device according to item 丨 丨 of the scope of patent application, wherein the second gate is coupled to the second node through a first impedance. 1 4 · The electrostatic discharge protection device as described in item 13 of the patent application, wherein the first impedance is a resistive element. 1 5 · The electrostatic discharge protection device described in item 11 of the scope of patent application, wherein the second gate electrode is further coupled to the first section through a second impedance. 16 · According to item 15 of the scope of patent application The electrostatic discharge protection device 'wherein the second impedance is a capacitive element. 17 · The electrostatic discharge protection device as described in item} of the declared patent scope, wherein the first node is a frontal ridge. No. 1 on the scope of patent application! The electrostatic discharge protection device according to the item, wherein the second node is a high-potential VDD power bus and a low-potential VSS power bus. An electrostatic discharge protection device according to item 3 of the scope of application of P 2 Lizhong, which further includes-an island-less region with at least one island and m and pole contact windows with the first: = the one between. ^ Gate, second insulation area 20. The electrostatic discharge protection device described in item 3 of the scope of patent application, 200408107 6. Scope of patent application --- It also includes an island array with at least one island distributed in the electrodeless region and located in the drain contact window and at least the first gate and the second gate Between the electrode and one of the second insulation regions. 2 1 · The electrostatic discharge protection device as described in item 20 of Shenyan's patent scope, wherein the drain contact window is a contact window array having a plurality of contact windows, the first and second gate electrodes and the second insulation The region forms a first element sample group. The island array includes a row of islands between the contact window array and the first element group. 2 2 · The electrostatic discharge protection device according to item 19 of the scope of patent application, wherein the island array includes a plurality of rows of islands. 23. The electrostatic discharge protection device according to item 19 of the scope of the patent application, wherein the island array includes a first island, and the first island includes a polycrystalline silicon element formed on an oxide layer. 24. The electrostatic discharge protection device according to item 9 in the scope of the patent application, wherein the island array includes a first island, and the first island includes an oxide layer. 25. The electrostatic discharge protection device according to item 19 of the scope of the patent application, wherein the island array includes a first island, and the first island is made by the same system as the first insulation region. Cake formed. 2 6 · The electrostatic discharge protection device according to item 3 of the scope of the patent application, wherein the second insulation region is an extension of the first insulation region to an active region. * 27. The electrostatic discharge protection device a as described in item 26 of the scope of patent application, wherein the second insulation region forms an extension from the first insulation region and 0492-7917TWF (nl); 90-164TW2; Vincent.ptd page 21 200408107 6. Scope of patent application A peninsula structure partially surrounded by the first active area. 28. The electrostatic discharge protection device according to item 3 of the scope of patent application, further comprising a second and a fourth gate formed in the active area, the third gate having a fifth and a sixth terminal, The fourth gate has a seventh and an eighth end, respectively, and extends above the first and second insulation regions, respectively. 29. The electrostatic discharge protection device according to item 28 of the scope of patent application, wherein the first gate is connected to the third gate and the second gate is connected to the fourth gate. 30. The electrostatic discharge protection device described in item 28 of the scope of patent application, wherein the drain contact window is located between the third and third gate electrodes, and the other non-contact contact window is located between the second and third gate electrodes. Between the four gates. 31. The electrostatic discharge protection device according to item 28 of the scope of the patent application, wherein the first and second gates are located on a straight line, and the third and fourth gates are also located on another straight line. 32. The electrostatic discharge protection device according to item 3 of the scope of the patent application, wherein the island array includes a group of scattered islands, and the second insulation extends into the group of 50 Hai dispersed islands. 3 3 · One of the N-type transistors of the electrostatic discharge protection tape described in item 1 of the scope of patent application includes: a first insulating region formed on the substrate; an active region *, which is the first insulating region Surrounded by; a second insulating region formed on the substrate and surrounded by the active region; a first gate electrode formed in the active region and coupled to a first-^ ' 200408107 200408107 6. The scope of the patent application includes: a P-type transistor with a plurality of gate fingers, at least one coupled to-the first point and the polar region, and at least one source region that is connected to the second second point. And, "an N-type transistor having at least one gate finger and the P-type transistor—the gate finger, at least one sum region coupled to the first node, and at least—connected to a second node The source region of the P-type transistor, wherein the number of gate electrodes of the P-type transistor is at least twice that of the N-type transistor. 39 · The electrostatic discharge protection device described in item 38 of the scope of patent application, wherein the gate finger of the N-type transistor and the gate finger of the P-type transistor are perpendicular to each other. Day 40. The electrostatic discharge protection mechanism as described in item 38 of the scope of the patent application, wherein the number of gate fingers of the at least one N-type transistor is at least three times the number of gate fingers of the at least -p $ crystal. = 4 1 · The electrostatic discharge protection strip as described in item 38 of the scope of patent application, wherein one of the N-type transistors includes: a first insulating region formed on the substrate; the last active £ ' Formed on the substrate and surrounded by the first insulating region, a second insulating region, formed on the substrate and surrounded by the active region, a first gate electrode is formed in the active region, and has a first = Around the first insulation region and a second end extending to the second insulation = extended side; a second gate electrode of the product is formed in the active region, and the second gate electrode has 200408107 The third end of the patent application scope extends above the insulation area; the upper end of the water area and a fourth end extend to the second and & contact window 'electrically couples the drain region to The first node of which: the pole j touches the window to electrically couple the source region to the second node. The first and second regions are formed in the active region and the first side. The source regions of the wide and idle poles are formed in the active region and the second side, and the gates of the gates are not composed of N, Lei, f, and the first and second gate systems are formed on a straight line. One of the gate fingers of this N-type electric sun-solar body. -42. The electrostatic discharge protection device according to item 41 of the scope of patent application, wherein the second insulation area is completely covered by the active area 0492-7917TWF (nl); 90-164TW2; Vincent.ptd page 25