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TW200405718A - Photoconductor on active pixel image sensor - Google Patents

Photoconductor on active pixel image sensor Download PDF

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Publication number
TW200405718A
TW200405718A TW92123616A TW92123616A TW200405718A TW 200405718 A TW200405718 A TW 200405718A TW 92123616 A TW92123616 A TW 92123616A TW 92123616 A TW92123616 A TW 92123616A TW 200405718 A TW200405718 A TW 200405718A
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sensor
layer
pixel
item
patent application
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TW92123616A
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TWI268098B (en
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Tzu-Chiang Hsieh
Calvin Chao
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Phocus Inc E
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Priority claimed from US10/229,955 external-priority patent/US7411233B2/en
Priority claimed from US10/229,956 external-priority patent/US6798033B2/en
Priority claimed from US10/229,953 external-priority patent/US20040041930A1/en
Priority claimed from US10/229,954 external-priority patent/US6791130B2/en
Priority claimed from US10/371,618 external-priority patent/US6730900B2/en
Application filed by Phocus Inc E filed Critical Phocus Inc E
Publication of TW200405718A publication Critical patent/TW200405718A/en
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Publication of TWI268098B publication Critical patent/TWI268098B/en

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Abstract

A MOS or CMOS based photoconductor on active pixel image sensor. Thin layers of semi-conductor material, doped to PIN or NIP photoconducting layers, located above MOS and/or CMOS pixel circuits produce an array of layered photodiodes. Positive and negative charges produced in the layered photodiodes are collected and stored as electrical charges in the MOS and/or CMOS pixel circuits. The present invention also provides additional MOS or CMOS circuits for reading out the charges and for converting the charges into images. With the layered photodiode of each pixel fabricated as continuous layers of charge generating material on top of the MOS and/or CMOS pixel circuits, extremely small pixels are possible with almost 100 percent packing factors. MOS and CMOS fabrication techniques permit sensor fabrication at very low costs. In preferred embodiments all of the sensor circuits are incorporated on or in a single crystalline substrate along with the sensor pixel circuits. Techniques are disclosed for tailoring the spectral response of the sensor for particular applications.

Description

200405718 玖、發明說明: 一、發明所屬之技術領域 本發明為美國專利申請號 1〇/〇72,637(申請於 2/5/2002)、10/229,953(申請於 8/27/2002)、10/229,954(申 請於 8/27/2002)、10/229,955(申請於 8/27/2002)、 10/229,956(申請於 8/27/2002)及 10/371,618(申請於 2/22/2003)之邵份接續案(Continuation In Part,CIP)。本發 明係關於一影像感測器,特別是關於基於MOS與CMOS 之影像感測器。 二、先前技術 一典型之電子影像感測器係由大量之微小光檢測器陣列 組成,總稱為一「畫素陣列」。該感測器通常產生代表每個 畫素點(電訊號,該電訊號之振幅與陣列中每個檢測器接 收到之光強度成正比。電子照相機中之影像元件產生一場 景的光影像且投影至書夺陸^丨丨u ^ ^ ^ ^ . ^ 土里京降列上,然後孩電子影像感測器 將該光影像轉換成一$万丨|1_ - 又糸列兒子訊號。該電子照相機一般包 號之元件’以將該影像轉換成數位 ^式k | ’影像即可由數位處理器進行處理,以進 行儲存、數位式傳輪或麵; 飞頒717。多種半導體元件可以用來獲 取該影像’其包括電符輕人— 合 件(Charge Coupled Device, CCD)、光電二極體陣列和、 ^ 卞〜和私何〉王入式兀件。最普遍之電子 影像感測器係使用Γγγι认 Κ ^ CCD檢測器陣列將光轉換成電子訊 號。CCD檢測器已存在多 、 年’且其技術已成熟並有良好發 展。CCD之一最大缺愛上产、人* ”、、在Α其與其他積體電路技術如金屬200405718 (1) Description of the invention: 1. Technical field to which the invention belongs The present invention is US Patent Application No. 10 / 〇72,637 (filed on 2/5/2002), 10 / 229,953 (filed on 8/27/2002), 10 / 229,954 (filed on 8/27/2002), 10 / 229,955 (filed on 8/27/2002), 10 / 229,956 (filed on 8/27/2002) and 10 / 371,618 (filed on 2/22/2003) Continuation In Part (CIP). The present invention relates to an image sensor, and more particularly to an image sensor based on MOS and CMOS. 2. Prior Technology A typical electronic image sensor is composed of a large number of tiny photodetector arrays, collectively referred to as a "pixel array". The sensor usually generates a signal representing each pixel (a signal, the amplitude of which is proportional to the intensity of the light received by each detector in the array. The image element in the electronic camera generates a light image of the scene and projects it Until the book wins ^ 丨 丨 u ^ ^ ^ ^. ^ Torikyo descends, and then the electronic image sensor converts the light image into a $ 10,000 丨 | 1_-and lists the signal of the son. The electronic camera is generally Package number of components 'to convert the image to digital ^ k |' The image can be processed by a digital processor for storage, digital transfer or surface; Flying 717. A variety of semiconductor components can be used to obtain the image 'It includes Charge Coupled Device (CCD), Photodiode Array, and ^ 卞 ~ 和 私 何> King-in-the-wood type. The most common electronic image sensor uses Γγγι K ^ CCD detector array converts light into electronic signals. CCD detectors have existed for many years, and their technology has matured and developed well. One of the biggest lack of CCDs is love for production, people *, Other integrated circuit technologies Metal

H:\HU\TYS\ii □案\87767\87767.DOC 200405718 氧化物半導體(Metal Oxide Semiconductor,MOS)或互補金 屬氧化物半導體(Complementary Metal Oxide Semiconductor,CMOS)技術不相容,因此CCD陣列之處 理電路必須設置於CCD元件外之晶片中。 現有另一態樣之影像感測器係基於MOS或CMOS技 術。該感測器通常在每個畫素内具有多個電晶體。最常見 之CMOS感測器設計係在每個畫素胞(pixel cell)内設有光 敏電路(photo-sensing circuitry)和主動電路(active circuitry),其稱為主動式畫素感測器(Active Pixel Sensor, APS)。該主動電路由多個藉由金屬線(metal line)内部互聯 之電晶體組成。如此一來,對可見光不透光之電路所佔據 之區域不能作為光感測之用。因此,每個畫素胞一般包含 光感測和非光感測電路。除與每個畫素胞結合之電路外, CMOS感測器亦具有其他數位訊號和類比訊號處理電路, 例如取樣和保持放大器(sample-and-hold amplifier)、類比 數位轉換器和數位訊號處理邏輯電路,其都被整合成一單 石(monolithic)元件。畫素陣列和其他數位和類比電路均使 用相同之基本製作流程加以製造。 使用CCD感測器之小型照相機一般需要消耗大量之能 量(相較於具有CMOS感測器之照相機),且需要高滿擺 幅(rail-to-rail)電壓擺動以操作CCD。這會引起目前移動式 電子裝置之問題,如手機和個人數位助理(Personal Digital Assistant,PDA)。另一方面,使用CMOS感測器之小型照 相機可提供能量消耗之解決方案,然而因矽基板之淺結合H: \ HU \ TYS \ ii □ case \ 87767 \ 87767.DOC 200405718 Metal Oxide Semiconductor (MOS) or Complementary Metal Oxide Semiconductor (CMOS) technologies are not compatible. The processing circuit must be placed in a wafer outside the CCD element. Another existing image sensor is based on MOS or CMOS technology. The sensor typically has multiple transistors in each pixel. The most common CMOS sensor design is to have photo-sensing circuitry and active circuitry in each pixel cell. This is called an active pixel sensor. Pixel Sensor, APS). The active circuit is composed of a plurality of transistors interconnected by metal lines. In this way, the area occupied by circuits that are not transparent to visible light cannot be used for light sensing. Therefore, each pixel cell generally contains light-sensing and non-light-sensing circuits. In addition to the circuits combined with each pixel cell, the CMOS sensor also has other digital signal and analog signal processing circuits, such as sample-and-hold amplifiers, analog digital converters, and digital signal processing logic. The circuits are all integrated into a monolithic element. Pixel arrays and other digital and analog circuits are manufactured using the same basic fabrication process. Small cameras using CCD sensors generally consume a large amount of energy (compared to cameras with CMOS sensors) and require high rail-to-rail voltage swings to operate the CCD. This can cause problems with current mobile electronic devices, such as mobile phones and Personal Digital Assistants (PDAs). On the other hand, small cameras using CMOS sensors can provide solutions for energy consumption, but due to the shallow integration of silicon substrates

H:\HU\TYS\進口案\87767\87767.DOC 200405718 (shallow junction)深度與其主動電晶體電路佔據了寶貴之 光感測所需面積,傳統使用CMOS之小型照相機受限於上 述CMOS主動式畫素感測器之固有特性,使得其光感測性 不佳。H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC 200405718 (shallow junction) depth and its active transistor circuit occupy the area needed for precious light sensing. Traditional small cameras using CMOS are limited to the above-mentioned CMOS active type The inherent characteristics of the pixel sensor make its light sensing poor.

美國專利第 5,528,043、5,886,353、5,998,794 和 6,1 63,030號係例示使用CMOS電路成像之習知技藝。該專 利已授權予申請者之雇主。第5,528,043號專利描述了在單 晶片上使用CMOS陣列之具有讀取電路之X射線檢測器。 在該例中,使用一單獨之處理器處理影像。第5,886,353 號專利描述一使用一氫化非晶矽層之一般畫素結構,如 p-i-n或p-n或者其他衍生物並結合CMOS電路用於該畫素 陣列。第5,998,794和6,163,030號專利描述了與一個畫 素底部之CMOS電路作電氣連接之各種方法。所有上述美 國專利將以引用的方式併入本文中。U.S. Patent Nos. 5,528,043, 5,886,353, 5,998,794, and 6,1 63,030 illustrate conventional techniques for imaging using CMOS circuits. The patent has been granted to the applicant's employer. Patent No. 5,528,043 describes an X-ray detector with a read circuit using a CMOS array on a single wafer. In this example, a separate processor is used to process the images. Patent No. 5,886,353 describes a general pixel structure using a hydrogenated amorphous silicon layer, such as p-i-n or p-n or other derivatives in combination with a CMOS circuit for the pixel array. Patent Nos. 5,998,794 and 6,163,030 describe various methods for making electrical connections to CMOS circuits at the bottom of a pixel. All of the aforementioned U.S. patents are incorporated herein by reference.

將CMOS或MOS感測器與外部處理器進行整合會增加 複雜性和導致生產成本之提升,故需要一種改良之影像感 測技術,其相較於先前之感測器能夠提供低成本、高品質、 高性能和較小尺寸之影像感測器。 三、發明内容 本發明提供了一種設有MOS或CMOS光電導器之主動式 畫素影像感測器。摻雜至PIN或NIP光電導層,且位於MOS 或CMOS畫素電路上之薄半導體材料層產生分層之光電二 極體陣列。該分層之光電二極體内產生之正、負電荷被收 集並儲存於MOS或CMOS畫素電路。本發明亦提供了附加Integrating a CMOS or MOS sensor with an external processor will increase complexity and increase production costs. Therefore, an improved image sensing technology is needed, which can provide low cost and high quality compared to previous sensors. , High performance and smaller size image sensor. 3. Summary of the Invention The present invention provides an active pixel image sensor provided with a MOS or CMOS photoconductor. A thin semiconductor material layer doped into a PIN or NIP photoconductive layer and located on a MOS or CMOS pixel circuit creates a layered photodiode array. The positive and negative charges generated in the layered photodiode are collected and stored in a MOS or CMOS pixel circuit. The invention also provides additional

H:\HU\TYS·口案\87767\87767.DOC 200405718H: \ HU \ TYS · mouth case \ 87767 \ 87767.DOC 200405718

之MOS或CMOS電路以讀取該電荷並將其轉換成影像。藉 由每個畫素之分層光電二極體加工為在MOS和/或CMOS 畫素電路頂部之電荷產生材料之連續層,極小之畫素可能 具有幾乎100%之裝填係數(packing factor)。利用MOS或 CMOS之製造技術可使得感測器的製造成本非常低。在較 佳實施例中,所有感測器電路與感測器畫素電路一起整合 在單一結晶基板内或上。本發明亦揭示適用於特殊應用之 感測器之頻譜回應設計技術。例如,在較佳實施例中,感 測器之頻譜範圍能夠調整為覆蓋紫外線和近紅外線以及可 見光範圍或者該廣大範圍之任意部分。本發明之一些較佳 實施例包括將畫素間之串擾(cross talk)最小化之附加特 徵。該附加特徵包括每個畫素點中有一閘極偏壓電晶體 (gate bias transistor),以維持每個畫素之電荷收集單元务 大致相同之電位(electrical potential)。在另外之實施例中, 為增加其電阻,於圍繞於電荷收集單元周圍之半導體材料 中摻雜碳。該實施例提供了高於50%之量子效率以及等於 甚至低於幾百微秒(microsecond)之極快回應時間。 在特定之較佳實施例中,感測器係一具有5微米方形畫素 之30萬畫素陣列(3.2毫米X 2.4毫米,640x480),其與1/4.5 英寸光學格式之鏡頭相容。在該較佳實施例中,感測器和 聚焦光學元件整合於手機式照相機中,以允許在語音通信 同時傳輸視訊影像。結果造成低成本之照相機大批f生 產,且可以做得非常小(例如,比人眼小)。高於30萬畫 素之照相機大批量生產之成本計劃將低於每台10美元。較MOS or CMOS circuit to read the charge and convert it into an image. By processing the layered photodiodes of each pixel as a continuous layer of charge generating material on top of MOS and / or CMOS pixel circuits, extremely small pixels may have a packing factor of almost 100%. Using MOS or CMOS manufacturing technology can make the manufacturing cost of the sensor very low. In a preferred embodiment, all the sensor circuits are integrated into or on a single crystalline substrate together with the sensor pixel circuits. The invention also discloses a spectrum response design technique of a sensor suitable for a particular application. For example, in the preferred embodiment, the spectral range of the sensor can be adjusted to cover ultraviolet and near-infrared and visible light ranges, or any portion of that wide range. Some preferred embodiments of the present invention include additional features that minimize cross talk between pixels. This additional feature includes a gate bias transistor in each pixel point to maintain the electrical potential of the charge collection unit of each pixel to be approximately the same. In another embodiment, in order to increase its resistance, carbon is doped in the semiconductor material surrounding the charge collection unit. This embodiment provides a quantum efficiency higher than 50% and an extremely fast response time equal to or even a few hundred microseconds. In a particularly preferred embodiment, the sensor is a 300,000 pixel array (3.2 mm x 2.4 mm, 640 x 480) with 5 micron square pixels, which is compatible with lenses in 1 / 4.5 inch optical format. In the preferred embodiment, the sensor and focusing optics are integrated into a mobile phone camera to allow simultaneous transmission of video images during voice communications. As a result, low-cost cameras are produced in large numbers and can be made very small (for example, smaller than the human eye). The cost of mass production of cameras above 300,000 pixels is planned to be less than $ 10 per unit. Compare

H:\HU\TYS\進口案\87767\87767.DOC 200405718 佳實施例亦包括具有高量子效率、快速回應時間,且具有 =畫素陣列之紫外線和紅外線照相機,例如2㈣畫素之高 畫質電視(high definition televisi〇n)格式感測器。 四、實施方式 第一較佳實施例 具有主動式畫素感測器上之光電導體之單晶片照相機 電路之一 測器為「 、本:明之-較佳實施例係一具有由光電二極體陣列組成之 二、!J早晶片照相機,該光電二極體陣列係由位於 王動式陣列頂部之光電導層構成。(申請者稱該感 P0AP 感測器」,P0AP 係 ph〇t〇c〇nduct〇r 〇n ActiveH: \ HU \ TYS \ import case \ 87767 \ 87767.DOC 200405718 The preferred embodiment also includes ultraviolet and infrared cameras with high quantum efficiency, fast response time, and = pixel array, such as the high quality of 2 pixels TV (high definition television) format sensor. Fourth, the implementation of the first preferred embodiment of a single-chip camera circuit with a photoconductor on the active pixel sensor, a sensor is ", this: Ming-the preferred embodiment is a photodiode The second component of the array, the! J early wafer camera, the photodiode array is composed of a photoconductive layer on the top of the king-type array. (Applicant calls the P0AP sensor, and the P0AP is ph〇t〇c. 〇nduct〇r 〇n Active

Plxel之縮窝,即主動式畫素上之光電導體)。在該特定 感/則為中,307,200個畫素點排列成64〇χ48〇之畫素陣列, 同時在光電導層上有一透明電極。該畫素點係5微米Μ微米 大小,且其裝填率幾乎為1〇〇%。感測器之主動部份尺寸為 3·2耄米Χ2·4毫米,較佳鏡頭單元係一具有1/4·5英寸光學 才口式之t孚鏡頭。該照相機之一較佳應用係作為圖1Α和圖 B中之手機元件。在圖丨a中,該照相機係手機2a之一整 肢邵分,而鏡頭則顯示於圖4A中。圖1B中,相機6與手機 2B分開並通過3針式連接器10相連接。該照相機之鏡頭顯 示在圖4B中,圖中標號8顯示了相機之護蓋。圖1 c係〜方 塊圖,其包含鏡頭4、鏡頭座12、影像晶片14、感測器畫素 陣列100、電路板16以及針式連接器1〇,用以顯示圖中 照相機4B之主要功能。 CMOS感測器Plxel's dimples, which are photoconductors on active pixels). In this particular sense, 307,200 pixel dots are arranged in a 64 × 480 pixel array, and there is a transparent electrode on the photoconductive layer. The pixel size is 5 micrometers and micrometers, and the filling rate is almost 100%. The size of the active part of the sensor is 3.2mm x 2.4mm. The preferred lens unit is a t-shaped lens with 1/4 · 5 inch optics. One of the preferred applications of this camera is as a mobile phone component in Figs. 1A and B. In Fig.a, the camera is a whole limb of a mobile phone 2a, and the lens is shown in Fig. 4A. In FIG. 1B, the camera 6 is separated from the mobile phone 2B and connected through a 3-pin connector 10. The lens of the camera is shown in Fig. 4B, and reference numeral 8 in the figure shows the cover of the camera. FIG. 1 c is a block diagram, which includes a lens 4, a lens holder 12, an image chip 14, a sensor pixel array 100, a circuit board 16, and a pin connector 10 for displaying the main functions of the camera 4B in the figure . CMOS sensor

HAHUVrYS\進口案\87767\87767.DOC -10- 200405718 該感測器畫素陣列藉由—主動式畫素陣列上之光電導器、 讀取電路、讀取時序/控制電路、感測器時序/控制電ς和 類比數位轉換電路加以實現。該感測器包括: 1. 一基於CMOS之晝素陣列,包括64〇χ48〇之電荷收隹 器與640x480之CMOS畫素電路;及 术 2. - CMOS讀取電路,包括類比數位(At〇D)轉換和時序 控制電路。 該感測器陣列與美國5,886,353號專利於技術背景中描述 (可見光感測器陣列類似(特別見於文字第19至Μ攔及圖 27),其將以引用的方式併人本文中。各種感測器陣列之詳 細說明亦描述於本說明書之第六頁所列之專利,其亦將以引 用的方式併入本文中。目2、3A、3B和3C描述該手機式照 相機之較佳感測器陣列之特徵。該感測器之一般佈局係顯示 於圖2中之標號100。該感測器包括畫素陣列1〇2及讀取和 時序/控制電路104。圖3A顯示了該畫素陣列之一五晝素部 分之分層結構。 该感測条陣列覆盍有彩色濾光片(c〇l〇r filter),每個晝素只 塗覆一種彩色濾光片以限制只有彩色頻譜中之一成分能夠傳 輸通過。較佳彩色濾光片套件由三種寬帶(br〇adband)之彩色 滤光片組成,其傳輸峰值分別在450奈米(藍光)、550奈 米(綠光)和630奈米(紅光)。對藍光和綠光濾光片而言, 奋亥彩色滤光片之半南王見(full width at half maximum)約為50 奈米。紅光濾光片一般允許近紅外線之所有光線之傳輸。對 於可見影像之應用,需要紅外線截止(cut-0ff)濾光片用以調 H:\HU\TYS\進口案\87767\87767.DOC -11 - 200405718 整紅光回應之峰值在630奈米,且其半高全寬為50奈米。該 遽光片用於可見光感測應用。如圖3 C所示,四個畫素形成 一四件式套組。四畫素中之二個覆蓋上傳輸峰值在55〇奈米 <彩色濾光片,其稱為「綠光畫素」。一畫素覆蓋上傳輸峰 值在450奈米(藍光畫素)之彩色濾光片,另一畫素覆蓋上 傳輸峰值在630奈米(紅光畫素)之彩色濾光片。該二個綠 光畫素放置在該四件式套組之右上方和左下方。該紅光畫素 置於该四件式套組之左上方,該藍光畫素則置於該四件式套 組之右下方。該覆蓋有彩色濾光片之四件式套組重覆放置在 整個640x480陣列。圖3A顯示了 一頂部滤光層1〇6,其中綠 光和藍光濾光片交替穿插於一列畫素。 於濾光層下係一透明表面電極層1〇8,其由大約〇 〇6微米 厚之錮錫氧化物(Indium Tin Oxide,ITO)層組成,其具導電 性,且可見光在該層可進行傳輸。 光電導層 在圖3A巾,於傳導表面電極層之下係一由三個子層組成 之光電導層。最上面之子層為大約〇〇〇5微米厚之η型摻雜 虱化非晶咬層110’其下方係大約〇·5微米厚之非摻雜氣化非 晶矽層112。該112層稱為為「本徵(intrinsic)」層。除非光 子照射,該本徵層表現為具有高電阻率。在非接雜層ιΐ2下 面係大約0·01微米厚,且具有高電阻率之?型摻雜氫化非晶 石夕層114。肖Ν型摻雜而| ’較佳之鱗接雜濃度大約在 原子/立方I米範圍内。對p型摻雜而言,較佳之臀雜濃 度大約在,原子/立方釐米範圍内。該三層氫化非晶石夕層HAHUVrYS \ import case \ 87767 \ 87767.DOC -10- 200405718 The sensor pixel array is based on the photoconductive device, reading circuit, reading timing / control circuit, and sensor timing on the active pixel array. / Control electronics and analog digital conversion circuits. The sensor includes: 1. a CMOS-based daylight array, including a 64 × 480 × charge receiver and a 640 × 480 CMOS pixel circuit; and 2. a CMOS reading circuit, including analog digital (At〇 D) Conversion and timing control circuits. This sensor array is described in the US Patent No. 5,886,353 in the technical background (visible light sensor arrays are similar (especially in texts 19 to 24 and Figure 27), which will be incorporated herein by reference. Various sensing A detailed description of the sensor array is also described in the patents listed on page 6 of this specification, which will also be incorporated herein by reference. Heads 2, 3A, 3B, and 3C describe preferred sensors for the mobile phone camera. Characteristics of the array. The general layout of the sensor is shown as 100 in Figure 2. The sensor includes a pixel array 102 and a read and timing / control circuit 104. Figure 3A shows the pixel array One of the layered structures of the five-day element. The sensor strip array is covered with a color filter (collor filter), each day element is coated with only one color filter to limit only the color spectrum One component can be transmitted through. The preferred color filter kit is composed of three types of broadband color filters, with transmission peaks at 450 nm (blue), 550 nm (green), and 630. Nano (red). For blue and green filters, The full width at half maximum of Fenhai color filter is about 50 nanometers. The red light filter generally allows transmission of all light rays in the near infrared. For the application of visible images, infrared cut-off is required ( cut-0ff) filter is used to adjust H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -11-200405718 The peak value of the red light response is 630 nm, and its full width at half maximum is 50 nm. The Kallas are used for visible light sensing applications. As shown in Figure 3C, four pixels form a four-piece set. Two of the four pixels cover a transmission peak at 55 nm < color filter Film, which is called "green light pixels". One pixel covers a color filter with a transmission peak at 450 nm (blue light pixels), and the other pixel covers a transmission peak at 630 nm (red light pixels). Color filter. The two green pixels are placed on the upper right and lower left of the four-piece set. The red pixels are placed on the upper left of the four-piece set. The blue light picture The four-piece set is placed at the bottom right of the four-piece set. The four-piece set covered with color filters is repeatedly placed over the entire 640x48 0 array. Figure 3A shows a top filter layer 106, in which green and blue filters are alternately interspersed in a row of pixels. Below the filter layer is a transparent surface electrode layer 108, which consists of about 0. 〇6 micron thick Indium Tin Oxide (ITO) layer, which is conductive, and visible light can be transmitted in this layer. The photoconductive layer is shown in Figure 3A, under the conductive surface electrode layer A photoconductive layer composed of three sub-layers. The uppermost sub-layer is an n-type doped lice-crystallized amorphous bite layer 110 'with a thickness of about 0.05 micrometers, and a non-doped gasification layer with a thickness of about 0.5 micrometers below it. Amorphous silicon layer 112. The 112 layers are called "intrinsic" layers. Except for photon irradiation, this intrinsic layer appears to have high resistivity. Under the non-doped layer ιΐ2 is about 0.01 micrometers thick and has a high resistivity? Type doped hydrogenated amorphous stone layer 114. In the case of N-type doping, | 'a preferred scale doping concentration is in the range of about 1 atom per cubic meter. For p-type doping, the preferred hip impurity concentration is in the range of atoms / cm3. The three-layer hydrogenated amorphous stone layer

H:\HU\TYS\進口案\87767\87767.DOC -12- 200405718 在每個畫素電路上產生二極體效應。中請者稱該層4叫-p 或P-I-N光電導層。 PIN和NIP層H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -12- 200405718 produces a diode effect on each pixel circuit. Applicants claim that this layer 4 is called -p or P-I-N photoconductive layer. PIN and NIP layers

本發明之一非常重要之要素係主動式MOS或CMOS電路 上之光導材料之本徵層和摻雜層之佈局。讀者應該明白,上 述層之放置順序可以顛倒。即鄰近透明上電極層108者可以 為P型摻雜層’且該情況鄰近下畫素電極者可以為η型層。 -本徵層則位於ρ型層和“層之間。大多數電荷對⑽ pairs)係在本欲層内產生。申請者於該說明書和申請專利範圍 中將以:奪冪順序進行引用,即p型層靠近該透明上電極層而 η型層靠近畫素電極,M(ph〇t〇electric)層可為piN光電層 (或者PIN層);在相反情況下,該配置將為Νιρ光電層(或 者私為NIP層)。例如,圖3 a之實施例中所示光電層為驗A very important element of the present invention is the layout of the intrinsic layer and the doped layer of the light guide material on an active MOS or CMOS circuit. The reader should understand that the order in which the layers are placed can be reversed. That is, those adjacent to the transparent upper electrode layer 108 may be a P-type doped layer 'and in this case, those adjacent to the lower pixel electrode may be an n-type layer. -The intrinsic layer is located between the ρ-type layer and the "layer. Most charge pairs (⑽ pairs) are generated in the intrinsic layer. The applicant in this specification and the scope of the patent application will be cited in the order of power: The p-type layer is close to the transparent upper electrode layer and the η-type layer is close to the pixel electrode. The M (ph0toelectric) layer may be a piN photovoltaic layer (or a PIN layer); in the opposite case, the configuration will be a Νρ photovoltaic layer (Or the private NIP layer.) For example, the optoelectronic layer shown in the embodiment of FIG.

層,圖4所示之實施例中則為PIN層。於下面-些實施例; 詳細況明中,申請者於p型層和本徵層之間增加了 —阻障^ (與本徵層相似,但更薄並且稍微摻雜了碳),該光電層系 為PBIN層或NIBP層。以下將詳細描述布置該層之技術。 於孩說明書詳細描述之較佳實施例中,所有光電層均係施 以反向偏壓’因此對於如圖3A之實施例之典型聊配置, 万、每個甩何儲存(電荷累積)階段前之重置操作期間,一如 + 3.3V之正偏壓電荷加於透明上導電層,而畫素電容則通過 重置甩曰曰體接地。在電荷累積過程中,光電導層產生之正 電荷^電容246以提升其電位。快速反應電晶體讀取該增 南之電位。充電後或讀取電容後,該電容通過-重置電晶體Layer in the embodiment shown in FIG. 4 is a PIN layer. In the following examples: In the detailed description, the applicant added a barrier between the p-type layer and the intrinsic layer ^ (similar to the intrinsic layer, but thinner and slightly doped with carbon). The photovoltaic layer system It is the PBIN layer or the NIBP layer. The technique of arranging this layer will be described in detail below. In the preferred embodiment described in detail in the instruction manual, all optoelectronic layers are reverse biased. Therefore, for the typical configuration of the embodiment shown in FIG. 3A, before each storage (charge accumulation) stage, During the reset operation, a positive bias charge of + 3.3V is applied to the transparent upper conductive layer, and the pixel capacitor is grounded by resetting. During the charge accumulation process, the positive charge generated by the photoconductive layer capacitor 246 increases its potential. The fast response transistor reads the potential of this increase. After charging or reading the capacitor, the capacitor passes-reset transistor

H:\HU\TYS\進口案\87767\87767.DOC -13- 200405718 接地。該重置操作將畫素電容(圖3B中所示246)上之電壓 降低到大約0.7V之電晶體門檻電壓。 對於如圖5和6中描述之PIN配置,在每次重置操作過程 中,透明電極355接地而畫素電容正向充電至大約2.7V。在 該情況下之累積過程中,由PIN光電二極體層產生電荷所形 成之負電荷電流將流向畫素電容以進行部份放電。正電荷流 向透明電極355後接地。在該情況下,畫素電容上電壓之降 低係累積過程中畫素所偵測光照之測量值。當讀取該電荷之 降低電壓後,該畫素電容在重置步驟中再次被充電到2.7伏 左右。 增加大約1〇22原子/立方釐米之碳原子或分子至圖3A中 之層114以增加其電阻。這將畫素點和其對應之空間解析度 損失之間之橫向串擾減少到最小。該PIN光電導層不是利用 微影(lithography)製程進行圖案化,而係均勻之薄膜結構(在 水平面内),這樣簡化了製程。在該子層114内為307,200 個4.6 X 4.6微米之電極116,其定義了較佳感測器陣列中之 3 07,200個畫素。電極116係由氮化鈦(TiN)製成。電極116 之正下方係CMOS畫素電路118。於本文中,申請者稱該電 極116為「畫素電極」或「收集電極(collecting electrode)」。 該畫素收集電極結合上層透明電極用於供給光電導層内之壓 降,使得光產生之電荷流至儲存電容。圖3B說明畫素電路 118中之元件。該CMOS畫素電路118使用三個電晶體250、 248和260。美國專利5,886,353詳細描述一類似三電晶體畫 素電路之運作。該實施例中使用之電路係盡可能減少晶片面 托\111;\丁丫5\進□案\87767\87767.DOC -14- 200405718 積。說明書第六頁提到之申請專利詳細描述了其他更精細之 讀取電路,且在本說明書後敘部分詳細說明了其他實施例。 如圖3A所示,亦由氮化鈦組成之畫素收集電極11 6連接到 圖3B所示之電荷收集節點120。畫素電路118包括收集電極 116、收集電容246、源跟隨緩衝電晶體(source follower buffer transistor)248、選擇電晶體260及重置電晶體250。畫素電 路118以p型通道電晶體作為重置電晶體250,以η型通道 電晶體作為源跟隨電晶體248和選擇電晶體260。COL (輸 出)256上之電壓正比於收集電容246儲存之電荷Q(輸入)。 藉由二次讀取該節點,其中一次係光照射後,另一次係重置 後,其電壓差正比於該光敏結構122偵測到之光量。畫素電 路118之節點262處係正電壓Vcc(典型值為2.5到5V)。’353 號專利詳細描述了該陣列之畫素電路。’353號專利及本說明 書之後續章節中之其他實施例詳細描述了各種可能用於製造 圖3B感測器中元件之積體電路微影技術。 照相機之其他功能 如圖2所示之本較佳實施例中,額外MOS或CMOS電路 設置在用來收集電荷之相同結晶基板上,用於將電荷轉化成 電訊號、放大該訊號、將類比訊號轉化為數位訊號及數位訊 號處理。該感測器部分100輸出之資料為數位形式並具有連 續畫素流。該感測器晶片區域包括一標準時脈產生功能(這 裏沒有顯示,但在背景部分中提到之’353號專利有詳細描 述)。從其中可知,訊號代表幀框(frame)之起始、線之開始、 幀框之結束,線之結束,且畫素係分佈於影像晶片之所有部 H:\HU\TYS\ 進口案\87767\87767.DOC -15- 200405718 分以同步化資料流。 環境分析電路(environmental analyzer circuit): 感測器部分輸出之資料登錄到一資料分析電路14〇,在此 進行影像之統計。該感測器區域以分割成孤立之子區域較 佳,琢區域内之均值訊號與該區域内之個別訊號進行比較以 鐘別影像資料之特徵。例如,光照環境之下述特性係進行測 量: 1 ·影像平面中之光源亮度 % 2·白平衡(whitebalance)所需之光源頻譜組成 3·成像目標之反射率 4·成像目標之反射頻譜 5·成像目標之反射均勻性 將只^里像特徵提供至決定與控制電路(decision and 欠circmt) I44 ’且以不對資料分析電路刚中通過之影 r:改為佳。在本實施例中,被測量之影像特 ::值中第一基本色訊號之均值、第二基本色訊號 q / 色彩訊號之均值以及亮度訊號之均值。該 ^ ^ ^ ,, ^ ^ ^,但將計算資料之統計值並將 原始資料傳遞到影像處理 丁 149 n _ mage manipulation circuit) ㈣ 如最域和最小料其簡料訊。這此數 值對於判定目標之反射桌铲网心 、二數 P ^ -TL > ^ &和光照情況非常有用。對於色 Α貝釩<統計以在整個影像範 號之統計在各個子影像區域之基乂=車父佳,但是光照訊 用加權平均以_某—選定子=讀。執行上其允許使 nj區域之重要性,例如中心H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -13- 200405718 Grounding. This reset operation reduces the voltage on the pixel capacitor (246 shown in Figure 3B) to a transistor threshold voltage of about 0.7V. For the PIN configuration as described in Figures 5 and 6, during each reset operation, the transparent electrode 355 is grounded and the pixel capacitor is charged forward to approximately 2.7V. In the accumulation process in this case, the negative charge current formed by the charge generated by the PIN photodiode layer will flow to the pixel capacitor for partial discharge. The positive charge flows to the transparent electrode 355 and is grounded. In this case, the decrease in voltage across the pixel capacitor is the measured value of the light detected by the pixel during the accumulation process. When the reduced voltage of the charge is read, the pixel capacitor is charged again to about 2.7 volts in the reset step. Add about 1022 atoms / cm3 of carbon atoms or molecules to the layer 114 in Fig. 3A to increase its resistance. This minimizes horizontal crosstalk between the pixel points and their corresponding spatial resolution loss. The PIN photoconductive layer is not patterned using a lithography process, but has a uniform thin film structure (in the horizontal plane), which simplifies the manufacturing process. Within this sublayer 114 are 307,200 4.6 x 4.6 micron electrodes 116, which define 3,07,200 pixels in a better sensor array. The electrode 116 is made of titanium nitride (TiN). Directly below the electrode 116 is a CMOS pixel circuit 118. In this document, the applicant refers to the electrode 116 as a "pixel electrode" or a "collecting electrode." The pixel collecting electrode is used in combination with the upper transparent electrode to supply a voltage drop in the photoconductive layer, so that the charge generated by the light flows to the storage capacitor. FIG. 3B illustrates the elements in the pixel circuit 118. FIG. The CMOS pixel circuit 118 uses three transistors 250, 248, and 260. U.S. Patent 5,886,353 describes the operation of a tri-transistor pixel circuit in detail. The circuit used in this embodiment is to reduce the wafer surface support as much as possible \ 111; \ 丁 丫 5 \ 进 □ 案 \ 87767 \ 87767.DOC -14- 200405718. The patent application mentioned on the sixth page of the specification describes other finer reading circuits in detail, and other embodiments are explained in detail in the later part of this specification. As shown in FIG. 3A, a pixel collection electrode 116, which is also composed of titanium nitride, is connected to the charge collection node 120 shown in FIG. 3B. The pixel circuit 118 includes a collecting electrode 116, a collecting capacitor 246, a source follower buffer transistor 248, a selection transistor 260, and a reset transistor 250. The pixel circuit 118 uses a p-type channel transistor as the reset transistor 250, and an n-type channel transistor as a source to follow the transistor 248 and the selection transistor 260. The voltage on COL (output) 256 is proportional to the charge Q (input) stored by the collection capacitor 246. By reading the node twice, the voltage difference is proportional to the amount of light detected by the photosensitive structure 122 after the light is irradiated once and the reset is performed again. The node 262 of the pixel circuit 118 is a positive voltage Vcc (typically 2.5 to 5V). The '353 patent describes the pixel circuit of the array in detail. The '353 patent and other embodiments in subsequent sections of this specification describe in detail various integrated circuit lithography techniques that may be used to make the components in the sensor of Figure 3B. Other functions of the camera are shown in this preferred embodiment shown in FIG. 2. In the preferred embodiment, an additional MOS or CMOS circuit is provided on the same crystalline substrate used to collect the charge, which is used to convert the charge into an electrical signal, amplify the signal, and analog signals. Converted into digital signals and digital signal processing. The data output by the sensor section 100 is in digital form and has a continuous pixel stream. The sensor chip area includes a standard clock generation function (not shown here, but described in detail in the '353 patent mentioned in the background section). It can be seen that the signal represents the beginning of the frame, the beginning of the line, the end of the frame, and the end of the line, and the pixels are distributed in all parts of the image chip. H: \ HU \ TYS \ Import Case \ 87767 \ 87767.DOC -15- 200405718 minutes to synchronize the data stream. Environmental analyzer circuit: The data output by the sensor is registered in a data analysis circuit 14o, where the statistics of the images are performed. It is better to divide the sensor area into isolated sub-areas. The average signal in the cut area is compared with the individual signals in the area to distinguish the characteristics of the image data. For example, the following characteristics of the lighting environment are measured: 1 ·% of light source brightness in the image plane 2 · Spectrum composition of the light source required for white balance 3 · Reflectance of the imaging target 4 · Reflection spectrum of the imaging target 5 · The reflection uniformity of the imaging target will provide only the image features to the decision and control circuit (decision and less circmt) I44 ', and the image passing through the data analysis circuit r: will be changed to better. In this embodiment, the average value of the first basic color signal, the average value of the second basic color signal q / color signal, and the average value of the brightness signal among the measured image features. The ^ ^ ^ ,, ^ ^ ^, but the statistical value of the data will be calculated and the original data will be passed to the image processing. These values are very useful for determining the target's reflection table shovel mesh center, the binary P ^ -TL > ^ & and lighting conditions. As for the color A, the statistics are based on the statistics of the entire image model in each sub-image area. 乂 = Che Fujia, but the light weighted average is _some—selected child = read. Implementation of the importance of allowing it to make nj regions, such as the center

H:VHUVFYS\進口案\87767\87767.DOC -16- 200405718 區域。 決定與控制電路: 決定與控制電路144使用從資料分析儀14〇接收之影像參 數訊號進行自動曝光和自動白平衡(auto_white_baiance)fe 制’並評估所檢測之影像之品質。基於該評估,控制元件為 感測器1G0提供反饋訊號以更改感測輯提供之影像資料之 某些可調整方面。且控制元件為影像處理電路142提供控制 訊號和參數。該變化可基於子影像亦可基於整個影像。自控 制電路U4至感測器_之反饋訊號為感測器元素提供主動 式控制(基板、影像吸收層以及讀取電路)以將影像資料之 特徵進行最佳化。特別地,該反饋控制提供編程感測器之能 力以改.交感測益元素之運作(或控制參數)。在相機輸出 貝料之蓟,&供土该影像處理電路丨42之控制訊號和參數可 包括對影像資料之特定修正性改變。 影像處理電路: 影像處理電路142從資料分析儀接收影像資料,並考慮從 控制模組接收之控制訊號,從而提供一輸出影像資料訊號, 其中之訊號資料係基於一控制演算法針對其參數進行最佳 化。於該電路中,根據該演算法影像資料係逐個畫素進行處 理,以使每個畫素係由三個色彩要素所表示。色彩飽和度 (color saturation)、色調(c〇l〇r hue)、對比度(c〇ntrast)、亮度 (brightness)都可以進行調整以獲得預期之影像品質。影像處 理電路為每個畫素,以及同種彩色濾光片之相鄰畫素提供色 彩插值(interpolation),以使每個畫素能夠由三個色彩成分所 H:\HU\TYS\iin^\87767\87767.DOC -17- 200405718 表示。這料每個畫素而言已經提供了足夠之資訊,因此感 測器能夠為每個畫素產生人們能夠感知之色彩。同時其也能 夠進行色彩調整,因而感測器之色彩回應間之任何預期差異 和人類視角都可以得到最佳化。 通信協定電路: 通信協定電路146將從影像處理電路接收之影像資料重新 組織,使其下行(down-stream)設備符合通信協定,如工業標 準或專用標準。該協定可為串列位元(bit_serial)或並行位元 (bit-parallel)格式。較佳地,通信協定電路146將影像處理資 料轉換成亮度和色度成分,如ITU_RBT·601_4標準所述。藉 由忒貝料協足,該影像晶片之輸出可方便地使用於市場上之 其他元件上。其他協定也可以用於特定應用中。 輸入和輸出介面電路: 輸入和輸出介面電路148接收來自通信協定電路丨46之資 料,並將其轉化成下行設備可以偵測和認知之電訊號。在該 較佳實施例中,輸入和輸出介面電路148提供電路以使得外 部設備可以從影像晶片獲得資料,並從影像晶片之可編程參 數部分讀窝資訊。 晶片封裝: 該影像晶片係封裝於一具有玻璃罩之8毫米X8毫米之塑 膠晶片載器(chip carriei·)。根據經濟性和應用要求,其他型 式和尺寸之晶片載器亦可加以使用。該玻璃罩可由其他型式 之透明物代替。該破璃罩可以塗有一抗反射層 (anti-reflectance coating)或紅外線截止濾光片(infraredH: VHUVFYS \ import case \ 87767 \ 87767.DOC -16- 200405718 area. Decision and control circuit: The decision and control circuit 144 uses the image parameter signal received from the data analyzer 140 to perform automatic exposure and auto_white_baiance (feature control) and evaluates the quality of the detected image. Based on this evaluation, the control element provides a feedback signal to the sensor 1G0 to modify some adjustable aspects of the image data provided by the sensor series. And the control element provides control signals and parameters for the image processing circuit 142. This change can be based on the sub-image or the entire image. The feedback signal from the self-control circuit U4 to the sensor_ provides active control for the sensor elements (substrate, image absorption layer, and reading circuit) to optimize the characteristics of the image data. In particular, the feedback control provides the ability to program the sensor to modify the operation (or control parameters) of the sensing element. The output signal from the camera, the control signals and parameters of the image processing circuit 42 may include specific corrective changes to the image data. Image processing circuit: The image processing circuit 142 receives the image data from the data analyzer and considers the control signal received from the control module to provide an output image data signal. The signal data is based on a control algorithm to optimize its parameters. Optimization. In this circuit, the image data is processed pixel by pixel according to the algorithm, so that each pixel is represented by three color elements. Color saturation, color hue, contrast, brightness can be adjusted to obtain the desired image quality. The image processing circuit provides color interpolation for each pixel and adjacent pixels of the same color filter, so that each pixel can be represented by three color components H: \ HU \ TYS \ iin ^ \ 87767 \ 87767.DOC -17- 200405718. This material has provided enough information for each pixel, so the sensor can generate a color that people can perceive for each pixel. At the same time, it is also capable of color adjustment, so that any expected difference between the color response of the sensor and the human perspective can be optimized. Communication protocol circuit: The communication protocol circuit 146 reorganizes the image data received from the image processing circuit so that its down-stream equipment conforms to the communication protocol, such as an industrial standard or a dedicated standard. The protocol can be in bit_serial or bit-parallel format. Preferably, the communication protocol circuit 146 converts the image processing data into luminance and chrominance components, as described in the ITU_RBT · 601_4 standard. The output of the image chip can be easily used on other components on the market by cooperating with the materials. Other agreements can also be used in specific applications. Input and output interface circuit: The input and output interface circuit 148 receives the data from the communication protocol circuit 46 and converts it into electrical signals that can be detected and recognized by downstream equipment. In the preferred embodiment, the input and output interface circuit 148 provides circuitry so that external devices can obtain data from the image chip and read nest information from the programmable parameter portion of the image chip. Chip package: The image chip is packaged in a 8mm x 8mm plastic chip carrier (chip carrie) with a glass cover. Depending on economy and application requirements, other types and sizes of wafer carriers can also be used. The glass cover can be replaced by other types of transparent objects. The broken glass cover can be coated with an anti-reflectance coating or an infrared cut filter.

H:\HU\TYS\MLM\87767\87767.DOC -18 - 200405718 曰off filter*)。在另—實施例中,如果該模組係由—安裝影 象曰曰片之基板所货封,且與鏡頭座組合於高潔淨度之潔淨室 作為遮蓋,則可不需該玻璃罩。 照相機 圖1C中所不之鏡頭4係基於i/4 5,f 8之光學格式,並 具有聚焦範m為3至5米之固定焦距。因為該晶片之尺寸較 小因此整個照相機模組可以小於1G毫米(長)xl〇毫米 (寬)Χίο晕米(高),其實際上比人眼球還要小!如此小 巧之模組非常適合於攜帶型電子裝置,如手機。鏡頭座Ρ 由黑色塑膠製成以防止光淺漏和内部反射。該影像晶片插入 四面具有單向凹痕之鏡頭座,且當影像晶片插入並牢靠地拴 緊時即提供-獨立單元。該模組在8毫米χ8毫米晶片載體 上具有金屬引線,其可焊接到典型之電路板上。 反饋和控制例 照相機曝光控制: 感測裔100可以作為光檢測器用以測定照明條件。因為感 測器訊號與每個畫素檢測到之光成正比,所以相機可以進行 杈正以產生一預設光位準(lighting level)下之「標稱」訊號。 當訊號低於該「標稱」值時,意味著周圍之「光位準」低於 預期。為使電訊號恢復到「標稱」位準,畫素之曝光時間和 /或感測裔或者;像處理模組中之訊號放大係數可以自動士周 整。該相機可以編程為將整個影像劃分成幾個子區域,以確 保操作之變化能夠基於一子區域或者使在意的區域占有較大 之權值。 H:\HU\TYS\iiPS\87767\87767.DOC -19- 200405718 照相機之白平衡控制: 該相機能夠在任何「光源」下使用。每個光源可能有不同 之頻譜分佈,結果導致在不同之光源下感測器之訊號輸出可 能不同。然而用戶可能希望在不同之顯示設備上顯示影像 時,例如當列印於紙上或顯示於陰極射線管(Cath〇de Ray Tube,CRT)頦示為上時能夠顯示同樣之影像。這意味著不同 <光源(日光、閃光、鎢絲燈泡等)都應該視為一白色物體。 因為感測器具有主要彩色濾光片覆蓋之畫素,因此相機能夠 編程以測疋由影像資料來之光源之相對強度。環境分析儀用 以接收々像之統計資料並測定頻譜成分,且在感測器操作或 影像處理時進行必要之參數調整以產生一訊號,其能夠顯示 和人們在白光下感覺一樣之影像。 其他POAP感測器畫素胞陣列 具有減低串擾之POAP陣列 圖4係具有減低串擾之poAp感測器3〇〇之較佳實施例之 截面圖。如圖所示’感測器300包含一基板310和PIN層350、 345及3 40 ’與圖3A所示感測器相似(除了圖3A中感測器 之層順序係相反以提供一 NIP層外)。該圖4中之感測器另 包含連續形成於基板31〇之上且piN層之下之底層、中間層 和上層之互連結構315、32〇和325。在該實施例中,金屬過 孔(via) 335係作為畫素電極之用,其係通過多重互連結構而 連接至下方之畫素電路。感測器畫素陣列之每個畫素包括設 置於基板310上之過孔335、互連結構315、32〇和金屬線 336。如將要在這裏詳細說明者,基板31〇包含畫素胞電路。H: \ HU \ TYS \ MLM \ 87767 \ 87767.DOC -18-200405718 (off filter *). In another embodiment, if the module is enclosed by the substrate of the installation image, and is combined with the lens holder in a high-cleanness clean room as a cover, the glass cover may not be needed. Camera The lens 4 shown in Fig. 1C is based on the optical format of i / 4 5, f 8, and has a fixed focal length of 3 to 5 meters. Because the size of the chip is small, the entire camera module can be less than 1G mm (length) x 10 mm (width) Xίο halo (height), which is actually smaller than human eyes! Such a compact module is very suitable for portable electronic devices such as mobile phones. The lens mount P is made of black plastic to prevent light leakage and internal reflection. The image chip is inserted into a lens holder with unidirectional indentations on all sides, and is provided as an independent unit when the image chip is inserted and securely fastened. The module has metal leads on an 8mm x 8mm wafer carrier, which can be soldered to a typical circuit board. Feedback and control examples Camera exposure control: The sensor 100 can be used as a light detector to determine lighting conditions. Because the sensor signal is directly proportional to the light detected by each pixel, the camera can perform directing to generate a "nominal" signal at a preset lighting level. When the signal is lower than the “nominal” value, it means that the surrounding “light level” is lower than expected. In order to restore the telecommunication signal to the "nominal" level, the exposure time of the pixels and / or the sensor generation or; the signal amplification factor in the image processing module can be automatically adjusted. The camera can be programmed to divide the entire image into several sub-regions to ensure that changes in operation can be based on a sub-region or to give greater weight to the region of interest. H: \ HU \ TYS \ iiPS \ 87767 \ 87767.DOC -19- 200405718 Camera White Balance Control: The camera can be used under any "light source". Each light source may have a different spectral distribution. As a result, the signal output of the sensor may be different under different light sources. However, users may wish to display the same image when displayed on different display devices, such as when printed on paper or displayed on a Cathode Ray Tube (CRT). This means that different < light sources (daylight, flash, tungsten bulb, etc.) should be treated as a white object. Because the sensor has pixels covered by the main color filters, the camera can be programmed to measure the relative intensity of the light source from the image data. The environmental analyzer is used to receive the statistical data of the artifacts and determine the spectral components, and perform the necessary parameter adjustments during the operation of the sensor or the image processing to generate a signal that can display the same image as people feel under white light. Other POAP sensor pixel cell arrays POAP array with reduced crosstalk Figure 4 is a cross-sectional view of a preferred embodiment of a poAp sensor 300 with reduced crosstalk. As shown in the figure, 'the sensor 300 includes a substrate 310 and PIN layers 350, 345, and 3 40' is similar to the sensor shown in FIG. 3A (except that the layer order of the sensors in FIG. 3A is reversed to provide a NIP layer outer). The sensor in FIG. 4 further includes interconnection structures 315, 32, and 325 of the bottom layer, the middle layer, and the upper layer which are continuously formed on the substrate 31 and below the piN layer. In this embodiment, a metal via 335 is used as a pixel electrode, which is connected to a pixel circuit below through a multiple interconnection structure. Each pixel of the sensor pixel array includes a via 335 provided on the substrate 310, interconnect structures 315, 32, and metal lines 336. As will be described in detail here, the substrate 31 includes a pixel cell circuit.

H:\HU\TYS\進口案\87767\87767.DOC -20- 200405718 巧只施例中之電路包括減低串擾之附加功能。 I η型層34〇形成在與上層互連結構π〗相鄰之位置。 土層345形成於與η型層34〇相鄰之位置,而ρ型層35〇形 成方、與1型層345相鄰之位置。該ρ型層350、i型層345和 n層340形成—觸層,其與下面描述之其他元素—起構成 IN光私一極體感測器陣列,其在此亦稱為畫素感測器。 層區域藉由傳導過孔335以及金屬化區域336電氣連接到畫 素私路(圖中,又有顯不)。一半透明之傳導層設置在ρ 型層3 5 0之相鄰位置。 底層和中間層互連結構315和320為標準之cm〇s互連結 ”由非苇薄之’巴緣材料(如Si〇2)組成並具有穿過絕緣 材料之傳導結構為佳。該CMQS互連結構包含圖4所示之過 孔335和金屬化區域336並包含傳導結構(沒有顯示在圖 中),提供與圖5中標號337所示互連結構下之畫素電晶體 《電氣連接。上層互連結構325與315層和32〇層_似, ^旱一些難,讀供更高之可隸和結構㈣。讀者應該 日白上叙層皆係精由眾所周知之積體電路製造技術製造, 而這些圖(如圖4)並不是要說明詳細之製程,例如金屬化 區域及過孔製造技術(例如過孔—般不放置於其他過孔之頂 ^。然而’該圖確實顯示感測器之各種元件之—般互連刑' 態。 土H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -20- 200405718 It is only the circuit in the example that includes the additional function of reducing crosstalk. The I n-type layer 34 is formed at a position adjacent to the upper interconnection structure π. The soil layer 345 is formed adjacent to the n-type layer 34o, and the p-type layer 35o is formed in a square and adjacent to the 1-type layer 345. The p-type layer 350, i-type layer 345, and n-layer 340 form a contact layer, which, together with other elements described below, form an IN light sensor array, which is also referred to herein as pixel sensing. Device. The layer region is electrically connected to the pixel private circuit through the conductive via 335 and the metallized region 336 (shown in the figure again). The semi-transparent conductive layer is disposed adjacent to the p-type layer 350. The bottom and middle layer interconnect structures 315 and 320 are standard cm0s interconnects. It is composed of a non-thin thin sill material (such as SiO2) and has a conductive structure passing through the insulating material. The CMQS mutual The connection structure includes the via 335 and the metallized region 336 shown in FIG. 4 and includes a conductive structure (not shown in the figure). It provides electrical connection with the pixel transistor “under the interconnection structure shown by reference numeral 337 in FIG. 5. The upper layer interconnect structure 325 is similar to 315 layers and 32 layers. ^ Some difficulties are difficult to read, and the structure can be read higher. The reader should understand that the upper layers are made by well-known integrated circuit manufacturing technology. These diagrams (see Figure 4) are not intended to illustrate detailed processes, such as metallized areas and via manufacturing techniques (such as vias-they are usually not placed on top of other vias ^. However, the diagram does show sensing The various components of the device are generally connected to each other.

•Γ丄丄N N灯表垅較佳,如氫>(| 晶矽。其他可能製造PIN層之材料包括 u伍非結晶碳、非晶石 化物、非晶錯和非晶♦錯。於齡彳去余、> 於1 又佳貝施例中,透明傳導層 -21 -• Γ 丄 丄 NN lamp table is better, such as hydrogen> (| crystalline silicon. Other materials that may be used to make the PIN layer include u-amorphous carbon, amorphous petrochemicals, amorphous silicon, and amorphous silicon. Yu Ling彳 去 余, > In the 1st best case, the transparent conductive layer -21-

H:\HU\TYS\進口案\87767\87767.DOC 43! 200405718 亦可以銦錫氧化物為材料。然而,其他傳導性材料亦可使用 以Φ成透明傳導層355,包括錫氧化物、氮化鈥、薄秒化物 八頌似材料。保護層(沒有顯示於圖中)亦可形成於該透 明傳導層355上。 感測器製造 、可使用任何習知之CMQS (或MQs)製造技術製造本發明 ^感測器。例如,可以使用眾所周知之〇·25微米微影技術。 藉由該0.25微米技術,可以製造4微米以微米之畫素胞, 且具有幾乎100%之填充係數。可使用該標準之微影技術於 矽晶圓上製造圖3Α標號118及圖3Β標號118所示之CM〇s 畫素電路。 互連t構亦優先使用標準之積體電路技術。當圖5所示之 私日日也製成以後,於矽晶圓上設置厚度大約〇·25微米之層以 形成上述結構。例如,可藉由濺鍍(spimering) 一大約〇·2微 米厚之至屬層,後接一黃光電阻和蝕刻製程來製造該電極 116。當利用蝕刻步驟將多餘之金屬除去後,該二氧化矽層 315係藉由CVD技術形成。藉由使用光阻和蝕刻技術,可以 產生過孔335所需之圓孔,然後使用濺鍍技術將該圓孔填充 傳導材料如鎢。然後’使用化學研磨(chemical mechanical polishing)技術對第一層315表面進行平坦化。然後,使用同 樣或者相同技術在第一層3丨5上形成另一互連層32〇。類似 地,第二層325形成於第二層上,每層大約為〇,5微米厚。 然後,藉由PECVD技術增加光電導層並藉由濺鍍法增加頂 部傳導層。 H:\HU\TYS\ii □案\87767\87767.DOC -22- 200405718 本發明之POAP感測器可包含具有各式各樣個別畫素胞之 畫素胞陣列。例如,畫素胞陣列之行、列都可以擴展或壓縮 以獲得預期之陣列尺寸和配置(例如:120x160、 256x256、 512x512、1024x1024、2048x2048 和 4096x4096 等)。然而, 本發明並不限於特定尺寸或幾何形狀,而任何陣列配置可應 用CMOS製程以達到並包含最大畫素密度者即可加以使用。 本發明進一步考慮修改個別個畫素胞之尺寸,以及修改畫素 胞陣列之尺寸和幾何形狀,以適應任何可能存在之成本限制。 四電晶體POAP感測器電路 圖5和圖6顯示使用四電晶體畫素之POAP影像感測器之 功能。特別地,每個畫素胞包含第一較佳實施例中描述之三 個電晶體:一重置電晶體250、一個源跟隨電晶體248和一 個列選擇電晶體260。在本實施例中,提供了一額外電晶體, 即一閘極偏壓電晶體360。電晶體360之閘極被一閘極電壓 Vcgb施以偏壓。該電晶體360設置於畫素電極116和電荷檢 測節點120之間。圖6中,光電二極體370之入射光照於光 電導層中產生正電荷和負電荷,其產生一有效電流Ipd。該 有效電流Ipd部分地將電容346放電,而不會顯著地改變畫 素電極116之電位。因此,閘極電晶體360在累積過程中有 效地將畫素電極330與電荷檢測節點CS隔離開(即電荷聚 集階段)。然而,任何畫素電路中流過之電流使電容246放 電至與圖3B電路相同的程度。 如圖3B所示之感測器,其使用傳統三電晶體畫素胞配置, 並不結合一閘極電晶體360,其將會感應與其各自接收光能 迚\^]\丁丫5\進□案\87767\87767.DOC -23 - 200405718 量相關之電位差。結果導致與具有受限三電晶體配置之畫素 胞之相鄰電極116可能感應大約100微伏特至1000微伏特之 電位差(假設供電電壓約3伏特)。該電位差之存在可能導 致不希望之畫素串擾,且可能增加畫素模糊。因此,如果沒 有提供該閘極電晶體,可以考慮採用其他技術,如增加層114 (圖3A所示)或層340(圖4所示)之電阻。如前述說明者, 這可藉由在該層增加碳來實現。 如圖5和圖6所示,電晶體250作為一重置電晶體,其閘 極連接至列重置RST(圖5),其源極連接至閘極電晶體360。 一源跟隨電晶體248包含一連接至電晶體Mcgb之閘極。選 擇電晶體260包含一連接至列選擇RSL (圖5)之閘極,以 及一連接至源跟隨電晶體248之源極之汲極。在電荷累積過 程中,入射光有效地打擊光電二極體370,並產生一從電容 246流向電晶體360之光電流。因此,該光電流將電容246 放電到與光電二極體上入射光強度相關之程度。然而,如上 所述,因為電晶體360上恒定之閘極電壓,電極116上之電 位並不會因為電容246之放電而顯著地改變。 如前所述,本發明既可製作一 PIN二極體亦可製作一 NIP 二極體結構。因此,任何具有一般技術者都會意識到使用圖 6所示一 PIN二極體結構之個別畫素胞電路能夠調整以容納 一 NIP二極體結構。該結構之例子如圖7所示。圖7例示一 電路圖,其可用於具有所示NIP二極體結構之個別畫素胞。 電路中所示之各種電子元件實質上與圖5所示之PIN二極體 結構相似,但其被調整以容納NIP二極體結構。例如,如圖 H:\HU\TYS\il □案\87767\87767.DOC - 24- 200405718 :示之:電二極體37。與!6中之相反。同時,重置電晶體 《甲1極接收-表示為聊之反向重置訊號,其藉由重置電 晶體250將電容246接地。藉此,在每次重置操作中,電容 之電壓下降至電晶體25〇之門檻電壓(大約〇.7伏特):在 圖7電路中,半透明電極層⑸上之電壓^維持—恒定 供應電壓,如3.3伏特。 本發明描述為具有-平面,或者實質上平整之光電導層(例 如η型層340)。然而,本發明亦可能有其他的配置,且在 本發明 < 考量中。例如,感測器可修改成包括非平面光電導 層以下將藉由圖解方式描述本發明使用非連續、具溝道: 具圖案之光電導層配置之其他實施例。 非連績光電導層 參考圖8,係本發明之ΡΟΑΡ感測器之一實施例之截面圖, 其以400為標示。感測器400在很多方面與感測器1〇〇和3〇〇 相似,其可包含一基板310和形成於基板310 (具有其書素 私路)上之多層互連結構352。另外,感測器4〇〇另包含傳 導層355、ρ型層350、i型層345和η型層340。此外,基 板3 10可包含畫素胞電路,其係用以減少或消除晝素串擾。 感測器300和感測器400最下方之光電導層(例如ρΐΝ二極 體中之η型層,或NIP二極體中之ρ型層)有一顯著區別, 其係關於與傳導過孔335電氣連接。特別地,感測器4〇〇顯 示為具有一非連續η型層340,其係由相鄰畫素電極335間 之溝道342形成。典型地,因為本徵層345之材料具有比η 型層340更高之電阻率,該溝道配置提供相鄰畫素間額外程 H:\HU\TYS^ □案\87767\87767.DOC -25- 200405718 ^又電氣隔離。然而,因為感測器4〇〇之非連續η型層34〇 可與前面描述之畫素胞電路-起使用,該感測器在不“降 低填充因數的情況下能夠將畫素串擾減至更低。圖8α顯示 了圖8實施例之變體。與使甩溝道相反,巾請者使用一凸起 、Si〇2壁至以產生一非連~之η型層。肖壁叠能夠像 其他内部金屬介電層一樣沉積和蝕刻。 溝道層 參考圖9,顯示本發日月POAP感測器之另-實施例之截面 圖’其標示為500。感測器5〇〇在很多方面與感測器構類 似。與在感測器彻中使用之溝道設計一樣,感測器5〇〇也 包含—相鄰畫素電極335間之溝道344。然而,該溝道3私 並不同於溝道342 (感測器400中)。感測器5〇〇中之 層340為連續,這與感測器4〇〇中使用之非連續n型層不同。 圖9所示之溝道配置典型地藉由增加η型層關聯之相鄰畫素 間之笔阻來提供畫素胞之間一定之隔離度。 圖案層 參考圖10 ’其顯示本發明之ΡΟΑΡ感測器之另一實施例之 截面圖,其標示為600。感測器600在很多方面與感測器5〇〇 類似,如包含一基板310和形成於基板31〇上之多層互連結 構352。與上述其他感測器類似,感測器6〇〇另包含傳導層 355、ρ型層350和i型層345。然而,相對於其他感測器, 該感測器600亦包含一圖案化之n型層34〇,但其與感測器 400和500所用之溝道設計不同。圖1〇所示圖案配置典型地 於相鄰畫素胞之間提供一定程度之電氣隔離。然而在某些應 H:\HU\TYS\進口案\87767\87767.DOC -26- 200405718 用中,單靠η型層340圖案化提供之電氣隔離可能不夠。如 果這樣,那該感測器600可配置有上述包含閘極偏壓電晶體 (如圖5中所示電晶體360 )之畫素胞電路,以獲得所期望 之畫素胞隔離度。 可選結構 本發明使用之個別畫素胞描述為一使用三電晶體或四電晶 體之畫素胞結構。然而,在本發明的考量中亦可選用其他替 可選結構。例如,應用於本發明之感測器之畫素胞電路可包 含二到六個電晶體,或者更多。以下藉由圖解方式說明可使 用其他畫素胞結構以維持畫素電極陣列上更高之電位均勻 性。 六電晶體畫素胞 圖11例示一六電晶體畫素胞之電路圖,其可用於具有PIN 二極體結構之個別畫素胞。圖Π所示電路在很多方面與圖6 所示相似。然而,與圖6設計相比,圖11中之電路包含二個 額外之電晶體(即Mpg和Mtf電晶體)。於圖11中,電晶 體Mcgb由一恒定之閘極電壓Vcgb產生偏壓,故畫素電極陣 列之每個電極116能夠維持於大致相同之電位。該重置電晶 體Mrst、源跟隨電晶體Msf、列選擇電晶體Mrsl以及閘極偏 壓電晶體Mcgb與上述之四電晶體畫素胞(圖6 )功能相似。 一第五電晶體Mpg 41 0,即光閘(photogate)電晶體,可能作 為一 MOS電容以儲存光子產生之電荷載子(例如電子)。一 第六電晶體Mtf 4 1 1,即該傳輸電晶體,可用以把電晶體Mpg 下儲存之電荷傳送至電荷檢測節點CS。相對於較少個數之電 H:\HU\TYS\進口案\87767\87767.DOC -27- 200405718 晶體配置(如四電晶體畫素胞),使用一六電晶體畫素胞之 —優點在於該7T晶體畫素胞結構允許進行一關聯之雙取樣 (double sampling),而顯著降低了畫素讀取雜訊。 為降低於CMOS感測器讀取電路中畫素點之間之固定圖案 雜訊,使用一種稱為雙取樣之通用技術。在該技術中,每個 畫素之重置參考電壓可被讀取,且被從該光訊號電壓中減 去,用以消除由於設備不匹配而引起之偏移電壓,其於每個 畫素點閒可能不同。然而每次重置操作常會引入一暫態雜 訊,一般稱為KTC雜訊。例如,在四電晶體畫素胞中,電荷 儲存節點(儲存光子產生之電荷載子之節點)和電荷檢測節 點(將電荷轉化為電壓輸出之節點)通常為同一節點。如此 一來,每個畫素胞之電荷檢測節點上之重置參考電壓只能在 光訊號電壓被讀取後才能讀取(否則儲存之光電荷將會被清 除)。因此’重置參考電壓與光訊號電壓無關。因此,與訊 號電壓關聯之KTC雜訊不能夠在四電晶體設計中得到消 除。這樣執行之雙取樣一般稱為非關聯雙取樣。雖然非關聯 雙取樣可能降低畫素點間之固定圖案雜訊,但一般不能降低 KTC雜訊,且在很多情況下其反而會增加KTC雜訊。另一方 面’就一六電晶體畫素胞來說,傳輸電晶體Mtf有效地將電 荷儲存節點(Mpg之閘極下之MOS電容)和電荷檢測節點 CS隔離。在電荷累積過程中,光閘極電晶體Mpg可能以深 耗(deep depletion)模式產生偏壓(對NMOS來說即Vpg=Vdd ) 並且斷開傳輸電晶體。在電荷累積結束時,一來自電晶體250 之重置脈衝可將電荷檢測節點CS重置。然後,先使用電晶 H.\HU\TYS\進口案 \87767\87767.DOC -28- 200405718 體248和260讀取電荷檢測節點上之重置參考電壓,接著可 接通傳輸電晶體411且Mpg 410之閘極電壓脈衝進入累積模 式(對NMOS來說,Vpg=0)以將儲存之光電荷轉儲到電荷 檢測節點,從而能夠讀取光訊號電壓。因為該重置參考電壓 包含與光訊號電壓中同樣之KTC雜訊,重置參考電壓從光訊 號電壓中外部減去即一般能夠完全消除KTC雜訊。該操作稱 為關聯雙取樣。由於額外之二個電晶體,該六晶體畫素胞配 置一般需要比四電晶體畫素胞更大之畫素胞面積。然而,即 使需要更大之畫素胞,該六電晶體畫素胞配置在需要降低畫 素間固定圖案雜訊且同時需要實質擺脫KTC雜訊之應用中 非常有用。 圖12例示一六電晶體畫素胞之電路圖,可用於具有NIP 二極體結構之個別畫素胞。該電路所示之各種電子元件與圖 11所示PIN二極體結構基本上相同,其變化係可容納一 NIP 二極體結構。例如,圖11顯示一能與一 PIN POAP感測器結 構一起使用之六電晶體畫素胞,該電容器246在累積過程中 藉由光電二極體370放電,且將電荷之降低測量為讀取電 壓。相反地,圖12顯示一能與一 NIP POAP感測器結構一起 使用之六電晶體晝素胞,該電容器246在累積過程中藉由光 電二極體370充電,且將電荷之增加測量為讀取電壓。另外, 圖12所示之六電晶體畫素胞包含反向PG、TF和RST訊號, 與圖11所示之PIN二極體結構使用之非反向PG、TF和RST 訊號相反。 四電晶體NIP結構 H:\HU\TYS\il □案\87767\87767.DOC -29- 200405718 圖13係本發明一實施例之一截面圖,其標示為7〇〇。感測 咨700包括之結構在很多方面與使用於例如感測器3〇〇(圖5 ) 者類似。特別地,感測器700包含一多層互連結構,該多層 互連結構包含於基板310上形成之層315、320和325。然而, 感測森700包含一 NIP二極體結構,與圖5中感測器3〇〇所 不PIN二極體配置相反。感測器7〇〇及其他任何感測器實施 例可能配置有另外之電晶體,以滿足上述之特殊設計需要。 阻障層和内層介電層(Interlayer Dielectric,ILD) 圖14係一感測器800之截面圖,該感測器8〇〇包含一位於 上述PIN光電二極體結構内之阻障層836以產生一 pBiN光 電一極體結構。該感測器亦包含一在互連結構下之特殊内層 介電層820。如圖所示,該感測器8〇〇包含一基板81〇 (包含 上述畫素電路)及一形成於該基板81〇(包含上述畫素電路) 上且位於互連結構815下之内層介電層82〇。該實施例亦包 含一製作於基板中之擴散區830,其為過孔825提供電氣接 觸位置。該擴散區係以P或N型摻雜材料向矽基板區域擴散 為佳’以使得該區域具有傳導性。p型層和丨型層間之額外 阻障層836提升了通過光電導電路之電流傳導性。其厚度以 小於50埃較佳,且可由與丨型層相似之材料組成,但具二、 比例碳。申請者之實驗顯示於阻障層中加入非常少量之p型 掺雜或可提升光電導電路之性能。額外之内層介電層82〇係 與層⑴類似之非常薄之絕緣層1,在較佳實施例中,在 製成孩電晶體之前係先應用一熱製程於矽晶圓(以產生非常 薄之高品質Si02層)。層815之_2材料係由CVD技術^ A A. i.t- H:\HIATYS^ □案\87767\87767.DOC -30- 200405718 行披覆較佳。提醒讀者,層820、815、825和83〇之生產係 跟隨業界標準積體電路製程。 圖1 5顯不了一可被本發明之任何感測器實施例應用之畫 素胞結構之更詳細視圖。特別地,圖15顯示具有—透明傳導 層845之個別畫素胞之上面部分。該透明傳導層⑷鄰近於 PBIN輻射吸收結構835形成,該pBiN輻射吸收結構8乃之 另一面緊鄰於該多層互連結構815之上表面。該多層互連結 構815顯示具有三個不同層86〇、865和87〇。該互連結構815 之每個層都可包含介電材料(如氧化矽、氮化矽或替他類似 材料)作為絕緣材料以隔絕各種層内金屬導體、金屬化區域 873、過孔840、825以及其他金屬電晶體之連接(未顯示於 圖中)。該過孔和金屬化區域提供至擴散區域83〇之電氣連 接’且其與光電導層接觸以作畫素電極用。 金屬墊 圖16 A係一使用畫素胞結構之感測器之截面示意圖,其以 標號900表示。相對於圖丨5中之感測器,該感測器9〇〇包含 與過孔840電氣連接之金屬墊876。該金屬墊876可結合過 孔840 —起用於提供輻射吸收結構835 (例如,pBIN配置中 之底邵η型層,或NIBP分層設計中之底部p型層)和擴散 區域830之間之更好電氣連接。該金屬墊8 76可由一合適之 傳導材料,如氮化鈦或鎢形成。 可選金屬墊設計 圖1 6Β係一使用畫素胞結構之感測器之截面示意圖,其以 標號950表示。該感測器950並不使用一互連結構815,也 H:\HU\TYS\il □案\8T767\87767.DOC •31 - 200405718 不使用一内層介電(ILD)層82〇,其係應用於本發明之其他 很多感測器設計中。在說明之PBIN配置中,藉由一擴散區 域830陣列和-金屬塾876陣列可定義—電荷收集畫素電極 陣列。 附加電路 圖PA顯示根據本發明之一些較佳實施例之畫素胞陣列 802和電路區域804間之相互關係。於該圖中,感測器_ 顯示具有-個別畫素之畫素胞陣列(ΝχΜ)。特別地,電路 區域804被隔離至該區域只佔有感測器8〇〇 一個單側之程 度。電路區域804包含用於支援和感測器8〇〇關聯之畫素胞 陣列I謂取和控制電路。例如,電路區域8〇4亦可製成包含 類比數位轉換器(ADC)、數位訊號處理器(Dsp)、時^ 和控制電路以及提供影像處理支援之電路。電路區域8〇4另 可包含RF電路以滿足無線影像器中之影像資料傳送和接收 要求。本發明《POAP感測器可包含一畫素胞陣列,其具有 大範圍之個別畫素胞。例如,(ΝχΜ)畫素胞陣列之列、行 都可以各自擴展或者壓縮以達到所預期之陣列尺寸和配置 (例如,120x160 256x256 、 512x512 、 1024x1024 、 2048x2048、4096x4096等)。然而,必須明白本發明並不局 限於㈣之陣列尺寸或者幾㈣狀,而任何陣列配置可應用 CMOS裝私以達到並包含最大畫素密度者即可加以使用。且 本1月可it步考量修改個別畫素胞之尺寸,以及修改畫素 胞陣列之尺寸和幾何形狀,以容納可能存在之任何鏡頭i本 限制。H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC 43! 200405718 It can also be made of indium tin oxide. However, other conductive materials can also be used to form the transparent conductive layer 355, including tin oxide, nitride, thin film and the like. A protective layer (not shown) can also be formed on the transparent conductive layer 355. Sensor manufacturing The sensor of the present invention can be manufactured using any conventional CMQS (or MQs) manufacturing technology. For example, the well-known 0.25 micron lithography technique can be used. With this 0.25 micron technology, it is possible to manufacture pixel cells with a size of 4 micrometers and micrometers, and have a fill factor of almost 100%. The standard lithography technology can be used to fabricate the CMos pixel circuit shown in Figure 3A, 118 and Figure 3B, 118 on a silicon wafer. Interconnects also prefer to use standard integrated circuit technology. When the private day shown in FIG. 5 is also made, a layer having a thickness of about 0.25 micrometers is formed on the silicon wafer to form the above structure. For example, the electrode 116 can be fabricated by spimering a sublayer with a thickness of about 0.2 micrometers, followed by a yellow photoresistor and an etching process. After the excess metal is removed by an etching step, the silicon dioxide layer 315 is formed by a CVD technique. By using photoresist and etching techniques, the circular holes required for the vias 335 can be created, and then the circular holes are filled with a conductive material such as tungsten using a sputtering technique. The surface of the first layer 315 is then planarized using a chemical mechanical polishing technique. Then, another interconnection layer 32 is formed on the first layer 3 5 using the same or the same technique. Similarly, second layers 325 are formed on the second layer, each layer being approximately 0.5 micron thick. Then, a photoconductive layer is added by a PECVD technique and a top conductive layer is added by a sputtering method. H: \ HU \ TYS \ ii □ Case \ 87767 \ 87767.DOC -22- 200405718 The POAP sensor of the present invention may include a pixel cell array with various individual pixel cells. For example, the rows and columns of the pixel cell array can be expanded or compressed to obtain the expected array size and configuration (for example: 120x160, 256x256, 512x512, 1024x1024, 2048x2048, 4096x4096, etc.). However, the present invention is not limited to a specific size or geometry, and any array configuration can be applied using a CMOS process to achieve and include the maximum pixel density. The invention further considers modifying the size of individual pixel cells, as well as modifying the size and geometry of the pixel cell array to accommodate any possible cost constraints. Four-transistor POAP sensor circuit Figures 5 and 6 show the function of a POAP image sensor using four-transistor pixels. Specifically, each pixel cell contains three transistors described in the first preferred embodiment: a reset transistor 250, a source follower transistor 248, and a column selection transistor 260. In this embodiment, an additional transistor is provided, that is, a gate bias transistor 360. The gate of transistor 360 is biased by a gate voltage Vcgb. The transistor 360 is provided between the pixel electrode 116 and the charge detection node 120. In FIG. 6, incident light from the photodiode 370 generates positive and negative charges in the photoconductive layer, which generates an effective current Ipd. This effective current Ipd partially discharges the capacitor 346 without significantly changing the potential of the pixel electrode 116. Therefore, the gate transistor 360 effectively isolates the pixel electrode 330 from the charge detection node CS during the accumulation process (ie, the charge accumulation stage). However, the current flowing in any pixel circuit discharges the capacitor 246 to the same extent as the circuit of FIG. 3B. As shown in FIG. 3B, the sensor uses a traditional three-transistor pixel cell configuration, and does not combine a gate transistor 360, which will sense and receive light energy from each of them. □ Case \ 87767 \ 87767.DOC -23-200405718 volume-dependent potential difference. As a result, the neighboring electrode 116 of the pixel cell with the restricted triode configuration may sense a potential difference of about 100 microvolts to 1000 microvolts (assuming a supply voltage of about 3 volts). The presence of this potential difference may cause unwanted pixel crosstalk and may increase pixel blur. Therefore, if the gate transistor is not provided, other techniques may be considered, such as increasing the resistance of layer 114 (shown in FIG. 3A) or layer 340 (shown in FIG. 4). As explained previously, this can be achieved by adding carbon to this layer. As shown in Figs. 5 and 6, the transistor 250 functions as a reset transistor, and its gate is connected to the column reset RST (Fig. 5), and its source is connected to the gate transistor 360. A source follower transistor 248 includes a gate connected to the transistor Mcgb. The selection transistor 260 includes a gate connected to the column selection RSL (FIG. 5), and a drain connected to the source of the source follower transistor 248. During the charge accumulation process, the incident light effectively strikes the photodiode 370 and generates a photocurrent flowing from the capacitor 246 to the transistor 360. Therefore, the photocurrent discharges the capacitor 246 to a degree related to the intensity of incident light on the photodiode. However, as mentioned above, because of the constant gate voltage across transistor 360, the potential on electrode 116 does not change significantly due to the discharge of capacitor 246. As mentioned above, the present invention can make both a PIN diode and a NIP diode structure. Therefore, anyone with ordinary skill will realize that individual pixel cell circuits using a PIN diode structure shown in FIG. 6 can be adjusted to accommodate a NIP diode structure. An example of this structure is shown in FIG. 7. Fig. 7 illustrates a circuit diagram which can be used for individual pixel cells having the NIP diode structure shown. The various electronic components shown in the circuit are substantially similar to the PIN diode structure shown in Fig. 5, but they are adjusted to accommodate the NIP diode structure. For example, as shown in Figure H: \ HU \ TYS \ il □ case \ 87767 \ 87767.DOC-24- 200405718: Shown: Electric Diode 37. versus! The opposite of 6. At the same time, the reset transistor "1-pole receiving-represented as a reverse reset signal of chat", which resets the capacitor 246 to ground by resetting the transistor 250. As a result, in each reset operation, the voltage of the capacitor drops to the threshold voltage of the transistor 25 (about 0.7 volts): In the circuit of FIG. 7, the voltage on the translucent electrode layer 电极 is maintained-a constant supply Voltage, such as 3.3 volts. The present invention is described as having a -planar, or substantially planar photoconductive layer (e.g., n-type layer 340). However, the present invention is also possible with other configurations, and is considered in the present invention < For example, the sensor may be modified to include a non-planar photoconductive layer. Other embodiments of the present invention using a discontinuous, channeled: patterned photoconductive layer configuration will be described graphically below. Non-continuous photoconductive layer Refer to FIG. 8, which is a cross-sectional view of an embodiment of a POA sensor of the present invention, which is denoted by 400. The sensor 400 is similar to the sensors 100 and 300 in many respects, and may include a substrate 310 and a multilayer interconnection structure 352 formed on the substrate 310 (having its private circuit). In addition, the sensor 400 further includes a conductive layer 355, a p-type layer 350, an i-type layer 345, and an n-type layer 340. In addition, the substrate 3 10 may include a pixel cell circuit for reducing or eliminating day-to-day crosstalk. There is a significant difference between the photoconductive layer at the bottom of the sensor 300 and the sensor 400 (such as the n-type layer in a ρΐN diode or the p-type layer in a NIP diode), which is related to the conduction via 335 Electrical connections. In particular, the sensor 400 is shown as having a discontinuous n-type layer 340 formed by a channel 342 between adjacent pixel electrodes 335. Typically, because the material of the intrinsic layer 345 has a higher resistivity than the n-type layer 340, this channel configuration provides an extra distance between adjacent pixels: H: \ HU \ TYS ^ □ case \ 87767 \ 87767.DOC- 25- 200405718 ^ and electrically isolated. However, because the non-continuous n-type layer 34 of the sensor 400 can be used in conjunction with the pixel cell circuit described above, the sensor can reduce pixel crosstalk to "without reducing the fill factor." Lower. Fig. 8α shows a variation of the embodiment of Fig. 8. In contrast to making the channel ditched, the person who requested the towel used a raised, SiO2 wall to create a non-connected η-type layer. Deposited and etched like other internal metal dielectric layers. Channel layer Referring to FIG. 9, a cross-sectional view of another embodiment of the present day and month POAP sensor is shown, which is labeled 500. The sensor 500 is The aspect is similar to the sensor structure. Like the channel design used in the sensor, the sensor 500 also includes a channel 344 between adjacent pixel electrodes 335. However, the channel 3 is private. It is different from the channel 342 (in the sensor 400). The layer 340 in the sensor 500 is continuous, which is different from the non-continuous n-type layer used in the sensor 400. As shown in FIG. 9 The channel configuration typically provides a certain degree of isolation between pixel cells by increasing the pen resistance between adjacent pixels associated with the n-type layer. Figure 10 'shows a cross-sectional view of another embodiment of the POAP sensor of the present invention, which is labeled 600. The sensor 600 is similar to the sensor 500 in many respects, such as including a substrate 310 and formed on The multilayer interconnect structure 352 on the substrate 31. Similar to the other sensors described above, the sensor 600 also includes a conductive layer 355, a p-type layer 350, and an i-type layer 345. However, compared to other sensors, The sensor 600 also includes a patterned n-type layer 34, but it is different from the channel design used by the sensors 400 and 500. The pattern configuration shown in FIG. 10 is typically between adjacent pixel cells. Provide a certain degree of electrical isolation. However, in some applications such as H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -26- 200405718, the electrical isolation provided by the n-type layer 340 patterning alone may not be sufficient. If In this way, the sensor 600 may be configured with the pixel cell circuit including the gate bias transistor (transistor 360 shown in FIG. 5) to obtain the desired pixel cell isolation. Optional structure The individual pixel cells used in the present invention are described as a pixel cell junction using a tri- or quad-transistor. However, other alternative structures can also be used in the consideration of the present invention. For example, the pixel cell circuit used in the sensor of the present invention may include two to six transistors, or more. The following is illustrated by illustration Method description: Other pixel cell structures can be used to maintain higher potential uniformity on the pixel electrode array. Hexamorphic pixel cell Figure 11 illustrates a circuit diagram of a six-transistor pixel cell, which can be used with PIN diode Individual pixel cells of the structure. The circuit shown in Figure II is similar in many respects to that shown in Figure 6. However, compared to the design in Figure 6, the circuit in Figure 11 contains two additional transistors (ie, Mpg and Mtf transistors). In FIG. 11, the transistor Mcgb is biased by a constant gate voltage Vcgb, so each electrode 116 of the pixel electrode array can be maintained at approximately the same potential. The reset transistor Mrst, the source follower transistor Msf, the column selection transistor Mrsl, and the gate bias piezoelectric crystal Mcgb have functions similar to those of the four-transistor pixel cell (Fig. 6). A fifth transistor Mpg 410, a photogate transistor, may be used as a MOS capacitor to store charge carriers (such as electrons) generated by photons. A sixth transistor Mtf 4 1 1, that is, the transmission transistor, can be used to transfer the charge stored in the transistor Mpg to the charge detection node CS. Relative to a small number of electricity H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -27- 200405718 crystal configuration (such as four-cell crystal cell), using one-six-cell pixel cell—advantages The pixel structure of the 7T crystal allows an associated double sampling, which significantly reduces the pixel reading noise. In order to reduce the fixed pattern noise between pixel points in the CMOS sensor reading circuit, a general technique called double sampling is used. In this technology, the reset reference voltage of each pixel can be read and subtracted from the optical signal voltage to eliminate the offset voltage caused by equipment mismatch. Idle may be different. However, each reset operation often introduces a transient noise, commonly referred to as KTC noise. For example, in a four-transistor pixel cell, the charge storage node (the node that stores the charge carriers generated by photons) and the charge detection node (the node that converts charge into a voltage output) are usually the same node. In this way, the reset reference voltage on the charge detection node of each pixel cell can only be read after the optical signal voltage is read (otherwise the stored photo charge will be cleared). Therefore, the 'reset reference voltage is independent of the optical signal voltage. Therefore, the KTC noise associated with the signal voltage cannot be eliminated in a four-transistor design. The double sampling performed in this way is generally called non-associative double sampling. Although uncorrelated double sampling may reduce fixed pattern noise between pixel points, generally it cannot reduce KTC noise, and in many cases it will increase KTC noise instead. On the other hand, in the case of a six-transistor pixel cell, the transmission transistor Mtf effectively isolates the charge storage node (the MOS capacitor under the gate of Mpg) from the charge detection node CS. During the charge accumulation process, the photogate transistor Mpg may generate a bias in the deep depletion mode (for NMOS, Vpg = Vdd) and disconnect the transmission transistor. At the end of charge accumulation, a reset pulse from transistor 250 resets the charge detection node CS. Then, first use the transistor H. \ HU \ TYS \ import case \ 87767 \ 87767.DOC -28- 200405718 to read the reset reference voltage on the charge detection node, and then turn on the transmission transistor 411 and The gate voltage pulse of Mpg 410 enters the accumulation mode (for NMOS, Vpg = 0) to dump the stored photocharge to the charge detection node, so that the optical signal voltage can be read. Because the reset reference voltage contains the same KTC noise as in the optical signal voltage, subtracting the reset reference voltage from the optical signal voltage externally can generally completely eliminate the KTC noise. This operation is called correlated double sampling. Due to the additional two transistors, the six-crystal pixel cell configuration generally requires a larger pixel cell area than the four-crystal pixel cell configuration. However, even if a larger pixel cell is required, the six-transistor pixel cell configuration is very useful in applications where it is necessary to reduce fixed pattern noise between pixels and at the same time to substantially get rid of KTC noise. FIG. 12 illustrates a circuit diagram of a six-cell pixel cell, which can be used for individual pixel cells having a NIP diode structure. The various electronic components shown in this circuit are basically the same as the PIN diode structure shown in FIG. 11, and the variation is to accommodate a NIP diode structure. For example, FIG. 11 shows a six-transistor pixel cell that can be used with a PIN POAP sensor structure. The capacitor 246 is discharged by the photodiode 370 during the accumulation process, and the decrease in charge is measured as a read Voltage. In contrast, FIG. 12 shows a six-transistor day cell that can be used with a NIP POAP sensor structure. The capacitor 246 is charged by the photodiode 370 during the accumulation process, and the increase in charge is measured as a read Take the voltage. In addition, the six-transistor pixel cell shown in FIG. 12 includes reverse PG, TF, and RST signals, which is opposite to the non-reverse PG, TF, and RST signals used in the PIN diode structure shown in FIG. 11. Four-transistor NIP structure H: \ HU \ TYS \ il Case \ 87767 \ 87767.DOC -29- 200405718 FIG. 13 is a cross-sectional view of an embodiment of the present invention, which is labeled 700. The sensor 700 includes a structure similar to that used in, for example, the sensor 300 (FIG. 5) in many respects. Specifically, the sensor 700 includes a multilayer interconnection structure including layers 315, 320, and 325 formed on a substrate 310. However, the sensing sensor 700 includes a NIP diode structure, as opposed to the PIN diode configuration of the sensor 300 in FIG. 5. Sensor 700 and any other sensor embodiments may be equipped with additional transistors to meet the special design needs described above. Barrier Layer and Interlayer Dielectric (ILD) FIG. 14 is a cross-sectional view of a sensor 800. The sensor 800 includes a barrier layer 836 in the PIN photodiode structure. A pBiN photodiode structure is generated. The sensor also includes a special inner dielectric layer 820 under the interconnect structure. As shown in the figure, the sensor 800 includes a substrate 810 (including the pixel circuit described above) and an inner interposer formed on the substrate 810 (including the pixel circuit described above) and located under the interconnect structure 815 Electrical layer 82. This embodiment also includes a diffusion region 830 formed in the substrate, which provides an electrical contact location for the via 825. The diffusion region is preferably diffused to the silicon substrate region with a P or N-type doped material to make the region conductive. An additional barrier layer 836 between the p-type layer and the 丨 -type layer improves the current conductivity through the photoconductive circuit. Its thickness is preferably less than 50 angstroms, and it may be composed of materials similar to the 丨 type layer, but with a proportion of carbon. Applicant's experiments show that adding a very small amount of p-type doping to the barrier layer may improve the performance of the photoconductive circuit. The additional inner dielectric layer 82 is a very thin insulating layer 1 similar to the layer 在. In a preferred embodiment, a thermal process is applied to the silicon wafer (to produce a very thin High quality Si02 layer). The material of layer 815-2 is formed by CVD technology ^ A A. i.t-H: \ HIATYS ^ □ case \ 87767 \ 87767.DOC -30- 200405718. The reader is reminded that the production systems of layers 820, 815, 825, and 830 follow the industry standard integrated circuit manufacturing process. Figure 15 shows a more detailed view of the pixel cell structure that can be applied to any sensor embodiment of the present invention. In particular, Fig. 15 shows the upper portion of individual pixel cells having a transparent conductive layer 845. The transparent conductive layer ⑷ is formed adjacent to the PBIN radiation absorbing structure 835, and the other side of the pBiN radiation absorbing structure 8 is close to the upper surface of the multilayer interconnection structure 815. The multilayer interconnect structure 815 is shown to have three different layers 860, 865, and 870. Each layer of the interconnect structure 815 may include a dielectric material (such as silicon oxide, silicon nitride, or other similar materials) as an insulating material to isolate metal conductors in various layers, metallized regions 873, vias 840, 825 And other metal transistor connections (not shown). This via and the metallized region provide electrical connection 'to the diffusion region 83 and it is in contact with the photoconductive layer for a pixel electrode. Metal pad FIG. 16A is a schematic cross-sectional view of a sensor using a pixel cell structure, which is denoted by reference numeral 900. Compared to the sensor in FIG. 5, the sensor 900 includes a metal pad 876 electrically connected to the via 840. The metal pad 876 may be combined with the via 840 to provide a radiation-absorbing structure 835 (eg, a bottom n-type layer in a pBIN configuration or a bottom p-type layer in a NIBP layered design) and a diffusion region 830 Good electrical connection. The metal pad 8 76 may be formed of a suitable conductive material such as titanium nitride or tungsten. Optional metal pad design Figure 16B is a schematic cross-sectional view of a sensor using a pixel cell structure, which is denoted by reference numeral 950. The sensor 950 does not use an interconnect structure 815, but also H: \ HU \ TYS \ il case \ 8T767 \ 87767.DOC • 31-200405718 does not use an inner layer dielectric (ILD) layer 82, which is It is used in many other sensor designs of the present invention. In the illustrated PBIN configuration, a charge-collecting pixel electrode array can be defined by a diffusion region 830 array and -metal 塾 876 array. Additional Circuit FIG. PA shows the relationship between the pixel cell array 802 and the circuit area 804 according to some preferred embodiments of the present invention. In the figure, the sensor_ displays a pixel cell array (N × M) with -individual pixels. In particular, the circuit area 804 is isolated to the extent that it only occupies the sensor 800 for one side. The circuit area 804 contains a pixel cell array I for fetching and controlling circuits for supporting 800 sensors. For example, the circuit area 804 can also be made up of an analog-to-digital converter (ADC), a digital signal processor (Dsp), a clock and control circuit, and a circuit that provides image processing support. The circuit area 804 may also include an RF circuit to meet the image data transmission and reception requirements in the wireless imager. The POAP sensor of the present invention may include an array of pixel cells having a large range of individual pixel cells. For example, the (N × M) pixel cell array columns and rows can be individually expanded or compressed to achieve the expected array size and configuration (for example, 120x160 256x256, 512x512, 1024x1024, 2048x2048, 4096x4096, etc.). However, it must be understood that the present invention is not limited to the size of the array or the shape of the array, and any array configuration can be applied using CMOS equipment to achieve and include the maximum pixel density. And in January, it can consider changing the size of individual pixel cells, as well as the size and geometry of the pixel cell array, to accommodate any lens restrictions that may exist.

H:\HU\TYS\iiP^\87767\87767.DOC 442 -32- 200405718 圖17B至C顯示了可使用於本發明P〇Ap感測器中之附加 配置。圖17B顯示於二個電路區域850之間佈置有一(NxM) 畫素胞陣列之感測器800,而圖17C顯示了具有一(NxM) 畫素胞陣列之感測器8 0 0,其由電路區域§ 〇 4圍繞整個書素 胞陣列製造。圖17A至C中所示畫素胞陣列和電路區域之安 排提供了能用於各種不同應用之感測器。例如,感測器模組 可藉由縮放使用圖示之一個或多個感測器配置之複數個個別 感測器製造。可以瞭解的是,圖17A至C中所示之電路區域 配置可由此說明之任何感測器設計所使用。 NIBP POAP感測器 圖1 8 A係本發明之一可選實施例之感測器之截面圖,其係 由標號1000表示。感測器1〇〇〇包含在許多方面和可能使用 之感測器相似之結構,例如,感測器100 (圖14),除了本 例,輻射吸收層885為一 NIBP結構而非一 PBIN結構。圖 18B和圖18C係使用具有金屬墊之畫素胞結構之感測器之截 面示意圖。除了輻射吸收層為PBIN外,該感測器在許多方 面和圖16A和圖16B所示之感測器和畫素胞陣列相似。 其他感測器結構 本發明其他的較佳實施例如圖19至29所示。圖19係本發明 利用非連續光電導層設計之POAP感測器之一可選實施例之 截面圖。圖20係本發明利用溝道式光電導層設計之poAp感測 另一可選實施例之截面圖。圖21係本發明利用圖案式光 電導層設計之POAP感測器之另一可選實施例之截面圖。圖22 係本發明之PBIN感測器之一實施例之截面圖,以及一些可用H: \ HU \ TYS \ iiP ^ \ 87767 \ 87767.DOC 442 -32- 200405718 Figures 17B to C show additional configurations that can be used in the POAp sensor of the present invention. FIG. 17B shows a sensor 800 having a (NxM) pixel cell array arranged between two circuit regions 850, and FIG. 17C shows a sensor 800 having a (NxM) pixel cell array. The circuit area § 〇4 is fabricated around the entire leptin cell array. The arrangement of pixel cell arrays and circuit areas shown in Figures 17A to C provides sensors that can be used in a variety of different applications. For example, a sensor module may be manufactured by scaling a plurality of individual sensors using one or more sensor configurations shown in the figure. It will be appreciated that the circuit area configuration shown in Figs. 17A to C can be used in any sensor design described herein. NIBP POAP Sensor FIG. 18A is a cross-sectional view of a sensor according to an alternative embodiment of the present invention, which is denoted by reference numeral 1000. The sensor 1000 includes a structure similar to a sensor that may be used in many aspects, for example, the sensor 100 (FIG. 14). Except for this example, the radiation absorbing layer 885 has a NIBP structure instead of a PBIN structure. . 18B and 18C are schematic cross-sectional views of a sensor using a pixel cell structure with a metal pad. This sensor is similar in many respects to the sensor and pixel cell arrays shown in Figures 16A and 16B, except that the radiation absorbing layer is PBIN. Other Sensor Structures Other preferred embodiments of the present invention are shown in Figs. FIG. 19 is a cross-sectional view of an alternative embodiment of a POAP sensor using a discontinuous photoconductive layer design according to the present invention. FIG. 20 is a cross-sectional view of another alternative embodiment of poAp sensing using a trench-type photoconductive layer design according to the present invention. FIG. 21 is a cross-sectional view of another alternative embodiment of a POAP sensor using a patterned photoconductive layer design according to the present invention. FIG. 22 is a cross-sectional view of an embodiment of the PBIN sensor of the present invention, and some available

H:\HU\TYS\igp ^\87767\87767.DOC -33- 200405718 於支援PBIN二極體結構之相關畫素胞電路。圖23係本發明之 一 NIBP感測器之截面圖,以及一些可用於支援NIBP二極體結 構之相關畫素胞電路。圖24例示一六電晶體結構之電路圖, 其可用於具有PBIN二極體結構之個別畫素胞。圖25例示一六 電晶體結構之電路圖,其可用於具有NIBP二極體結構之個別 畫素胞。圖26例示一電路圖,其可用於具有PBIN二極體結構 之個別畫素胞,而不需使用閘極偏壓電晶體。圖27例示一電 路圖,其可用於具有NIBP二極體結構之個別畫素胞,而不需 使用閘極偏壓電晶體。圖28例示一五電晶體結構之電路圖, 其可用於具有PBIN二極體結構之個別畫素胞。圖29例示一五 電晶體結構之電路圖,其可用於具有NIBP二極體結構之個別 畫素胞。 POAP感測器製造 圖30例示一用於製造POAP感測器之操作流程圖。本發明 實施例之POAP感測器之形成請參考圖30所示之操作,以及 圖3 1A至F所示之感測器製造階段進行說明。在圖30中, 第一操作605係提供一具有電氣傳導擴散區830 (圖31A) 陣列之基板8 1 0。在該較佳實施例中,畫素電路單元包含放 置於基板上並連接至擴散區830之至少二個電晶體。接著, 於操作610中,形成一内層介電層820 ( ILD),其係具有由 接觸通道(contact) 825所形成之陣列。該接觸通道825與擴 散區830 (圖31B)所形成之陣列中之一擴散區830相連。 於操作615中,一多層互連結構815形成於ILD層820 (圖 31C)之上。多層互連結構815内之傳導過孔840可由一合 H:\HU\TYS\iinil\87767\87767.DOC -34- 200405718 適之電導材料形成,如鎢、銅、鋁、或者其他使用於眾所周 知之積體電路製造技術中以生成過孔之類似材料。一般之傳 導過孔840由CVD製程形成,然亦可使用其他技術(如濺 鍍)。連接畫素電路元素之金屬導體亦可能包含於該多層互 連結構之中。於可選之操作中,一金屬墊876可圖案化^作 而相鄰於互連結構815。這樣過孔840和光電導層835 (圖 3 1D )之間之電氣連接將得到改善。於下一操作中,各單獨 之PMN層連續地沉積於互連結構815上,以形成該輻射吸 收結構835 (圖31E)。或者,在需要一 NIBp二極體結構之 情況下(如圖18A所示之感測器1〇〇〇),各個單獨之NiBp 光電二極體層連續地沉積於互連結構815上以形成輻射吸收 結構。一般而言,輻射吸收結構835中各層之沈積係利用 PECVD製私το成。再者,可瞭解的是,根據一個實施例,因 為並不需要將一個或者多個層加以圖案化(如PBin二極體 結構中之底部N層),輻射吸收結構835能夠於一連續沉積 過程中形成。一透明傳導層845可能沉積於輻射吸收結構835 (圖31F)之頂層上。該透明傳導層845為輻射吸收結構835 之頂層(如PBIN二極體結構之p型層,或者NIBp二極體結 構之η型層)提供接地或者至一電壓源之電氣連接。該透明 傳導層8 4 5可成藉由反應錢鍍法沉積。透明傳導層$ 4 $可藉 由蒸鍍形成。然而,如果透明傳導層845係由氮化鈦形成, 此時一般使用CVD或濺鍍技術。 應用、其他特點和變異 此處所顯示者均被認為係本發明之較佳實施例,然,顯然 H:\HU\TYS\ 進口案\87767\87767.DOC -35- 200405718 熟知本項技藝者可以進行各種修改和變化,而不偏離 之範圍和精髓。 Λ 應用 一使用該ΡΟΑΡ感測器結構之具有適當配置之感測器單元 能夠使用於各種應用中,包括照相機、機器視覺系統、車輛 導航系統、視訊電話、電腦輸入設備、監視系統、自動對焦 系統、星系追蹤、動作偵測系統、影像穩定系統、掃描器及 其他類似設備。 使用孩種設備能夠受益之人包括:法律施行、醫療、火罄 邵門、緊急服務和搜救行動,以及軍事和情報團體。另外之 應用包括··非破壞性檢測、預防性維護操作、商務安全應用 以及汽車業,例如,為司機提供低亮度視覺增強設備。 摻雜 本發明之感測器之各層之摻雜可藉由眾所周知之半導體製 程加以實施。該製程可用於形成具有摻雜梯度之層,例如, 摻雜濃度將隨層深度之變化,或者具有突然變化之摻雜濃 度。該摻雜梯度或者摻雜剖面可為某一特殊感測器設計進行 最佳化。雖然已說明複數個用於製造輻射吸收結構835之合 適材料之例子,然本發明並不限於此。 於較佳實施例中,申請者使用電漿增強型化學汽相沈積 (Plasma Enhanced Chemical Vapor Deposition,PECVD)技 術以產生NIP光電二極體層,該技術在業界係眾所周知者。 我們首先成長一 p型層,該P型層與畫素墊接觸,其薄膜使 用《P型雜質係侧。為增加電阻率,我們亦可於p型層換雜 •36- h:\hu\tys\進口案\87767\87767d〇c 200405718 、/刀子硼摻雜濃度係丨020·1 〇21原子/立方I米之數 量級。而碳原子/分子係1G21,22原子/立方董米之數量 級。:徵:最好僅含有矽原子和氳原子,氫原子之濃度最好 2 10 _1022原子/立方釐米之數量級。當然,在薄膜中亦可 把有一些非預期之雜質。與IT〇接觸之n型層應僅含有^型 雜質和氫原子。於本例中,該n型雜f為濃度1()2。_1()21原子 /上方贊米數畺級之磷。於p型層和n型層中,氫原子之目 軚;辰度係10 Lio22原子/立方釐米之數量級。 保護層 透明傳導層845 (圖31F所示)可由銦錫氧化物(IT0)、 氧化錫、氮化鈦、薄矽化物或其他類似材料製成。一保護層 (沒有顯π於圖中)可於透明傳導層845上形成。該保護層 可提供機械保護、電氣隔離,以及提供抗反射特性。 缺陷校正電路 缺陷杈正電路可加以使用。該電路之目的係消除視訊流 (video Stream)中之「單個畫素缺陷」或「小集組缺陷」,而 不需事先確定缺陷位置。該電路之工作原理係將感測器編程 為檢查某個畫素以及其最鄰近之畫素,且將該畫素點之值與 為區域之標準值比較。如果該畫素點之值比經驗判定之標準 門檻值高或低,則該畫素點將被認為「有缺陷」,而該畫素 點之值將由標準值取代。該技術可消除缺陷點,然而如資訊 為僅一個畫素之寬度(雖然此狀況非常不可能發生於正常的 照相機應用),則真實之資訊亦會被消除。該電路可潛在地 實質改進感測器之良率(yiel句,因現在和可預見之將來之製 H:\HU\TYS\進口案\87767\87767.DOC -37- 200405718 程 < 良率損失係r單畫素缺陷」引起。 微晶碎 於較佳實施例中,製造輻射吸收層(即PIN、NIP、ΡΒΙΝ 或者NIBP層)之基本材料係微晶碎(& )和微晶硬(鍺) 而不是非晶碎。結果將頻譜回應寬度從非晶矽之35〇奈米至 750奈米提升至微晶矽之3〇〇奈米至1〇〇〇奈米和微晶矽(鍺) 之300奈米至1200奈米。採用微晶矽或微晶矽(鍺)之另一 優點係提升至少1〇倍之反應時間,這樣能於KHz幀框速率 之感測器中取得領先。 高畫質電視(HDTV)感測器 針對一 2百萬畫素之高畫質電視之感測器,申請者整合二 獨特之電路,一係「列類比數位轉換器(c〇lunin ADC)」, 另一個係「雙差異取樣(deita-double sampling,DDS)」電路。 在一較佳感測器中,每列(該較佳傳感器具有丨92〇行(c〇lumn) X 1280列(row))係提供一類比數位轉換器。該列類比數位轉 換器之用途係緩解類比數位轉換器之取樣速率。一 2 ·丨百萬 畫素之陣列以3 0赫茲、1 〇位元執行即表示單個類比數位轉 換器需每秒執行60M之1〇位元樣本。這會使類比數位轉換 器處於最尖端之設計和製造技術。藉由使用「列類比數位轉 換器」,申請者能以列數目降低取樣速率,本例中為192〇。 因此申請者可緩解類比數位轉換器之取樣速率要求,且在其 他電路上使用相同之CMOS技術。而DDS電路連續轉換二 汛號,一個係真正之訊號,另一係每個畫素之參考輸出。申 請者之電路將該二訊號轉換成數位值並用該二訊號之差值代H: \ HU \ TYS \ igp ^ \ 87767 \ 87767.DOC -33- 200405718 Supports related pixel cell circuits of PBIN diode structure. FIG. 23 is a cross-sectional view of an NIBP sensor according to the present invention, and some related pixel cell circuits that can be used to support the NIBP diode structure. FIG. 24 illustrates a circuit diagram of a six-transistor structure, which can be used for individual pixel cells having a PBIN diode structure. FIG. 25 illustrates a circuit diagram of a six-transistor structure, which can be used for individual pixel cells having a NIBP diode structure. FIG. 26 illustrates a circuit diagram that can be used for individual pixel cells having a PBIN diode structure without using a gate bias transistor. Fig. 27 illustrates a circuit diagram which can be used for individual pixel cells having a NIBP diode structure without using a gate bias transistor. FIG. 28 illustrates a circuit diagram of a five-transistor structure, which can be used for individual pixel cells having a PBIN diode structure. FIG. 29 illustrates a circuit diagram of a five-transistor structure, which can be used for individual pixel cells having a NIBP diode structure. POAP Sensor Manufacturing FIG. 30 illustrates an operation flowchart for manufacturing a POAP sensor. For the formation of the POAP sensor according to the embodiment of the present invention, please refer to the operation shown in FIG. 30 and the manufacturing stages of the sensor shown in FIGS. 3A to F. In FIG. 30, the first operation 605 is to provide a substrate 8 1 0 having an array of electrically conductive diffusion regions 830 (FIG. 31A). In the preferred embodiment, the pixel circuit unit includes at least two transistors placed on the substrate and connected to the diffusion region 830. Next, in operation 610, an inner dielectric layer 820 (ILD) is formed, which has an array formed by contact channels 825. The contact channel 825 is connected to one of the diffusion regions 830 in an array formed by the diffusion regions 830 (Fig. 31B). In operation 615, a multilayer interconnection structure 815 is formed on the ILD layer 820 (FIG. 31C). The conductive vias 840 in the multilayer interconnect structure 815 can be formed from a combination of H: \ HU \ TYS \ iinil \ 87767 \ 87767.DOC -34- 200405718 suitable conductive materials, such as tungsten, copper, aluminum, or other well-known Similar materials in integrated circuit manufacturing technology to generate vias. Generally, the conductive vias 840 are formed by a CVD process, but other techniques (such as sputtering) can also be used. Metal conductors that connect pixel circuit elements may also be included in the multilayer interconnect structure. In an optional operation, a metal pad 876 may be patterned adjacent to the interconnect structure 815. In this way, the electrical connection between the via 840 and the photoconductive layer 835 (FIG. 31D) will be improved. In the next operation, individual PMN layers are successively deposited on the interconnect structure 815 to form the radiation absorbing structure 835 (FIG. 31E). Alternatively, in the case where an NIBp diode structure is required (sensor 1000 as shown in FIG. 18A), each individual NiBp photodiode layer is continuously deposited on the interconnect structure 815 to form radiation absorption structure. In general, the layers of the radiation absorbing structure 835 are deposited using PECVD. Furthermore, it can be understood that, according to one embodiment, because one or more layers need not be patterned (such as the bottom N layer in a PBin diode structure), the radiation absorbing structure 835 can be used in a continuous deposition process. Middle formation. A transparent conductive layer 845 may be deposited on the top layer of the radiation absorbing structure 835 (FIG. 31F). The transparent conductive layer 845 is a top layer of the radiation absorbing structure 835 (such as a p-type layer of a PBIN diode structure or an n-type layer of a NIBp diode structure) to provide ground or an electrical connection to a voltage source. The transparent conductive layer 8 4 5 can be deposited by a reactive plating method. The transparent conductive layer can be formed by vapor deposition. However, if the transparent conductive layer 845 is formed of titanium nitride, a CVD or sputtering technique is generally used at this time. Applications, other features, and variations shown here are considered to be the preferred embodiments of the present invention. However, it is clear that H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -35- 200405718 Make various modifications and changes without departing from the scope and essence. Λ Application-A sensor unit with proper configuration using the POA sensor structure can be used in various applications, including cameras, machine vision systems, car navigation systems, video phones, computer input devices, surveillance systems, autofocus systems , Galaxy tracking, motion detection systems, image stabilization systems, scanners and other similar devices. People who can benefit from the use of children's equipment include: law enforcement, medical treatment, burned out door, emergency services and search and rescue operations, and military and intelligence groups. Other applications include non-destructive inspection, preventive maintenance operations, business safety applications, and the automotive industry, for example, providing drivers with low-brightness visual enhancement devices. Doping The doping of the layers of the sensor of the present invention can be performed by well-known semiconductor processes. This process can be used to form a layer with a doping gradient. For example, the doping concentration will change with the depth of the layer, or the doping concentration may change suddenly. The doping gradient or doping profile can be optimized for a particular sensor design. Although a number of examples of suitable materials for manufacturing the radiation absorbing structure 835 have been described, the present invention is not limited thereto. In a preferred embodiment, the applicant uses Plasma Enhanced Chemical Vapor Deposition (PECVD) technology to generate a NIP photodiode layer, which is well known in the industry. We first grow a p-type layer. This p-type layer is in contact with the pixel pad. The film uses the "P-type impurity system side". In order to increase the resistivity, we can also change the impurity in the p-type layer On the order of one meter. Carbon atoms / molecules are on the order of 1G21, 22 atoms / cubic meter. : Sign: It is best to contain only silicon and thorium atoms, and the concentration of hydrogen atoms is preferably in the order of 2 10 _1022 atoms / cm 3. Of course, some undesired impurities may be contained in the film. The n-type layer in contact with IT0 should contain only ^ -type impurities and hydrogen atoms. In this example, the n-type impurity f has a concentration of 1 () 2. _1 () 21 Atoms / Zambeam top grade Phosphorus. In the p-type layer and the n-type layer, the order of hydrogen atoms is 軚; the degree of order is 10 Lio22 atoms / cm3. Protective layer The transparent conductive layer 845 (shown in FIG. 31F) may be made of indium tin oxide (IT0), tin oxide, titanium nitride, thin silicide, or other similar materials. A protective layer (not shown in the figure) may be formed on the transparent conductive layer 845. This protective layer provides mechanical protection, electrical isolation, and anti-reflective properties. Defect Correction Circuit Defect correction circuit can be used. The purpose of this circuit is to eliminate the "single pixel defect" or "small set defect" in the video stream without determining the defect location in advance. The working principle of this circuit is to program the sensor to check a pixel and its nearest pixels, and compare the value of the pixel point with the standard value of the area. If the value of the pixel point is higher or lower than the standard threshold value determined by experience, the pixel point will be considered "defective" and the value of the pixel point will be replaced by the standard value. This technology can eliminate defects. However, if the information is only one pixel wide (although this situation is very unlikely to occur in normal camera applications), the real information will also be eliminated. This circuit can potentially substantially improve the yield of the sensor (yiel sentence, because of the present and foreseeable future system H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -37- 200405718 Cheng & Yield The loss is caused by the "single pixel defect". In the preferred embodiment, the microcrystals are broken. The basic materials used to make the radiation absorbing layer (ie, PIN, NIP, PBIN or NIBP layer) are microcrystals (microamps) and microcrystals. (Germanium) instead of amorphous fragments. As a result, the spectral response width was increased from 35nm to 750nm in amorphous silicon to 300nm to 1000nm in microcrystalline silicon and microcrystalline silicon ( Germanium) 300nm to 1200nm. Another advantage of using microcrystalline silicon or microcrystalline silicon (germanium) is to improve the response time by at least 10 times, which can lead the sensor in the KHz frame rate. . High-definition television (HDTV) sensor For a high-definition television sensor of 2 million pixels, the applicant integrated two unique circuits, a series of "column ADC" ", The other is a" deita-double sampling (DDS) "circuit. In a better sensor, each row (the The preferred sensor has 920 rows (column X 1280 rows) to provide an analog-to-digital converter. The purpose of the column analog-to-digital converter is to ease the sampling rate of the analog-to-digital converter.-2 · 丨Arrays of megapixels are executed at 30 Hz and 10 bits, which means that a single analog digital converter needs to execute 60M 10-bit samples per second. This puts the analog digital converter at the most cutting-edge design and manufacturing technology. By using a "column-to-analog digital converter", the applicant can reduce the sampling rate by the number of columns, which is 1920 in this example. Therefore, the applicant can ease the sampling rate requirements of the analog-to-digital converter and use the same on other circuits. CMOS technology. The DDS circuit continuously converts the two signals, one is the real signal and the other is the reference output of each pixel. The applicant's circuit converts the two signals into digital values and uses the difference between the two signals to replace

H:\HU\TYS\ 進口案\87767\87767.DOC -38- 200405718 表真正之視訊訊號。該電路係為了將畫素中之電荷儲存電容 和歹】邊比數位轉換器輸入之間之任何偏移量(由於電路或製 程 < 不均勻性)減小至最小。該DDS電路能提升均句性並緩 解對製造技術之均勻性要求。 小相機之應用 本發明之實施例提供了一種潛在之相機,具有非常小的尺 寸、非常低的製造成本和非常高的品質。一般而言,於尺寸、 品質和成本之間會有一些牵制,然隨著在幾美元成本範圍内 之大I生產、毫米大小之尺寸和以百萬畫素或十萬畫素者衡 量之影像品質,本發明可應用之範圍非常廣泛。除手機外, 其他潛在之應用列舉如下: 一 類比攝錄相機 - 數位攝錄相機 一 安全照相機 一 數位照相機 一 個人電腦照相機 - 玩具 - 内視鏡 ~ 軍用無人飛機、炸彈和飛彈 - 體育器材 - 高畫質電視感測器 因相機可做得比人之眼球小,本發明之一實施例係做成人 眼形狀之照相機。因其成本很低,該眼球相機可併入到許多 玩具和新產品當中。可附加一電纜作為光學神經以從一監視H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -38- 200405718 represents the real video signal. This circuit is designed to minimize any offset (due to the circuit or process < non-uniformity) between the charge storage capacitance in the pixel and the input of the edge-to-digital converter. This DDS circuit can improve uniformity and alleviate the requirement for uniformity of manufacturing technology. Applications of small cameras Embodiments of the present invention provide a potential camera with a very small size, very low manufacturing cost, and very high quality. Generally speaking, there will be some restraint between size, quality and cost, but with the large I production in the cost range of a few dollars, the size of the millimeter size and the image measured in millions of pixels or 100,000 pixels Quality, the scope of application of the present invention is very wide. In addition to mobile phones, other potential applications are listed below: An analog video camera-digital video camera-security camera-digital camera-a personal computer camera-toys-endoscopes ~ military drones, bombs and missiles-sports equipment-high definition Since the quality television sensor can be made smaller than a human eyeball, one embodiment of the present invention is a camera shaped as a human eye. Due to its low cost, the eyeball camera can be incorporated into many toys and new products. A cable can be attached as an optical nerve to monitor from a

H:\HU\TYS\進口案\87767\87767.DOC -39- 200405718 器(如個人電腦監視器)獲取影像資料。該眼球相機可併入 玩具娃娃或人體模型中,且甚至裝上轉動元件以及-反饋電 路因此涊眼球旎夠於其視覺範圍内移動。如果不用電纜, 影像資料亦可藉由手機技術進行無線傳輸。該小尺寸之照相 機允朴-手機式傳送器—起裝在職業足球運動負之頭盘 中這樣1:視迷們可以像運動貞_樣觀看職業運動員們之 動作。事實上’具有—傳送器之相機甚至可裝在足球上,這 樣月匕夠才疋供㉟非常有意思之動作才見圖。i述僅係該微小、 廉價、高品質相機之成千上萬種潛在應用之例子。該小型相 機可在沒有鏡頭情況下用以監控光強度輪廓,以及輸出其強 度和輪廓之變化,這一點在光通信應用中至關緊要。因為這 需要檢測光束輪廓以獲得最高之傳輸效率。當用其他光傳感 材料代替非晶矽時,該相機能用於將光傳感(lightsensing)擴 展至可見光外。例如,人們可使用微晶矽(鍺)將光傳感擴 展至近紅外光範圍,其相機非常適合夜視。我們在較佳實施 例中使用這樣一種封裝,感測器係安裝於一晶片載器上面, 並按合於一鏡頭外殼。人們亦可改變裝配順序,首先將該感 測器焊接至一感測器底板上,然後將具有鏡頭之鏡頭支架覆 盖該感測器並機械式地固定至PCB板上以生產照相機。對熟 悉此項技術者來說,其僅係本發明之一自然改變。 本發明之其他應用 除上述說明之應用外,一使用POAP感測器結構並合理配 置之感測器單元亦可使用於許多應用當中,如機器視覺系 統、車輛導航系統、視訊電話、電腦輸入設備、監視系統、 H:\HU\TYS\進□案\87767\87767.DOC • 40- 200405718 焦系統、星系追縱器、動作偵測系統、影像穩定系統、 田=及其他類㈣備。受益於使用該設備者包括法律施 :二療、消防部門、緊急服務和搜救行動,以及軍事和情 ^另外《應用包括非破壞性檢測、預防性維護操作、 強::全應用’以及汽車業,例如為司機提供低亮度視覺增 其他變化 該透明層可由非常薄之導體組成之網柵代替。圖2所示之 :取電路和照相機電路14〇ι148可部分或者整個位於 CMOS畫素陣列下,以製造非常微小之照相機。該c刪電 路可邵分或者完全由M0S電路所取代12所示之—些電路 L40至148可位於一塊或者多塊晶片上,而非位於具有感測 益陣列(晶片上。例如,如同時將電路144和146分開為製 作於一早獨之晶片上每去一 g、 、日卩π上次者一早獨 < 處理器内將具有成本優 勢畫素之數目可從0.3兆畫素點增加或減少而幾乎可以 受限制。 因此,本發明之保護範圍應由以下之申請專利範圍及其法 律上之等同所決定。 五、圖式簡要說明 圖1ΑΗΒ顯示裝配有照相機之手機,且該照相機使用本發 明之CMOS感測器陣列; Λ 圖1C顯示该照相機之部分詳細資料; 圖2顯示使用本發明原理之CMOS積體電路之部分詳細資 料; 、、只H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -39- 200405718 (such as a personal computer monitor) to obtain image data. The eyeball camera can be incorporated into a doll or a mannequin, and even equipped with a rotating element and a feedback circuit so that the eyeball can move within its visual range. If no cable is used, the image data can also be transmitted wirelessly using cell phone technology. This small-sized camera allows Parker-Mobile Phone Transmitter to be mounted in the negative headboard of professional football. 1: Fans can watch the movements of professional athletes like sports. In fact, the camera with a transmitter can even be mounted on a football, so the moon dagger is enough to provide a very interesting action. These are just examples of the thousands of potential applications for this tiny, cheap, high-quality camera. This small camera can be used to monitor the light intensity profile without a lens, and to output changes in its intensity and profile, which is crucial in optical communication applications. Because this requires detecting the beam profile to obtain the highest transmission efficiency. When other light sensing materials are used instead of amorphous silicon, the camera can be used to extend lightsensing beyond visible light. For example, one can use microcrystalline silicon (germanium) to extend light sensing to the near-infrared light range, and its cameras are ideal for night vision. We use such a package in a preferred embodiment. The sensor is mounted on a chip carrier and is snapped onto a lens housing. One can also change the assembly sequence by first soldering the sensor to a sensor base, then covering the sensor with a lens holder with a lens and mechanically fixing it to a PCB to produce a camera. To those skilled in the art, it is only a natural modification of the present invention. Other applications of the present invention In addition to the applications described above, a sensor unit using a POAP sensor structure and a reasonable configuration can also be used in many applications, such as machine vision systems, vehicle navigation systems, video phones, computer input devices , Surveillance system, H: \ HU \ TYS \ Entry case \ 87767 \ 87767.DOC • 40- 200405718 focus system, galaxy tracker, motion detection system, image stabilization system, field = and other types of equipment. Benefits from the use of this device include law enforcement: secondary treatment, fire services, emergency services and search and rescue operations, as well as military and intelligence ^ In addition, "applications include non-destructive testing, preventive maintenance operations, strong For example, to provide drivers with low brightness vision and other changes. The transparent layer can be replaced by a grid of very thin conductors. As shown in Figure 2: The fetch circuit and the camera circuit 148m148 can be partially or entirely located under the CMOS pixel array to make a very tiny camera. The c-deleted circuit can be divided or replaced entirely by M0S circuits as shown in 12. Some of the circuits L40 to 148 can be located on one or more wafers, rather than on a chip with a sensing array (eg. Circuits 144 and 146 are divided into chips manufactured on an early-morning wafer. For each g, 卩, the last one, the early-morning alone < the number of pixels with cost advantages in the processor can be increased or decreased from 0.3 megapixels. It can be almost limited. Therefore, the scope of protection of the present invention should be determined by the scope of the following patent applications and their legal equivalents. 5. Brief description of the drawings Figure 1AΗB shows a mobile phone equipped with a camera, and the camera uses the invention CMOS sensor array; Λ Figure 1C shows some details of the camera; Figure 2 shows some details of a CMOS integrated circuit using the principles of the present invention;

H:\HU\TYS\進口案 \87767\87767.DOC -41 · 200405718 圖3 A係一具有使用本發明原理之一感測器陣列内之五畫 素之畫素胞結構之局部截面示意圖; 圖3B顯示一單畫素之CMOS畫素電路; 圖3 C顯示一彩色滤光片之網柵圖案; 圖4係一具有光電二極體陣列之感測器之截面圖,該光電二 極體陣列由CMOS電路組件之主動式畫素陣列上之光電導層 組成; 圖5係本發明之POAP感測器之第一實施例之一截面圖,以 及一些相關之畫素胞電路,其可用以支援一個PIN光電二極 體結構; 圖6例示一電路圖,其可用於具有PIN光電二極體結構之個 別畫素胞; 圖7例示一電路圖,其可用於具有NIP二極體結構之個別畫 素胞; 圖8與圖8A係本發明之P0AP感測器之一可選實施例之戴面 圖,其使用非連續光電導層設計; 圖9係本發明之POAP感測器之另一可選實施例之截面圖, 其使用溝道式光電導層設計; 圖1 0係本發明之POAP感測器之另一可選實施例之截面 圖,其使用圖案型光電導層設計; 圖11例示一六電晶體結構之電路圖,其可用於具有PIN二極 體結構之個別畫素胞; 圖12例示一六電晶體結構之電路圖,其可用於具有NIP二極 體結構之個別畫素胞; H:\HU\TYS\進口案\87767\87767.DOC -42- 200405718 圖13係本發明之POAP感測器之一可選實施例之截面圖,以 及一些可用於支援NIP二極體結構之相關畫素胞電路; 圖14係一具有阻障層之感測器之第一實施例之截面示意 圖; 圖15例示畫素胞結構之局部截面圖,其可用於本發明之任 何P0AP感測器之實施例中; 圖16A係一使用一金屬墊之PBIN感測器之截面圖; 圖16B係一PBIN感測器之一可選實施例之截面示意圖; 圖17A係本發明之P0AP感測器之俯視圖,顯示一實施例之 畫素胞陣列與單感測器電路區域間之相互關係; 圖17B係本發明之P0AP感測器之俯視圖,顯示另一實施例 之畫素胞陣列與多感測器電路區域間之相互關係; 圖17C係本發明之P0AP感測器之俯視圖,顯示另一實施例 之畫素胞陣列與一四面感測器電路區域間之相互關係; 圖18A係本發明之NIBP感測器之一實施例之截面圖; 圖18B係一使用金屬焊墊之NIBP感測器之一可選實施例之 截面圖; 圖18C係一 NIBP感測器之另一可選實施例之截面圖; 圖19係本發明利用非連續光電導層設計之P0AP感測器之 一可選實施例之截面圖; 圖20係本發明利用溝道式光電導層設計之P0AP感測器之 另一可選實施例之截面圖; 圖21係本發明利用圖案式光電導層設計之P0AP感測器之 另一可選實施例之截面圖; H:\HU\TYS\進口案\87767\87767.DOC -43 - 200405718 圖22係本發明之PBIN感測器之一實施例之截面圖,以及一 些可用於支援PBIN二極體結構之相關畫素胞電路; 圖23係本發明之一NIBP感測器之截面圖,以及一些可用於 支援NIBP二極體結構之相關畫素胞電路; 圖24例示一六電晶體結構之電路圖,其可用於具有PBIN二 極體結構之個別畫素胞; 圖25例示一六電晶體結構之電路圖,其可用於具有NIBP二 極體結構之個別畫素胞; 圖26例示一電路圖,其可用於具有PBIN二極體結構之個別 畫素胞,而不需使用閘極偏壓電晶體; 圖27例示一電路圖,其可用於具有NIBP二極體結構之個別 畫素胞,而不需使用閘極偏壓電晶體; 圖28例示一五電晶體結構之電路圖,其可用於具有PBIN二 極體結構之個別畫素胞; 圖29例示一五電晶體結構之電路圖,其可用於具有NIBP二 極體結構之個別畫素胞; 圖3 0例示一操作流程圖,其可用於製造本發明所示之一實 施例之POAP感測器;及 圖31A至31F係顯示製造步騾之局部截面圖,可用於製造本 發明所示之一實施例之POAP感測器。 六、元件符號說明 2A、2B手機 4鏡頭 8 照相機護蓋 4B、6照相機 1〇連接器 H:\HU\TYS\進口案\87767\87767.DOC - 44 - 200405718 800 、 900 、 950 、 1000 100、300、400、500、600、700、 感測器畫素陣列 102、802畫素陣列 1 0 4、8 0 4讀取和定時/控制電路 106濾光層 110 、 112 、 114 、 340 、 118畫素電路 12鏡頭座 122光感測結構 14影像晶片 142影像處理電路 146通信協定電路 16電路板 250 、 248 、 260 、 360 、 410 256 COL (輸出) 310、810感測器基板 108電極層 、345 、 860 、 865 、 870 層 116電極 120電荷收集節點 335過孔 140資料分析電路 144決定和控制電路 148輸入和輸出介面電路 246電容 、411電晶體 262節點 315、320、325、337、352、815 互連結構 336金屬線 355透明傳導層 605 、 610、 615、 620、 804、850電路區域 825、840 過孔 835輻射吸收結構 845傳導層 876金屬墊 342、344 溝道 3 70光電二極體 625、630 操作 820中介電層 830擴散區 836阻障層 8 7 5金屬化區域 885輻射吸收層H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -41 · 200405718 Figure 3 A is a partial cross-sectional view of a pixel cell structure with five pixels in a sensor array using one of the principles of the present invention; Figure 3B shows a single pixel CMOS pixel circuit; Figure 3C shows a grid pattern of a color filter; Figure 4 is a cross-sectional view of a sensor with a photodiode array, the photodiode The array consists of a photoconductive layer on an active pixel array of CMOS circuit components; FIG. 5 is a cross-sectional view of a first embodiment of the POAP sensor of the present invention, and some related pixel cell circuits, which can be used for Supports a PIN photodiode structure; Figure 6 illustrates a circuit diagram that can be used for individual pixel cells with a PIN photodiode structure; Figure 7 illustrates a circuit diagram that can be used for individual pixels with a NIP diode structure Figure 8 and Figure 8A are wearing views of an optional embodiment of the POAP sensor of the present invention, which uses a discontinuous photoconductive layer design; Figure 9 is another alternative of the POAP sensor of the present invention A cross-sectional view of the embodiment, which uses a trench-type photoconductive layer design; FIG. 1 0 is a cross-sectional view of another alternative embodiment of the POAP sensor of the present invention, which uses a patterned photoconductive layer design; FIG. 11 illustrates a circuit diagram of a six-transistor structure, which can be used for a PIN diode structure Individual pixel cells; Figure 12 illustrates a circuit diagram of a six-transistor structure, which can be used for individual pixel cells with a NIP diode structure; H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -42- 200405718 FIG. 13 is a cross-sectional view of an alternative embodiment of the POAP sensor of the present invention, and some related pixel cell circuits that can be used to support the NIP diode structure; FIG. 14 is a diagram of a sensor with a barrier layer A schematic cross-sectional view of the first embodiment; FIG. 15 illustrates a partial cross-sectional view of a pixel cell structure, which can be used in any embodiment of the POAP sensor of the present invention; FIG. 16A is a PBIN sensor using a metal pad 16B is a schematic cross-sectional view of an alternative embodiment of a PBIN sensor; FIG. 17A is a top view of a POAP sensor of the present invention, showing a pixel cell array and a single sensor circuit area of an embodiment The relationship between them; FIG. 17B is the POAP sense of the present invention The top view of the device shows the correlation between the pixel cell array and the multi-sensor circuit area of another embodiment; FIG. 17C is a top view of the POAP sensor of the present invention, showing the pixel cell array and The relationship between the four-sided sensor circuit areas; Figure 18A is a cross-sectional view of an embodiment of the NIBP sensor of the present invention; Figure 18B is an optional embodiment of an NIBP sensor using a metal pad 18C is a cross-sectional view of another alternative embodiment of a NIBP sensor; FIG. 19 is a cross-sectional view of an alternative embodiment of a POAP sensor using a discontinuous photoconductive layer design according to the present invention; FIG. 20 is a cross-sectional view of another alternative embodiment of a POAP sensor using a trench-type photoconductive layer design according to the present invention; FIG. 21 is another alternative embodiment of a POAP sensor using a patterned photoconductive layer design according to the present invention; Sectional view of the selected embodiment; H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC -43-200405718 Figure 22 is a sectional view of one embodiment of the PBIN sensor of the present invention, and some can be used to support PBIN Related pixel cell circuit of diode structure; Figure 23 is a NI of the present invention A cross-sectional view of the BP sensor and some related pixel cell circuits that can be used to support the NIBP diode structure. Figure 24 illustrates a circuit diagram of a six-transistor structure that can be used for individual pixel cells with a PBIN diode structure. ; Figure 25 illustrates a circuit diagram of a six-transistor structure, which can be used for individual pixel cells with a NIBP diode structure; Figure 26 illustrates a circuit diagram, which can be used for individual pixel cells with a PBIN diode structure, without A gate bias transistor is required; Figure 27 illustrates a circuit diagram that can be used for individual pixel cells with a NIBP diode structure without the need for a gate bias transistor; Figure 28 illustrates a five-transistor structure Circuit diagram, which can be used for individual pixel cells with PBIN diode structure; Figure 29 illustrates a circuit diagram of a five-electrode structure, which can be used for individual pixel cells with NIBP diode structure; Figure 30 illustrates an operation flow Figures, which can be used to manufacture a POAP sensor according to one embodiment of the present invention; and Figures 31A to 31F are partial cross-sectional views showing manufacturing steps, which can be used to manufacture a POAP sensor according to one embodiment of the present invention. Device . Six, component symbol description 2A, 2B mobile phone 4 lens 8 camera cover 4B, 6 camera 10 connector H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC-44-200405718 800, 900, 950, 1000 100 , 300, 400, 500, 600, 700, sensor pixel array 102, 802 pixel array 1 0 4, 8 0 4 reading and timing / control circuit 106 filter layer 110, 112, 114, 340, 118 Pixel circuit 12 lens holder 122 light sensing structure 14 image chip 142 image processing circuit 146 communication protocol circuit 16 circuit board 250, 248, 260, 360, 410 256 COL (output) 310, 810 sensor substrate 108 electrode layer, 345, 860, 865, 870 layers 116 electrodes 120 charge collection nodes 335 vias 140 data analysis circuits 144 decision and control circuits 148 input and output interface circuits 246 capacitors, 411 transistors 262 nodes 315, 320, 325, 337, 352, 815 interconnect structure 336 metal line 355 transparent conductive layer 605, 610, 615, 620, 804, 850 circuit area 825, 840 via 835 radiation absorption structure 845 conductive layer 876 metal pad 342, 344 channel 3 70 photodiode 625, 630 operation 820 Barrier layer 836 a dielectric layer 830 diffusion region 875 region 885 of the radiation absorbing metal layer

H:\HU\T YS\進口案\87767\87767.DOCH: \ HU \ T YS \ import case \ 87767 \ 87767.DOC

Claims (1)

200405718 拾、申請專利範圍: 1· 一種主動式金屬氧化物半導體(MOS)或互補式金屬氧化 物半導體(CMOS)感測器,包含: A) —結晶基板; B) —電荷產生光電導層,包含至少二電荷產生材料 層,用於將光轉換為電荷; C) 複數個MOS或CMOS畫素電路,其定義複數個畫素, 且製造於該電荷產生光電導層之下的結晶基板中,該各畫 素電路定義一畫素且包含:一電荷收集電極、一電容及至 少二電晶體,該畫素電路用以收集與讀出該電荷產生材料 層產生之電荷; D) —表面電極,其為薄透明層或網柵型式,且位於該 電荷產生材料層之上;以及 E) —電源,用於提供一跨越該電荷產生光電導層之壓 降。 2·如申請專利範圍第丨項所述之感測器,其中該複數個M〇s 或CMOS畫素電路係複數個CMOS畫素電路。 3. 如申請專利範圍第丨項之感測器,其中一金屬墊係作為各 畫素之電荷收集電極之用。 4. 如申請專利範圍第丨項所述之感測器,其中該複數個畫素 係至少十萬畫素。 5·如申請專利範圍第丨項所述之感測器,其進一步包含與該 主動式感測器相同之結晶基板内或之上之附加M〇S或 CMOS電路,用以轉換為可由該畫素電路讀出之影像電 荷。 H:\HU\TYS\進口案\87767\87767.DOC λ r Γ· 200405718 6·如申請專利範圍第 ㈣《感心,其中該電荷產生材 枓層包έ—ρ型摻雜層、一本徵層及— η型層。 7.如中請專利範圍第6項所述之感測器,其中該表面電極由 銦錫氧化物(ΙΤΟ)組成。 8.,申請專利範圍第6項所述之感測器,其中該η型層係相鄰 亥表面笔極,而該Ρ型層係相鄰該電荷收集電極。 9·如申請專利範圍第6項所述之感測器,其進—步包含一介 於該ρ型層與本徵層間之阻障層。200405718 Patent application scope: 1. An active metal-oxide-semiconductor (MOS) or complementary metal-oxide-semiconductor (CMOS) sensor, including: A) — a crystalline substrate; B) — a charge-generating photoconductive layer, Including at least two charge generating material layers for converting light into charges; C) a plurality of MOS or CMOS pixel circuits, which define a plurality of pixels, and are manufactured in a crystalline substrate under the charge generating photoconductive layer, Each pixel circuit defines a pixel and includes: a charge collecting electrode, a capacitor, and at least two transistors, the pixel circuit is used to collect and read out the charges generated by the charge generating material layer; D) a surface electrode, It is a thin transparent layer or grid type and is located on the charge generating material layer; and E) a power source for providing a voltage drop across the charge generating photoconductive layer. 2. The sensor according to item 丨 of the patent application, wherein the plurality of Mos or CMOS pixel circuits are a plurality of CMOS pixel circuits. 3. For the sensor in the scope of patent application, a metal pad is used as a charge collection electrode for each pixel. 4. The sensor according to item 丨 of the patent application scope, wherein the plurality of pixels are at least 100,000 pixels. 5. The sensor as described in item 丨 of the patent application scope, further comprising an additional MOS or CMOS circuit in or on the same crystalline substrate as the active sensor for conversion to The image charge read by the element circuit. H: \ HU \ TYS \ import case \ 87767 \ 87767.DOC λ r Γ · 200405718 6 · For example, the scope of the patent application is "Sense, where the charge generating material includes a p-type doped layer, an intrinsic Layer and — n-type layer. 7. The sensor according to item 6 of the patent claim, wherein the surface electrode is composed of indium tin oxide (ITO). 8. The sensor according to item 6 of the patent application, wherein the n-type layer is adjacent to the surface pen and the P-type layer is adjacent to the charge collecting electrode. 9. The sensor according to item 6 of the patent application scope, further comprising a barrier layer between the p-type layer and the intrinsic layer. 沒如中請專利範圍第8項所述之感測器,其中該?型層包含碳 原子或分子。 申請專利範圍第!項所述之感測器,其中該複數個畫素 电路尤各畫素電路包含一閘極偏壓電晶體,用以將該電荷 收集電極自該電容分離。 12.如申請專利範圍第6項所述之感測器,其中該複數個畫素 電路之各畫素電路包含一閘極偏壓電晶體,其將該電荷收 集電極自該電容分離。 13 ·如申睛專利範圍第12項所述之感測器,其中該閘極偏塵電 0 晶體保持一恆定電壓。 14.如申請專利範圍第1項所述之感測器,其進一步包含一互 連結構’形成於該結晶基板之上及該電荷產生光電導層之 下。 1 5.如申請專利範圍第14項所述之感測器,其中該互連結構包 含至少二子層,各子層包含導電過孔,用於電氣連接該複 數個晝素電路與該電荷產生光電導層。 16·如申請專利範圍第1項所述之感測器,其亦包含製造於該 H:\HU\TYS\^L':J ^\87767\87767.DOC 200405718 結晶基板上之資料分析電路。 17.=申請專·圍第16項所述之感職,其亦包含製造於該 〜晶基板上之影像處理電路。 18.2請專利範圍第17項所述之感測器,其亦包含製造於該 、、、吉晶基板上之決定與控制電路。 19.=申請專利範圍第18項所述之感測器,其亦包含製造於該 結晶基板上之通訊電路。 2〇·如申請專利範圍第旧所述之感測器,其中該感測器係一 照相機<整體部分,該照相機藉由一纜線連接於一手機。 21·如中請專利範圍第!項所述之感測器,其中該表面電極係 由一銦錫氧化物層組成。 22·如申請專利範圍第丨項所述之感測器,其中該至少二電荷 產生層主要包含氫化非晶矽層。 23·如申請專利範圍第”頁所述之感測器,其中該該至少二電 荷產生材料層係由微晶矽或微晶矽(鍺)組成。 24·如申請專利範圍第1項所述之感測器,其另包含一保護 層。 2 5 ·如申请專利範圍第1項所述之感測器,其另包含用於定位 缺陷畫素,及為該缺陷畫素替換正常資料之電路。 26.如申請專利範圍第丨項所述之感測器,其中該感測器位於 一手機内之照相機之一整體部分。 27·如申請專利範圍第1項所述之感測器,其另包含一位於該 表面電極頂部之一彩色濾光片之陣列。 28·如申請專利範圍第27項所述之感測器,其中該彩色遽光片 係由紅、綠及藍濾光片組成,該濾光片依二綠色、一紅色 H:\HU\TYS\進□案\87767\87767.DOC 200405718 及—藍色之四件式套組配置。 9·如申請專利範圍第丨項所述之感測器,其中該感測器係一 製作成一人眼球形狀之照相機之一部分。 〇_如申請專利範圍第1 8項所述之感測器,其中該決定與控制 笔路包含一處理器,其編程有一用於分析畫素資料之一控 制次算法,且基於該資料控制自該感測器之訊號輸出。 如申μ專利圍弟3 0項所述之感測器,其中該處理器藉由 羽整畫素照明時間控制訊號輸出。 如申μ專利範圍弟3 0項所述之感測器,其中該處理器藉由 調整訊號放大以控制訊號輸出。 如申叫專利|li圍弟1項所述之感測器,其中該感測器係— 結合至一設備之照相機之一部分,該設備選自下列群組: -類比攝錄相機; -數位攝錄相機; -安全照相機; -數位相機; -個人電腦照相機; -玩具; -内視鏡; -軍事無人飛機、炸彈、飛彈; -運動器材;及 -高畫質電視感測器。 34· —具有主動式MOS或CMOS感測器陣列之昭知说 "、、祁機,利用電 荷產生光而產生電子影像,該照相機包含: A)—結晶基板; H:\HU\TYS\^t □案\87767\87767.DOC -4- 200405718 B) —電荷產生光電導層,包含至少二電荷產生材料 層,用於將光轉換為電荷; C) 複數個MOS或CMOS畫素電路,製造於該電荷產生光 電導層之下的結晶基板中,該各畫素電路包含:一電荷收 集電極、一電容及至少三電晶體;該畫素電路用以收集與 讀出該電荷產生層產生之電荷; D) —表面電極,其為薄透明層或網柵型式,且位於該 電何產生層之上, E) —電源,用於提供一跨越該電荷產生光導電層之反相 偏壓; F) 附加M0S或CMOS電路,於該相同結晶基板内和/或 上,具有用以將該電荷轉換為影像之主動式感測器陣列; G) 附加MOS或CMOS電路,於該相同結晶狀基板内和/ 或上,具有用以進行時序和訊號同步化之主動式感測器陣 列;以及 H) 聚焦光學元件,用以將電子電洞產生之光聚焦至該 主動式感測器陣列。 H:\HU\TYS\il □案\87767\87767.DOCNot the sensor described in item 8 of the patent scope, where? The mold layer contains carbon atoms or molecules. The scope of patent application! The sensor according to the above item, wherein the plurality of pixel circuits and each pixel circuit includes a gate bias transistor for separating the charge collecting electrode from the capacitor. 12. The sensor according to item 6 of the patent application, wherein each pixel circuit of the plurality of pixel circuits includes a gate bias transistor which separates the charge collecting electrode from the capacitor. 13. The sensor as described in item 12 of the Shen-Jin patent scope, wherein the gate-biased electric crystal maintains a constant voltage. 14. The sensor according to item 1 of the patent application scope, further comprising an interconnect structure 'formed on the crystalline substrate and under the charge generating photoconductive layer. 1 5. The sensor according to item 14 of the scope of patent application, wherein the interconnect structure includes at least two sub-layers, and each sub-layer includes conductive vias for electrically connecting the plurality of day-to-day circuits with the charge to generate photoelectricity导 层。 Guide layer. 16. The sensor described in item 1 of the scope of the patent application, which also includes a data analysis circuit manufactured on the H: \ HU \ TYS \ ^ L ': J ^ \ 87767 \ 87767.DOC 200405718 crystal substrate. 17. = Apply for the job description described in item 16, which also includes an image processing circuit manufactured on the substrate. 18.2 The sensor described in item 17 of the patent scope also includes a decision and control circuit manufactured on the substrate. 19. = The sensor described in item 18 of the scope of patent application, which also includes a communication circuit manufactured on the crystal substrate. 20. The sensor as described above in the scope of the patent application, wherein the sensor is an integral part of a camera, and the camera is connected to a mobile phone by a cable. 21 · If the patent scope, please! The sensor according to the item, wherein the surface electrode is composed of an indium tin oxide layer. 22. The sensor according to item 丨 of the patent application scope, wherein the at least two charge generating layers mainly include a hydrogenated amorphous silicon layer. 23. The sensor as described in page "Scope of the patent application", wherein the at least two charge generating material layers are composed of microcrystalline silicon or microcrystalline silicon (germanium). 24. As described in item 1 of the patent application scope The sensor includes a protective layer. 2 5 The sensor according to item 1 of the patent application scope further includes a circuit for locating a defective pixel and replacing normal data for the defective pixel. 26. The sensor according to item 1 of the scope of patent application, wherein the sensor is located in an integral part of a camera in a mobile phone. 27. The sensor according to item 1 of the scope of patent application, which An array of color filters located on top of the surface electrode is also included. 28. The sensor according to item 27 of the scope of patent application, wherein the color phosphor is composed of red, green and blue filters The filter is configured according to two green and one red H: \ HU \ TYS \ into the case \ 87767 \ 87767.DOC 200405718 and the blue four-piece set. 9 · As the first patent application scope The sensor described above, wherein the sensor is a camera made in the shape of a human eyeball. 〇_ The sensor as described in item 18 of the scope of patent application, wherein the decision and control pen circuit includes a processor, which is programmed with a control sub-algorithm for analyzing pixel data, and is based on the data. Controls the signal output from the sensor. The sensor as described in item 30 of the patent application of the μ μ patent, wherein the processor controls the signal output by the illumination time of the whole pixel. The sensor described in the above item, wherein the processor controls the signal output by adjusting the signal amplification. For example, the sensor described in item 1 of the patent application, wherein the sensor is-combined with a device As part of the camera, the device is selected from the following groups:-analog camcorders;-digital camcorders;-security cameras;-digital cameras;-personal computer cameras;-toys;-endoscopes;-military drones , Bombs, missiles;-sports equipment; and-high-definition television sensors. 34 ·-Known with active MOS or CMOS sensor array ", Qi machine, use charge to generate light to generate electrons Image The machine contains: A) —crystalline substrate; H: \ HU \ TYS \ ^ t □ case \ 87767 \ 87767.DOC -4- 200405718 B) — charge generation photoconductive layer, including at least two charge generation material layers for Light is converted into charge; C) A plurality of MOS or CMOS pixel circuits are manufactured in a crystalline substrate under the charge generating photoconductive layer. Each pixel circuit includes: a charge collection electrode, a capacitor, and at least three transistors. The pixel circuit is used to collect and read out the charges generated by the charge generating layer; D) — surface electrode, which is a thin transparent layer or grid type, and is located on the electric generating layer, E) — power supply, For providing an inverse bias across the charge to generate a photoconductive layer; F) additional MOS or CMOS circuits with active sensing in and / or on the same crystalline substrate to convert the charge into an image G) additional MOS or CMOS circuits with active sensor arrays for timing and signal synchronization in and / or on the same crystalline substrate; and H) focusing optics for The light generated by the electron hole is focused to the Movable sensor array. H: \ HU \ TYS \ il □ case \ 87767 \ 87767.DOC
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Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/229,955 US7411233B2 (en) 2002-08-27 2002-08-27 Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
US10/229,956 US6798033B2 (en) 2002-08-27 2002-08-27 Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
US10/229,953 US20040041930A1 (en) 2002-08-27 2002-08-27 Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
US10/229,954 US6791130B2 (en) 2002-08-27 2002-08-27 Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
US10/371,618 US6730900B2 (en) 2002-02-05 2003-02-22 Camera with MOS or CMOS sensor array

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TWI381741B (en) * 2007-03-19 2013-01-01 Sony Corp Imaging block and imaging apparatus
TWI811285B (en) * 2018-01-25 2023-08-11 中國大陸商深圳幀觀德芯科技有限公司 Packaging of Radiation Detectors

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TWI395473B (en) * 2009-10-09 2013-05-01 Altek Corp Automatic focusing system and method under low-illumination

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Publication number Priority date Publication date Assignee Title
TWI381741B (en) * 2007-03-19 2013-01-01 Sony Corp Imaging block and imaging apparatus
TWI811285B (en) * 2018-01-25 2023-08-11 中國大陸商深圳幀觀德芯科技有限公司 Packaging of Radiation Detectors

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