(i) (i)200307866 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 技術領域 本發明係關於一資料處理裝置.、其具有一處理器、一記 憶體組件及一映射裝置，用以將一虛擬記憶體位元址映射 到該記憶體組件内一實體記憶體位元址上，其中映射之執 行由該處理器提示。 先前技術 以虛擬及實體記憶體運轉的資料處理裝置之不同形式在 先前技術中眾所周知。以虛擬記憶體運轉允許處理器（隨 後稱為虛擬記憶體）内記憶體邏輯位元址與物理位元址間 大量任意結合。在本文中，例如，每一記憶體段皆有其特 定屬性，例如寫入保護，由使用者或雜項約束決定。此情 形中，邏輯位元址需映射至實體記憶體位址上。此映射利 用一儲存於映射裝置之表格來完成。 使用這樣的映射操作，會發生大量錯誤，使繼續程式或 映射操作無法進行或不合需要。此時，一報告返回處理器 以便它可以對錯誤發生作出反應。此情形中，通常傳送一 錯誤碼以便能夠限制該錯誤。因而就能夠辨別，例如，該 錯誤之問題是否有關浮動小數點操作、記憶體保護達反或 嘗試執行一特權指令。儘管此一組態允許限制錯誤，但不 能確定錯誤的實際原因。 發明内容 因此本發明之一目的係指定一資料處理裝置，其在錯誤 發生時，允許以一簡單方式精確確定該錯誤。 (2)200307866 徵 時 在 環 這 中 因 指 下 元 體 於 作 實 址 邏 但除錯误碼外儲存 •接受映射之虛擬位 虛擬記憶 舞濟續賓 此目的籍由簡介中提及之一型資料處理裝置實現，其特 係所提供之構件在映射裝置於映射過秘中出現一錯誤 ，可在處理咨可存取的一記憶體内儲存錯誤约束。 因而，本發明之資料處理裝置不僅提供_錯誤碼，而且 隨後的錯誤處理過禮中，能檢查因錯誤導致操作失敗的 境0 本發明上下文中使用的術語「錯誤」係關於異常情況， 時程式流程由於一錯誤狀態（在處理_指令時已出現）而 斷。因此在該已執行之指令與該異常情況或錯誤間有一 果關係。這些係「同步異常情況」，亦稱為陷阱。 正確確定錯誤原目提供一方法用^冑改變對原先失敗 令之執行的約束，如此便能繼續該程式。 儲存約束之範圍取決於各自的使用 列錯誤約束至少其中一項會很有利 址、存取類型、許可權狀態、請求者之識別 目前狀態或實體記憶體目前狀態。 在一晶片卡中使用本發明之資料處理装置尤其有利。 晶片卡的典型使用範圍，需要執行大量有關安全的 。同時能夠建立一錯誤發生之準確原因 底下將參考示範具體實施例，更詳細地解釋：發明。 施方式 一處理器1(隨後稱為CPU) ’處理一虚後記憶體4内之 。…開始藉由一映射裝置3轉換虛^己憶體*内之 輯位-址。另外，該映射裝置連接一實體記憶體5。 (3)200307866(i) (i) 200307866 (ii) Description of the invention (The description of the invention shall state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings.) Technical Field The present invention relates to a data processing device. It has a processor, a memory component and a mapping device for mapping a virtual memory bit address to a physical memory bit address in the memory component, and the execution of the mapping is prompted by the processor. Prior art Different forms of data processing devices operating in virtual and physical memory are well known in the prior art. Operating in virtual memory allows a large number of arbitrary combinations of logical and physical bit addresses of memory within a processor (hereinafter referred to as virtual memory). In this article, for example, each memory segment has its specific attributes, such as write protection, which is determined by the user or miscellaneous constraints. In this case, the logical bit address needs to be mapped to the physical memory address. This mapping is done using a table stored in the mapping device. With such a mapping operation, a large number of errors can occur, making the continued program or mapping operation impossible or undesirable. At this point, a report is returned to the processor so that it can respond to an error. In this case, an error code is usually transmitted so that the error can be limited. It is thus possible to discern, for example, whether the problem of the error is related to a floating-point operation, memory protection or an attempt to execute a privileged instruction. Although this configuration allows limiting errors, it is not possible to determine the actual cause of the error. SUMMARY OF THE INVENTION It is therefore an object of the present invention to designate a data processing device that allows an error to be accurately determined in a simple manner when an error occurs. (2) 200307866 The time in circulation is due to the fact that the lower body is used for real-site logic but stored except for error codes. • Accept the mapped virtual bits. Virtual memory. This is a type of model mentioned in the introduction. The data processing device is implemented. An error occurred in the mapping device during the mapping process provided by the component provided by the system. The error constraint can be stored in a memory accessible to the processing device. Therefore, the data processing device of the present invention not only provides an _error code, but can also check the situation where the operation fails due to an error during subsequent error handling. 0 The term "error" used in the context of the present invention is about abnormal conditions, and the program flow Broken due to an error condition (which occurred while processing the _ instruction). There is therefore a consequence between the executed instruction and the abnormal condition or error. These are "synchronous exceptions," also known as traps. Correctly identifying the wrong source provides a way to use ^ 胄 to change the constraints on the execution of the original failure order so that the program can continue. The scope of the storage constraints depends on their use. At least one of the error constraints can be very useful. Address, access type, permission status, requester's identification Current status or current status of physical memory. It is particularly advantageous to use the data processing device of the present invention in a chip card. The typical use of chip cards requires a lot of security-related implementations. At the same time, the exact cause of the error can be established. The following will explain in more detail: the invention with reference to the exemplary embodiment. Embodiment A processor 1 (hereinafter referred to as a CPU) 'processes a post-virtual memory 4. ... begins to convert the edit bit-address in the virtual memory by a mapping device 3. In addition, the mapping device is connected to a physical memory 5. (3) 200307866
一點上 技術。 所示資料處理裝置符合該說明簡介中提及的先前 為允终更好地分松辑^ 刀圻氣次約束，所提供之構 置3於映射過程中出 卞6在映射裝 憶體2内儲存錯誤丄：5吳時，可在CPU1可存取的-記 f生之H 1 射裝置3内貫施用以識別一錯誤 ，置’其亦屬於常用之先前技術，錯誤發生 跟一錯誤碼，即一扭起杜〜、 P鈦祆-特疋序號，報告回至CPU i。 本發明，與此同時錯誤約束 體2。 j果储存入CPU 1可存取之一記憶 下列約束對確定基本原因尤其重要： 程式計數器之内容： .程式計數器亦稱為指令指標，識別包含一錯誤之指令的 位元址。 指令長度： 若存在不同指令長 碼並保持就緒，例如 指令格式： 度，例如16或32位元，相應長度應編 「〇」對16位元或「1」對32位元。 才曰令編碼亦稱A > y. ^ 马〗曰令格式或OP編碼，以不變方式及/或 依據一近似分級方 Μ、、 、’ A (如跳躍、記憶體存取、算術、操作 寺）記錄。相庥藉彳k A #式咬計指令係讀取、寫入、修改、執行。 目的地位址： 為包含位址運算 中。該等位址運算 址、暫存器位址或 圈指令亦可存取大 A之·操作，這些會儲 70可以係邏輯或虛擬 桃躍位址。在本文中 f邏輯位元址。除邏 存在一暫存器記錄 記憶體或周邊位元 ，特定操作如多迴 輯位元址外，物理 200307866 (4) 發明說明績頁 位元址亦可儲存。本文中虛擬位元址與物理位元址通常長 度有別，例如'一虛擬位元址長度係3 2位元而該物理目的地 位元址長度係20位元。一些情形中，虛擬位元址至物理位 元址的轉換包括多階段表格存取操作’其依次成為記憶體 存取操作。此情形中，亦儲存中間位址。 許可權狀態： 一將要執行之指令的許可權狀態，例如有特權或無特 權，係與呼叫請求、使用者或作業系統核心相關連。目前 许可權狀態及執行此存取貫際需要之许可權同樣在一暫存 器中保持就緒。「必需許可權」應理解為表示一特定記憶 體結構單元之屬性，用於記憶體保護機制，如唯讀、唯寫 或可執行編碼。 另外，錯誤類型識別序號如先前技術一樣儲存。 請求者識別係扮演著一重要作用。因而來自CPU、快取 記憶體或另一控制器的請求可有不同許可權。儘管CPU自 己提示的特定操作之執行可無錯誤，同樣的操作由另一控 制器請求則可出現錯誤，因為此另一控制器沒有執行該操 作的必需許可權。 在所說明的資料處理裝置中，CPU 1具有一相關聯之錯 誤處理裝置7，其在映射裝置3發出錯誤碼通知後’為錯誤 約束檢查儲存於記憶體2中的資料以便確定錯誤。此情形 中’ CPU可存取之記憶體2可藉該CPU的暫存器形成。 進一步錯誤約束之記錄係在技術能力範圍内因而涵蓋于 本發明之内。 200307866 r5、 I發明說明續頁 圖式簡單說明 該圖係本發明之一資料處理裝i的示意圖。 圖式代表符號說明 1 處理器 2 記憶體 3 映射裝置 4 虛擬記憶體 5 實體記憶體 6 用於儲存錯誤約束之構件裝置 7 錯誤處理裝置 •10-A little bit of technology. The data processing device shown is in accordance with the earlier mentioned in the introduction, which allows for a better loosening of ^ ^ gas frequency constraints, the provided structure 3 during the mapping process 6 out of the mapping memory 2 Storage error: 5 hours, it can be applied in the CPU 1 accessible to the H 1 shooting device 3 to identify an error, and it is also a commonly used prior technology. An error occurs with an error code. That is, once the serial number of the 〜 ~, 祆-祆, 疋-疋 is returned, the report is returned to the CPU i. In the present invention, the body 2 is erroneously constrained at the same time. The following constraints are particularly important for determining the basic cause: The contents of the program counter: The program counter is also known as the instruction indicator, identifying the bit address of an instruction containing an error. Instruction length: If there are different instruction length codes and keep them ready, for example Instruction format: Degree, for example, 16 or 32 bits, the corresponding length should be "0" for 16 bits or "1" for 32 bits. The order code is also known as A > y. ^ Ma〗 The order format or OP code, in a constant manner and / or according to an approximate hierarchical method M ,,, 'A (such as jump, memory access, arithmetic, Operation Temple) record. The relative borrowed A # type bite meter instruction is read, write, modify, and execute. Destination address: Include address calculation. Such address operation addresses, register addresses, or loop instructions can also access large A operations. These storage addresses can be logical or virtual peach addresses. F logical bit address in this paper. In addition to logic, there is a register to record memory or peripheral bits, and specific operations such as multiple-reset bit addresses. Physics 200307866 (4) Inventory page. Bit addresses can also be stored. The length of the virtual bit address and the physical bit address are usually different in this paper. For example, 'a virtual bit address length is 32 bits and the physical destination bit address length is 20 bits. In some cases, the conversion from a virtual bit address to a physical bit address includes a multi-stage table access operation 'which in turn becomes a memory access operation. In this case, the intermediate address is also stored. Permission status: The permission status of an instruction to be executed, such as privileged or non-privileged, is related to the call request, user, or operating system core. The current permission status and the permissions required to perform this access are also kept in a temporary register. “Required permission” should be understood to mean a property of a specific memory structural unit, used for memory protection mechanisms, such as read-only, write-only, or executable coding. In addition, the error type identification number is stored as in the prior art. Requester identification plays an important role. So requests from the CPU, cache, or another controller can have different permissions. Although the execution of a particular operation suggested by the CPU itself may be error-free, the same operation may be errored when requested by another controller because this other controller does not have the necessary permissions to perform the operation. In the illustrated data processing device, the CPU 1 has an associated error processing device 7 which checks the data stored in the memory 2 for error determination after the mapping device 3 issues an error code notification 'to determine the error. In this case, the 'CPU accessible memory 2 can be formed by the CPU's register. Records of further error constraints are within the scope of technical capabilities and are therefore covered by the present invention. 200307866 r5, I Description of the invention Continuation page Brief description of the drawing This figure is a schematic diagram of a data processing device i of the present invention. Explanation of the symbols of the drawings 1 processor 2 memory 3 mapping device 4 virtual memory 5 physical memory 6 component device for storing error constraints 7 error processing device 10-