200306074 玖、發明說明 【發明所屬之技術領域】 本發明係關於振幅轉換電路，尤其是關於供轉換信號振 幅用的振幅轉換電路。 【先前技術】 圖2 7所示係相關習知行動電話之影像顯示部分構造的 方塊圖。 在圖27中，此行動電話係具備有：屬於MOST(MOS電晶 體）型積體電路的控制用L S I 7 1、屬於Μ Ο S T型積體電路的 位準轉換器72、以及屬於TFT (薄膜電晶體）型積體電路的 液晶顯示裝置7 3。 控制用LS171係產生液晶顯示裝置73用的控制信號。 此控制信號的「Η」位準爲3 V，而「L」位準則爲0 V。控 制信號實際上產生多數個，但是在此爲求說明上的簡化， 便將控制信號設定爲一個。位準轉換器72係將來自控制用 LSI7 1的控制信號之邏輯位準進行轉換，而產生內部控制 信號。此內部控制信號的「Η」位準爲7.5 V，而「L」位準 則爲0V。液晶顯示裝置73係依據來自位準轉換器72的內 控制信號而顯示出影像。 圖2 8所示係位準轉換器7 2構造的電路圖。在圖2 8中， 此位準轉換器72係包含有：Ρ通道MOS電晶體74,7 5、及Ν 通道MOS電晶體76,77。Ρ通道MOS電晶體74,75係分別 連接於電源電位 VCC(7.5V)的節點 Ν71與輸出節點 N74，N75之間，該等的閘極則分別連接於輸出節點 5 312/發明說明書(補件)/92-05/921 (M3 80 200306074 N75，N74。N通道MOS電晶體76,77係分別連接 點N7 4，N75與接地電位GND的節點之間，該等 分別接收輸入信號VI，/VI。 現況乃將輸入信號VI，/VI分別設定爲「L」位 以及「H」位準（3V)，而輸入信號V0，/V0則分別設 位準（7.5V)，以及「L」位準（0V)。此時，MOS電曰1 將呈導通狀態，而MOS電晶體7 5,7 6則呈非導通 在此狀態下，若輸入信號VI從「L」位準（0V)提 位準（3 V)，同時輸入信號/VI從「Η」位準（3 V)下 位準（0V)的話，首先Ν通道MOS電晶體76便將 降低輸出節點Ν74的電位。輸出節點Ν74的電位 電位V C C減掉Ρ通道Μ Ο S電晶體7 5的臨限電壓 後的電位値爲低的話，Ρ通道MOS電晶體75便開 而輸出節點Ν7 5電位便將開始上升。若輸出節點 位開始上升的話，Ρ通道MOS電晶體74之源極-電壓將變小，而Ρ通道MOS電晶體74的導通電 變高，使輸出節點Ν74的電位更加降低。所以， 正回饋（positive feedback)的進行動作，輸入信顯 則將分別變成「L」位準（0 V )與「Η」位準（7.5 V ) 位準轉換動作。 再者，亦有將Ρ通道Μ 0 S電晶體7 4，7 5的閘極 接於一個輸出節點Ν7 4或Ν75的位準轉換器。此 換器有如日本專利特開平丨丨-1 4 5 8 2 1號公報中所;200306074 (1) Description of the invention [Technical field to which the invention belongs] The present invention relates to an amplitude conversion circuit, and more particularly to an amplitude conversion circuit for converting the amplitude of a signal. [Prior Art] Fig. 27 is a block diagram showing the structure of an image display portion of a related conventional mobile phone. In FIG. 27, this mobile phone is provided with a control LSI 7 which is a MOST (MOS transistor) integrated circuit, a level converter 72 which is an M0 ST integrated circuit, and a TFT (thin film). Liquid crystal display device 73 of a transistor) type integrated circuit. The control LS171 series generates a control signal for the liquid crystal display device 73. The "Η" level of this control signal is 3 V, and the "L" bit criterion is 0 V. There are actually many control signals, but to simplify the explanation, the control signal is set to one. The level converter 72 converts the logic level of the control signal from the control LSI 71 to generate an internal control signal. The “Η” level of this internal control signal is 7.5 V, and the “L” level is 0V. The liquid crystal display device 73 displays an image based on an internal control signal from the level converter 72. FIG. 28 is a circuit diagram of the structure of the level converter 72. In FIG. 28, the level converter 72 includes: P-channel MOS transistors 74, 75, and N-channel MOS transistors 76, 77. The P-channel MOS transistors 74 and 75 are respectively connected between the node N71 of the power supply potential VCC (7.5V) and the output nodes N74 and N75, and the gates of these are respectively connected to the output node 5 312 / Invention Specification (Supplement) ) / 92-05 / 921 (M3 80 200306074 N75, N74. N-channel MOS transistors 76, 77 are connected between the points N7 4, N75 and the node of the ground potential GND, and these respectively receive the input signal VI, / VI The current situation is that the input signals VI and / VI are set to the "L" and "H" levels (3V), while the input signals V0 and / V0 are set to the (7.5V) and "L" levels, respectively. (0V). At this time, the MOS transistor 1 will be on, and the MOS transistors 7 5, 7 6 will be non-conductive. In this state, if the input signal VI is raised from the "L" level (0V) (3 V), at the same time the input signal / VI goes from the "Η" level (3 V) to the lower level (0 V), first the N-channel MOS transistor 76 will reduce the potential of the output node N74. The potential of the output node N74 is VCC If the potential after subtracting the threshold voltage of the P channel MOS transistor 7 5 is low, the P channel MOS transistor 75 is turned on and the output node N7 5 potential is reduced. It starts to rise. If the output node bit starts to rise, the source-voltage of the P-channel MOS transistor 74 will become smaller, and the conduction of the P-channel MOS transistor 74 will become higher, which will cause the potential of the output node N74 to decrease even more. Positive feedback (positive feedback) is performed, and the input signal display will become the "L" level (0 V) and "Η" level (7.5 V) level conversion actions. Furthermore, there is also a P channel M The gate of 0 S transistor 7 4, 7 5 is connected to a level converter of output node N7 4 or N75. This converter is as disclosed in Japanese Patent Laid-Open No. 丨 丨 -1 4 5 8 2 1;
如此的話’習知的位準轉換器72乃以配合輸J 312/發明說明書(補件)/92-05/92104380In this case, the conventional level converter 72 is matched with the input J 312 / Invention Specification (Supplement) / 92-05 / 92104380
於輸出節 的閘極則 準（0V)， 定爲「H」 ^ 體 74,77 狀態。 昇至「H」 降至「L」 導通，並 若較電源 的絕對値 I始導通， N 7 5的電 閘極間的 阻値則將 電路便將 I V05/V0 ，而完成 二者均連 種位準轉 掲示者。 、信號VI 6 200306074 k「L·」位準（〇V)提昇至「H」位準（3V)，而導通n通道 MOS電晶體76爲產生動作的提前。在爲導通N通道M〇s 電晶體7 6方面，便必須使n通道Μ 0 S電晶體7 6的臨限 電位在輸入信號V I的「Η」位準（3 V)以下。 在一般的半導體L S I中，將電晶體的臨限電位設定在3 ν 下之事雖尙屬容易，但是對液晶顯示裝置中所含的低溫多 晶矽TFT而言，則因爲臨限電壓的誤差較大，頗難將TFT 的臨限電壓設定在3 V以下。因此，如圖2 7所示，便將由 高耐壓Μ Ο S電晶體所構成的位準轉換器7 2，設置在控制 用L S I 7 1與液晶顯示裝置7 3之間，並執行信號的邏輯位準 轉換。 但是，若設計此種位準轉換器7 2的話，位準轉換器7 2 的成本將加計於系統成本上，導致系統成本上升。 【發明內容】 有鑒於斯，本發明的主要目的在於提供一種即便在輸入 信號的振幅電壓低於輸入電晶體的臨限電壓之情況下，仍 可正常進行動作的振幅轉換電路及採用其之半導體裝置。 本發明的振幅轉換電路係爲將其振幅屬於第1電壓的第 1信號，轉換爲其振幅高於第1電壓之屬於第2電壓的第2 信號，而具備有：第1導電形式第1與第2電晶體、第2導 電形式第3與第4電晶體；以及驅動電路。第1與第2電 晶體的第1電極均接收第2電壓，該等的第2電極則分別 連接於供輸出第2信號與其互補信號用的第1與第2輸出 節點上，該等的輸入電極則分別連接於第2與第1輸出節 312/發明說明書(補件)/92-05/921043 80 200306074 點。第3與第4電晶體的第1電極係分別連接於第1與第 2輸出節點上。驅動電路係利用第1信號與其互補信號而 驅動著，並響應第1信號的互補信號前緣，將高於第1電 壓的第3電壓供應給第3電晶體的輸入電極與第2電極 間，俾導通第3電晶體，響應著第1信號之互補信號後緣 所對應的上述第1信號前緣，將第3電壓供應給第4電晶 體的輸入電極與第2電極之間，而導通第4電晶體。所以， 因爲將響應著第1信號之互補信號前緣、或第1信號前緣， 將高於第1電壓的第3電壓提供給第3或第4電晶體的輸 入電極與第2電極間，而導通第3或第4電晶體，因此即 便第1信號的振幅低於第3與第4電晶體的臨限電壓之情 況下，仍可正常的動作。 再者’本發明的另一振幅轉換電路，係爲將其振幅屬於 第1電壓的第1信號，轉換爲其振幅高於第1電壓之屬於 第2電壓的第2信號，而具備有：第〗導電形式第1與第2 電晶體、第2導電形式第3與第4電晶體；以及驅動電路。 第1與第2電晶體的第1電極均接收第2電壓，該等的第 2電極則分別連接於供輸出第2信號與其互補信號用的第i 與第2輸出節點上，該等的輸入電極則均連接於第2輸出 節點。第3與第4電晶體的第1電極係分別連接於第1與 第2輸出節點上。驅動電路係利用第1信號與其互補信號 而驅動者’並響應第1信號的互補信號前緣，將高於第1 電壓的桌3電壓供應給％ 3電晶體的輸入電極與第2電極 間’俾導通第3電晶體’響應著第丨信號之互補信號後緣 8 312/發明說明書(補件)/92-05/921043 80 200306074 所對應的上述第1信號前緣，將第3電壓供應給第4 體的輸入電極與第2電極之間，而導通第4電晶體。所 因爲將響應著第1信號之互補信號前緣、或第1信號言 將高於第1電壓的第3電壓提供給第3或第4電晶體 入電極與第2電極間，而導通第3或第4電晶體，因 便第1信號的振幅低於第3與第4電晶體的臨限電壓 況下，仍可正常的動作。 【實施方式】 圖1爲顯示本發明一實施形態之行動電話影像顯示 部分的構造的方塊圖。 在圖1中，此行動電話係具備有：屬於MOST型積體 的控制用LSI1、及屬於TFT型積體電路的液晶顯示裝 液晶顯示裝置2係含有：位準轉換器3與液晶顯示部4 控制用L S 11係輸出液晶顯示裝置2用的控制信號 控制信號的「Η」位準爲3 V，而「L」位準則爲〇 V。 信號實際上產生多數個，但是在此爲求說明上的簡化 將控制信號設定爲一個。位準轉換器3係將來自控 LSI1的控制信號之邏輯位準進行轉換，而產生內部控 號。此內部控制信號的「Η」位準爲7 · 5 V，而「L」位 爲0V。液晶顯示裝置4係依據來自位準轉換器3的內 信號而顯示出影像。 圖2爲顯示位準轉換器3構造的電路圖。在圖2中 位準轉換器3係包含有：卩型丁？丁5,6、1^型丁？丁7〜14、 器15，16、及電阻元件17。Ρ型TFT5,6係分別連接於 312/發明說明書(補件)/92-05/92104380 電晶 ;以， ί緣， 的輸 此即 之情 關聯 電路 置2 〇 。此 控制 ，便 制用 制信 準則 控制 ，此 電容 電源 9 200306074 電位V c C ( 7 · 5 V )的節點N丨與輸出節點N 5，N 6 的鬧極則分別連接於輸出節點N6，N5。在輸出 中所出現的信號分別形成此位準轉換器3 ν〇，/ν〇。N型TFT7連接於節點N5與N7之間 連接f卩點N 1 1。N型τ F T 8連接於節點N 6與 其聞極則連接於節點N 1 3。對節點n 7 N 8分別 號VI與其互補信號/VI。 電阻元件17與N型TFT9,1〇係串聯連接於電 之卽點N 1、與接地電位G N D之節點之間。n S 極係連接於其汲極（節點N 9 )上，N型T F T 1 0之 其汲極上。N型TFT9，10係分別構成二極體元 件17與N型TFT9, 10係構成定電位產生電路 元件17的電阻値設定爲充分大（譬如ι〇〇μω) T F T 9，1 〇的導通電阻値設定爲充分小於電阻元彳 的話’節點N9的電位V9便將成爲V9 = 2VTN。 係指N型TFT的臨限電位。 N型TFT11係連接電源電位VCC之節點N1 之間，其閘極將接收節點N 9的電位V 9。N型 接於節點N 1 1與N 1 2之間，其閘極則連接於節 N型TFT12係構成二極體元件。電容器15係 Nil與N12之間。對節點N12提供信號/ VI。 N型TFT13係連接電源電位VCC之節點N1 之間，其閘極將接收節點N9的電位V9。N型 接於節點N 1 3與N 1 4之間，其閘極則連接於節 312/發明說明書(補件)/92-05/921043 80 之間，該等 節點N5，N6 的輸入信號 ，其閘極則 ! N8之間， 供應輸入信 源電位V C C 2 TFT9之閘 閘極連接於 件，電阻元 。若將電阻 ，並將N型 丨牛1 7電阻値 其中，VTN 與節點N 1 1 TFT12係連 點Nil上。 連接於節點 與節點N 1 3 TFT14係連 點N13上。 10 200306074 N型T F Τ 1 4係構成二極體元件。電容器1 6係連接於節點 Ν 1 3與Ν 1 4之間。對節點Ν 1 4提供輸入信號VI。 其次，針對此位準轉換器3的動作進行說明。現今若將 輸入信號VI，/VI分別設定爲3V、0V的話，Ν型TFT11便 將藉由源極浮置動作，使節點 Ν1 1的電位 V1 1成爲 VI 1 =2 VTN-VTN = VTN。此外，因爲連接於二極體的N型 TFT12之臨限電位將爲VTN，因此幾乎未從電源電位VCC 的節點Ν 1對節點Ν 1 2流入電流。因爲ν型T F T 7的閘極 電位爲V11=VTN，其源極電位爲3V，因此N型TFT7便 將呈非導通狀態。電容器1 5便被充電至臨限電壓V TN。 此外，如後述，因爲節點Ν 1 3的電位V 1 3將昇壓至VTN 以上，且節點N8將變爲0V，因此N型TFT 8便將被導通。 結果’輸出節點N 6便將成爲輸入節點N 8的電位（0 V )，而 導通P型TFT5，並使輸出節點N5成爲電源電位VCC。藉 此，P型TFT6便將處於非導通狀態，在電源電位VCC之 節點Ν 1與輸入節點N8之間並未流通電流。 其次，若將輸入信號VI從3 V下降至〇 V，同時將輸入 信號/VI從0V上升至3V的話，輸入信號/VI的電位變化 變將藉由電容耦合而經由電容器1 5傳輸給節點Ν 1 1，使節 點Ν 1 1的電位V 1 1被昇壓。若將電容器1 5的電容量設定 爲充分大於節點Nil之寄生電容（未圖示）的電容量的話， 節點 Nil 的電位 VII 便將成爲 VII与VTN+Δ VI = VTN + 3V。其中，△ VI係指輸入信號VI，/VI的振幅， 爲3 V。因爲N型TFT7的源極（節點N7)電位將變爲0V， 11 312/發明說明書(補件)/92-05/92104380 200306074 因此N型T F Τ 7的閘極-源極間電壓將爲ν Τ N + 3 V，而導通 N型TFT7。結果’輸出節點N5的電位便將爲〇V，而導通 Ρ 型 TFT6 ° 此外，輸入信號VI從3 V至0V的電位變化，將利用電 容耦合而經由電容器1 6傳輸給節點ν 1 3，而使節點Ν 1 3 的電位V13降壓。當輸入信號VI，/VI的變化週期屬於較短 的情況時，因爲在降壓前的節點N 1 3之電位V 1 3將成爲 V 1 3 = V T N + 3 V，因此降壓時的節點n 1 3之電位V 1 3便將成 爲V13=VTN + 3V-3V = VTN。當輸入信號VI，/VI的變化週期 屬於較長的情況時，因爲節點N 1 3之電位V 1 3將處於藉由 電容耦合而昇壓的電位狀態，因此將隨時間而降低。因此， 節點N13之電位V13僅降低較輸入信號VI，/VI變化週期 較短之情況時的値VTN爲低的部分，此情況下，N型TFT 1 3 將導通，而將節點N 1 3的電位V 1 3拉升至V TN。 如上述，因爲N型TFT8的閘極電位V13將變爲VTN， 而其源極（節點N8)電位將變爲3 V。因此N型TFT8便處於 非導通狀態。結果，輸出節點N6的電位便將爲7.5V，而 P型TFT5則變爲非導通狀態。如此的話，輸出節點N5，N6 便將分別爲〇V、7.5V，而形成執行從3 V變爲7.5V的邏 輯位準轉換。 在本實施形態中，因爲響應著輸入信號VI的下降邊緣， 將Ν型TFT7的臨限電壓VTN中加計著輸入信號/VI之振 幅電壓（3 V)後的電壓VTN + 3 V ’供應給Ν型TFT7的閘極-源極間，因此即便輸入信號/VI的振幅電壓（3 V)低於Ν型 12 312/發明說明書(補件)/92-05/92104380 200306074 TFT7的臨限電壓VTN之情況時，仍可使位準轉換器3正 常的產生動作。所以，如圖1所示，可將位準轉換器3與 液晶顯示部4形成一個液晶顯不裝置2 ( T F Τ型積體電路）。 所以，相較於需要個別設計位準轉換器5 2與液晶顯示裝置 5 3的習知技術之下，可減少組件數量，並降低系統成本。 再者，雖在動作中途過度性的流通著電源電流，但是除 電阻元件17與Ν型TFT 9，10之外，並未流通直流的電流。 因爲電阻元件1 7電阻値設定爲較大値，而僅流通著微小電 流，因此位準轉換器3的消耗功率極小。 再者，在本實施形態中雖採用T F T 5〜1 4，但是亦可取代 TFT而改爲採用MOS電晶體。此情況下，即便在輸入信號 VI，/VI的振幅小於MOS電晶體臨限電壓的情況下，仍可進 行動作。 再者，在本實施形態中雖採用屬於絕緣閘型場效電晶體 的TFT，但是當然亦可採用其他形式的場效電晶體。 以下，針對此實施形態的各種變化例進行說明。在圖3 之位準轉換器20中，N型TFT1 2,14的源極呈接地狀態。 在此變化例中，因爲N型TFT 12，14的電流將不致流入節 點N1 2，N14中，而流入接地電位GND的節點中，因此輸 入信號VI，/VI的驅動力便將變小。 在圖4的位準轉換器21中，對P型TFT 5,6的源極賦予 電源電位VCC(7.5 V)，並對N型TFT1 1的汲極賦予不同於 電源電位V C C的正電源電位V C C ’，對電阻元件1 7的其中 一電極（未連接於節點N9上的電極）賦予不同於電源電位 13 312/發明說明書(補件)/92-05/92104380 200306074 V C C，V C C ’的電源電位V c C ”。在此變化例中，譬如可防止 隨電源電位 VCC節點中所產生的雜音，而使節點 N9，N11，N13的電位V9，V11，V13產生變動。 在圖5的位準轉換器22中，電阻元件17係由P型TFT23 所構成。換句話說，P型TFT23係連接於電源電位VCC之 9卩點N 1 Μ自卩點n 9之間’其閘極則連接於接地電位g n D 的節點。由T F Τ所構成的電阻元件之平均單位面積電阻 値’係大於由擴散層所構成的電阻元件之平均單位面積電 阻値。所以’在此變化例中，可縮小電阻元件的佔有面積。 另外，由閘極接收電源電位V C C的Ν型T F Τ所構成的電 阻元件1 7，亦可獲得相同的效果。 在圖6的位準轉換器24中，追加設置Ν型TFT25,26。 Ν型T F Τ 2 5係連接於節點Ν 5與Ν 7之間，其閘極則連接於 節點Ν 6。Ν型T F Τ 2 6係連接於節點ν 6與Ν 8之間，其閘 極則連接於節點Ν5。若輸入信號VI，/VI分別呈「Η」位準 與「L」位準，且輸入信號ν〇，/ν〇分別呈ΓΗ」位準與「L」 位準的話，N型丁FT25便將呈非導通狀態，同時ν型丁FT 2 6 將導通，而使輸出節點N5，N6分別保持於「H」位準與「L」 位準。若輸入信號VI，/VI分別呈「L」位準與「H」位準， 且輸入信號VO，/VO分別呈「L」位準與「H」位準的話， N型T F T 2 5便將呈導通狀態，同時ν型T F T 2 6將處於非導 通狀態，而使輸出節點N5，N6分別保持於「L」位準與「H」 位準。 當輸入信號VI，/VI的變化週期屬於非常長的情況時，節 312/發明說明書(補件)/92-05/921043 80 14 200306074 點N 1 1，N 1 3的電位v 1 1，V 1 3均將變成N型T F T的臨限電 位VTN，輸出節點Ν5與Ν6的電位關係有反轉的可能性。 Ν型TFT2 5,2 6便屬於供防止發生此種節點Ν5與Ν6的電 位關係反轉現象者，而在無關節點Ν 1 1，Ν 1 3的電位 V 1 1，V 1 3的情況下，將節點Ν 5，Ν 6的電位予以固定。 圖7的位準轉換器27係屬於將圖6所示位準轉換器24 的Ν型TFT2 5,2 6之源極，連接於接地電位GND的節點上 者。在此變化例中，因爲N型T F T 2 5，2 6的電流並未流入 輸入節點N 7，N 8中，而是流入接地電位G N D的節點中， 因此便可減小輸入信號V I，/ V I的驅動力。 圖8的位準轉換器3 0係屬於將圖2所示位準轉換器3 的N型TFT7,8之源極，均連接於接地電位GND節點上者。 在此變化例中，因爲N型T F T 7，8的電流並未流入輸入節 點N7，N8中，而是流入接地電位GND的節點中，因此便 可減小輸入信號VI，/VI的驅動力。 圖9的位準轉換器3 1係屬於將圖7所示位準轉換器2 7 的N型TFT7,8,2 5,26之源極，均連接於接地電位Gnd節 點上者。在此變化例中，因爲N型T F T 7，8，2 5，2 6的電流並 未流入輸入節點N7，N8中，而是流入接地電位GND的節 點中，因此便可減小輸入信號VI，/VI的驅動力。 圖1 0的位準轉換器3 2係屬於將圖2所示位準轉換器3 的P型TFT5,6之閘極，均連接於節點N5上者。P型TFT5,6 係構成電流鏡電路（current mirror circuit)。在P型TFT5 與6中流通著同値的電流。當輸入信號VI，/VI非別呈「L i 15 312/發明說明書(補件)/92-05/921 (M3 80 200306074 位準與「Η」位準，且N型TFT7,8分別呈導通狀態與非導 通狀態之情況時，與TFT5，7中所流通電流相同値的電流， 亦將流入於P型TFT6中，並執行差洞放大。輸出節點N5，N6 便分別呈「L」位準與「Η」位準。在此變化例中，亦可獲 得如同圖2之位準轉換器3相同的振幅轉換效果。 圖1 1的位準轉換器3 3係屬於將圖6所示位準轉換器2 4 的Ρ型TFT5,6之閘極，均連接於節點Ν5上者。在此變化 例中，亦可獲得如同圖6之位準轉換器2 4相同的振幅轉換 效果。 圖1 2的位準轉換器3 4係屬於將圖1 〇所示位準轉換器 32的N型TFT 7,8之源極均呈接地狀態者。在此變化例中， 因爲N型T F T 7，8中所流通的電流並未流入輸入節點n 7，N 8 中，而是流入接地電位GND的節點中，因此便可減小輸入 信號VI，/VI的驅動力。 圖1 3的位準轉換器3 5係屬於將圖1 1所示位準轉換器 33的N型TFT7,8,2 5,2 6之源極均呈接地狀態者。在此變 化例中，因爲N型TFT7，8，2 5,2 6中所流通的電流並未流入 輸入節點N 7，N 8中，而是流入接地電位G N D的節點中， 因此便可減小輸入信號VI，/VI的驅動力。 在圖14的變化例中，含有電阻元件17與N型TFT9,10 的定電位產生電路36，係對複數位準轉換器3 8,3 9,…共通 設置。在定電位產生電路3 6的輸出節點N9、與接地電位 GND的節點之間，連接著電位安定化用電容器3 7。雖在爲 使電阻元件1 7的電阻値增加方面，需要增加電阻元件J 7 16 312/發明說明書(補件)/92-05/92104380 200306074 的面積’但是在本變化例中，因爲對複數位準轉換器 3 8，3 9，…共通設置定電位產生電路3 6，因此可減小整體電 路的佔有面積。 圖1 5的位準轉換器4 〇係在圖2的位準轉換器3中，追 加設置P型TFT41，42者。p型TFT41係連接於P型TFT5 的汲極與輸出節點N 5之間，其閘極則連接於節點n 1 1上。 P型TFT42係連接於P型TFT6的汲極與輸出節點N6之 間，其閘極則連接於節點N 1 3上。若輸入信號/VI從0V上 升至3 V的話’節點N 1 1的電位v 1 1便將爲V TN + 3 V，使P 型TFT41呈非導通狀態，同時使導通n型TFT7，而使輸 出節點N 5的電位變爲〇 v。因爲此時的p型τ F T 4 1處於非 導通狀態’因此電流並未從電源電位V C C的節點N 1流入 輸出節點N 5中，而使輸出節點N5的電位容易下降爲0V。 若輸入信號/ VI從3 V下降至〇v的話，節點Nl 1的電位VI 1 便將爲VTN，N型TFT7便將處於非導通狀態，同時p型 TFT41將導通，使輸出節點N5的電位變爲7.5V。 再者’若輸入信號VI從0V上升至3 V的話，節點N1 3 的電位V13便將爲VTN + 3V’使P型TFT42呈非導通狀態， 同時使導通N型TFT8，而使輸出節點N6的電位變爲0V。 因爲此時的P型T F T 4 2處於非導通狀態，因此電流並未從 電源電位VCC的節點N1流入輸出節點N6中，而使輸出 節點N6的電位容易下降爲〇V。若輸入信號vi從3V下降 至0V的話，節點N13的電位V13便將爲VTN，N型TFT8 便將處於非導通狀態，同時P型TFT42將導通，使輸出節 17 312/發明說明書(補件)/92-05/92104380 200306074 點 N 6的電位變爲7.5 V。在此變化例中，因爲輸出節點 N5，N6的電位較容易降低至0V，因此便可將輸入信號 VI，/VI的振幅僅縮小此部份，而使輸入信號VI，/VI的振幅 邊限變大。 圖16〜26的位準轉換器45〜55係分別在圖3〜圖13所示 位準轉換器20〜22,24,27,30〜35中追加P型TFT41，42者。 該等變化例亦可獲得如同圖1 5之位準轉換器40相同的效 果。 本次所揭示的實施形態全部均僅止於例示而已，不可認 爲係屬於限制。本發明的範圍並非上述說明，而是經申請 專利範圍所揭示者，舉凡在與申請專利範圍具均等涵義與 範疇內的所有變化均涵蓋在內。 【圖式簡單說明】 圖1爲本發明一實施形態之行動電話影像顯示所關聯部 分的構造方塊圖。 圖2爲圖1所示位準轉換器構造的電路圖。 圖3〜26分別爲本實施形態變化例的電路圖。 圖2 7爲習知行動電話影像顯示所關聯部分的構造方塊 圖。 圖2 8爲圖2 7所示位準轉換器構造的電路圖。 (元件符號說明）The gate of the output node is standard (0V), and is set to "H" ^ body 74,77 state. Rise to “H” to “L” to turn on, and if it is turned on more than the absolute power of the power supply, the resistance between the gates of N 7 5 will turn the circuit to I V05 / V0, and both are completed. Level shifter. Signal VI 6 200306074 k The “L ·” level (0V) is raised to the “H” level (3V), and the n-channel MOS transistor 76 is turned on in order to generate the action in advance. In order to turn on the N-channel Mos transistor 76, the threshold potential of the n-channel M0S transistor 76 must be below the "Η" level (3 V) of the input signal VI. In general semiconductor LSIs, it is easy to set the threshold potential of a transistor at 3 ν, but for low-temperature polycrystalline silicon TFTs included in liquid crystal display devices, the threshold voltage error is large. It is quite difficult to set the threshold voltage of the TFT below 3 V. Therefore, as shown in FIG. 27, a level converter 72 composed of a high withstand voltage MOS transistor is set between the control LSI 71 and the liquid crystal display device 73, and the logic of the signal is executed. Level shift. However, if such a level converter 72 is designed, the cost of the level converter 72 will be added to the system cost, resulting in an increase in the system cost. SUMMARY OF THE INVENTION In view of this, a main object of the present invention is to provide an amplitude conversion circuit capable of operating normally even when the amplitude voltage of an input signal is lower than a threshold voltage of an input transistor, and a semiconductor using the same. Device. The amplitude conversion circuit of the present invention is to convert a first signal whose amplitude belongs to the first voltage to a second signal whose amplitude is higher than the first voltage and belongs to the second voltage, and includes: a first conductive form; A second transistor, a second conductive type of the third and fourth transistors; and a driving circuit. The first electrodes of the first and second transistors both receive the second voltage, and the second electrodes of these are respectively connected to the first and second output nodes for outputting the second signal and its complementary signal, and the inputs of such The electrodes are respectively connected to the second and first output sections 312 / Invention Specification (Supplement) / 92-05 / 921043 80 200306074 points. The first electrodes of the third and fourth transistors are connected to the first and second output nodes, respectively. The driving circuit is driven by the first signal and its complementary signal, and in response to the complementary signal leading edge of the first signal, supplies a third voltage higher than the first voltage between the input electrode and the second electrode of the third transistor.俾 Turn on the third transistor, and in response to the first signal leading edge corresponding to the trailing edge of the complementary signal of the first signal, supply a third voltage between the input electrode of the fourth transistor and the second electrode, and turn on the 4 transistor. Therefore, in response to the complementary signal leading edge of the first signal or the leading edge of the first signal, a third voltage higher than the first voltage is provided between the input electrode and the second electrode of the third or fourth transistor, Since the third or fourth transistor is turned on, even if the amplitude of the first signal is lower than the threshold voltage of the third and fourth transistors, it can still operate normally. Furthermore, another amplitude conversion circuit of the present invention is to convert a first signal whose amplitude belongs to the first voltage to a second signal whose amplitude is higher than the first voltage and belongs to the second voltage, and includes: The first and second transistors of the conductive form, the third and fourth transistors of the second conductive form, and a driving circuit. The first electrodes of the first and second transistors both receive the second voltage, and the second electrodes of these are respectively connected to the i and second output nodes for outputting the second signal and its complementary signal, and the inputs of such The electrodes are all connected to the second output node. The first electrodes of the third and fourth transistors are connected to the first and second output nodes, respectively. The driving circuit uses the first signal and its complementary signal to drive the driver 'and responds to the complementary signal leading edge of the first signal to supply the voltage of the table 3 higher than the first voltage to the% 3 between the input electrode of the transistor and the second electrode'俾 Turn on the 3rd transistor 'in response to the complementary signal trailing edge of the 丨 signal 8 312 / Invention Specification (Supplement) / 92-05 / 921043 80 200306074 corresponding to the aforementioned leading edge of the first signal, and supply the 3rd voltage to The fourth transistor is turned on between the input electrode of the fourth body and the second electrode. This is because the complementary signal leading edge of the first signal, or the first signal, a third voltage higher than the first voltage is provided between the third or fourth transistor input electrode and the second electrode, thereby turning on the third signal. Or the fourth transistor can operate normally even when the amplitude of the first signal is lower than the threshold voltage of the third and fourth transistors. [Embodiment] Fig. 1 is a block diagram showing the structure of a video display portion of a mobile phone according to an embodiment of the present invention. In FIG. 1, this mobile phone is provided with a control LSI 1 which is a MOST type integrated body, and a liquid crystal display device liquid crystal display device 2 which is a TFT type integrated circuit, which includes a level converter 3 and a liquid crystal display portion 4. The "LS" level of the control signal for the LS 11 series output control signal for the liquid crystal display device 2 is 3 V, and the "L" level criterion is 0V. A plurality of signals are actually generated, but for simplicity of explanation, the control signal is set to one. The level converter 3 converts the logic level of the control signal from the control LSI1 to generate an internal control signal. The "Η" level of this internal control signal is 7 · 5 V, and the "L" bit is 0V. The liquid crystal display device 4 displays an image based on an internal signal from the level converter 3. FIG. 2 is a circuit diagram showing the structure of the level converter 3. As shown in FIG. In Figure 2, the level converter 3 series includes: Ding 5, 6, 1 ^ Ding? Ding 7 to 14, devices 15, 16, and resistance element 17. The P-type TFT5 and 6 are connected to the 312 / Invention Specification (Supplement) / 92-05 / 92104380 transistor; the input circuit is connected to the circuit. This control is controlled by the letter standard. The capacitor N 9 200306074 of potential V c C (7 · 5 V) is connected to node N 丨 of output node N 5 and N 6 respectively to output nodes N6 and N5. . The signals appearing in the output form the level converters 3 ν〇, / ν〇 respectively. The N-type TFT7 is connected between the nodes N5 and N7 and the connection point f 1 N 1 1. The N-type τ F T 8 is connected to the node N 6 and its snare pole is connected to the node N 1 3. Nodes n 7 N 8 are respectively numbered VI and its complementary signal / VI. The resistance element 17 and the N-type TFT 9, 10 are connected in series between the node N1 of the electricity and the node of the ground potential GND. The n S pole is connected to its drain (node N 9), and the N-type T F T 1 0 is its drain. The N-type TFTs 9 and 10 respectively constitute a diode element 17 and the N-type TFTs 9 and 10 each constitute a constant potential generating circuit element 17. The resistance 値 is set to be sufficiently large (for example, ι〇μμω). The on-resistance of the TFT 9, 10 is 値. If it is set to be sufficiently smaller than the resistance element 彳, the potential V9 of the node N9 becomes V9 = 2VTN. Refers to the threshold potential of N-type TFT. The N-type TFT 11 is connected between the node N1 of the power source potential VCC, and its gate will receive the potential V 9 of the node N 9. The N-type is connected between the nodes N 1 1 and N 1 2 and its gate is connected to the node. The N-type TFT12 series constitutes a diode element. Capacitor 15 is between Nil and N12. Provide signal / VI to node N12. The N-type TFT 13 is connected between the node N1 of the power source potential VCC, and its gate will receive the potential V9 of the node N9. Type N is connected between nodes N 1 3 and N 1 4 and its gate is connected between section 312 / Invention Specification (Supplement) / 92-05 / 921043 80. The input signals of these nodes N5, N6, The gate is! Between N8, the gate that supplies the input source potential VCC 2 TFT9 is connected to the component, the resistance element. If you connect a resistor and an N-type 丨 new 17 resistor 値, VTN and the node N 1 1 TFT12 are connected to the point Nil. Connected to the node N1 3 TFT14 is connected to point N13. 10 200306074 N-type TF T 1 4 series constitutes a diode element. The capacitor 16 is connected between the nodes N 1 3 and N 1 4. An input signal VI is provided to the node N 1 4. Next, the operation of the level converter 3 will be described. Now, if the input signals VI and / VI are set to 3V and 0V, respectively, the N-type TFT11 will cause the potential V1 1 of the node Ν1 1 to become VI 1 = 2 VTN-VTN = VTN by floating the source. In addition, since the threshold potential of the N-type TFT 12 connected to the diode will be VTN, almost no current flows from the node N 1 to the node N 1 2 of the power supply potential VCC. Because the gate potential of the ν-type T F T 7 is V11 = VTN and its source potential is 3V, the N-type TFT7 will be non-conductive. The capacitor 15 is charged to a threshold voltage V TN. In addition, as described later, since the potential V 1 3 of the node N 1 3 will be boosted to above VTN and the node N 8 will become 0 V, the N-type TFT 8 will be turned on. As a result, the output node N 6 becomes the potential (0 V) of the input node N 8, and the P-type TFT 5 is turned on, and the output node N 5 becomes the power supply potential VCC. As a result, the P-type TFT 6 will be in a non-conducting state, and no current will flow between the node N 1 and the input node N 8 of the power supply potential VCC. Secondly, if the input signal VI is decreased from 3 V to 0 V, and the input signal / VI is increased from 0 V to 3 V, the potential change of the input signal / VI will be transmitted to the node N through the capacitor 15 through capacitive coupling. 1 1, so that the potential V 1 1 of the node N 1 1 is boosted. If the capacitance of the capacitor 15 is sufficiently larger than the capacitance of the parasitic capacitance (not shown) of the node Nil, the potential VII of the node Nil will become VII and VTN + Δ VI = VTN + 3V. Among them, △ VI refers to the amplitude of the input signal VI, / VI, which is 3 V. Because the potential of the source (node N7) of the N-type TFT7 will become 0V, 11 312 / Invention Specification (Supplement) / 92-05 / 92104380 200306074 Therefore, the gate-source voltage of the N-type TF Τ 7 will be ν TN + 3V, and the N-type TFT7 is turned on. As a result, the potential of the output node N5 will be 0V, and the P-type TFT6 will be turned on. In addition, the potential change of the input signal VI from 3 V to 0V will be transmitted to the node ν 1 3 through the capacitor 16 through capacitive coupling, and The potential V13 of the node N 1 3 is stepped down. When the change period of the input signal VI, / VI belongs to a short case, because the potential V 1 3 of the node N 1 3 before step-down will become V 1 3 = VTN + 3 V, so the node n at step-down The potential of 1 3 V 1 3 will become V13 = VTN + 3V-3V = VTN. When the change period of the input signal VI, / VI is relatively long, since the potential V 1 3 of the node N 1 3 will be in a potential state boosted by capacitive coupling, it will decrease with time. Therefore, the potential V13 of the node N13 only decreases when the / VI is shorter than the input signal VI and the period of the VI change is short. In this case, the N-type TFT 1 3 will be turned on, and the node N 1 3 will be turned on. The potential V 1 3 is pulled up to V TN. As described above, because the gate potential V13 of the N-type TFT8 will become VTN, and the source (node N8) potential will become 3V. Therefore, the N-type TFT8 is in a non-conductive state. As a result, the potential of the output node N6 will be 7.5V, and the P-type TFT5 becomes non-conductive. In this case, the output nodes N5 and N6 will be 0V and 7.5V respectively, and a logic level conversion will be performed from 3 V to 7.5 V. In this embodiment, in response to the falling edge of the input signal VI, the threshold voltage VTN of the N-type TFT7 is added to the voltage VTN + 3 V 'after adding the amplitude voltage (3 V) of the input signal / VI to the N Between gate and source of type TFT7, so even if the amplitude voltage (3 V) of the input signal / VI is lower than N type 12 312 / Invention Specification (Supplement) / 92-05 / 92104380 200306074 In this case, the level converter 3 can still operate normally. Therefore, as shown in FIG. 1, the level converter 3 and the liquid crystal display section 4 can be formed into a liquid crystal display device 2 (a TF integrated circuit). Therefore, compared with the conventional technology that requires individually designing the level converter 52 and the liquid crystal display device 53, the number of components can be reduced and the system cost can be reduced. In addition, although a power supply current was excessively flowed in the middle of the operation, a direct current was not flowed except for the resistance element 17 and the N-type TFTs 9 and 10. Since the resistance 7 of the resistance element 17 is set to be large, and only a small current flows, the power consumption of the level converter 3 is extremely small. Furthermore, although T F T 5 to 14 are used in this embodiment, MOS transistors may be used instead of TFTs. In this case, even if the amplitude of the input signal VI, / VI is smaller than the threshold voltage of the MOS transistor, it can still operate. Furthermore, although a TFT belonging to an insulated gate field effect transistor is used in this embodiment, of course, other types of field effect transistor may be used. Hereinafter, various modifications of this embodiment will be described. In the level converter 20 of FIG. 3, the sources of the N-type TFTs 1, 2 and 14 are grounded. In this modification, since the current of the N-type TFTs 12, 14 will not flow into the nodes N1 2, N14, and into the node of the ground potential GND, the driving force of the input signal VI, / VI will become smaller. In the level converter 21 of FIG. 4, a source potential VCC (7.5 V) is given to the sources of the P-type TFTs 5, 6 and a positive power source potential VCC different from the source potential VCC is given to the drain of the N-type TFT 1 1 ', One of the electrodes of the resistive element 17 (the electrode not connected to the node N9) is given a different power supply potential 13 312 / Invention Specification (Supplement) / 92-05 / 92104380 200306074 VCC, VCC' Power supply potential V c C ”. In this variation, for example, it is possible to prevent the noise V9, V11, and V13 of the nodes N9, N11, and N13 from being changed with the noise generated by the power supply potential VCC node. The level converter in FIG. 5 In 22, the resistive element 17 is composed of a P-type TFT23. In other words, the P-type TFT23 is connected between the power source potential VCC at the 9 卩 point N 1 Μ and the n point n 9 ', and its gate is connected to the ground potential The node of gn D. The average unit area resistance of a resistive element composed of TF T is larger than the average unit area resistance of a resistive element composed of a diffusion layer. Therefore, in this variation, the resistance of the resistive element can be reduced. Occupied area In addition, the gate receives the power supply potential V The same effect can also be obtained by the resistance element 17 composed of CC's N-type TF T. In the level converter 24 of Fig. 6, N-type TFTs 25 and 26 are additionally provided. The N-type TF T 2 5 is connected to the node Between N 5 and N 7, the gate is connected to node N 6. The N-type TF T 2 6 is connected between nodes ν 6 and N 8, and its gate is connected to node N5. If the input signal VI, If / VI is at the "Η" level and "L" level, and the input signal ν〇, / ν〇 is at the ΓΗ "level and the" L "level, respectively, the N-type FT25 will be non-conducting. At the same time, the ν-type DFT 2 6 will be turned on, so that the output nodes N5 and N6 are maintained at the "H" level and the "L" level, respectively. If the input signals VI, / VI are at the "L" level and "H" level, and the input signals VO, / VO are at the "L" level and "H" level, respectively, the N-type TFT 2 5 will It is in a conducting state, and at the same time, the ν-type TFT 2 6 will be in a non-conducting state, so that the output nodes N5 and N6 are maintained at the "L" level and the "H" level, respectively. When the change period of the input signal VI, / VI belongs to a very long period, Section 312 / Invention Specification (Supplement) / 92-05 / 921043 80 14 200306074 The potential of the point N 1 1, N 1 3 v 1 1, V 13 will all become the threshold potential VTN of the N-type TFT, and the potential relationship between the output nodes N5 and N6 may be reversed. N-type TFTs 2, 5 and 6 belong to those who prevent such a potential inversion phenomenon between the nodes N5 and N6, and in the case of the potentials V 1 1, V 1 3 of the unrelated nodes N 1 1, N 1 3, The potentials of the nodes N 5, N 6 are fixed. The level converter 27 of FIG. 7 belongs to a node in which the source of the N-type TFTs 2 and 26 of the level converter 24 shown in FIG. 6 is connected to the ground potential GND. In this modification, because the current of the N-type TFTs 2 and 26 does not flow into the input nodes N 7 and N 8 but flows into the node of the ground potential GND, the input signal VI, / VI can be reduced. Driving force. The level converter 3 0 in FIG. 8 belongs to the source of the N-type TFTs 7 and 8 of the level converter 3 shown in FIG. 2, which are all connected to the ground potential GND node. In this modification, since the current of the N-type T F T 7,8 does not flow into the input nodes N7, N8, but flows into the node of the ground potential GND, the driving force of the input signal VI, / VI can be reduced. The level converter 31 of FIG. 9 belongs to the source of the N-type TFTs 7, 8, 2, 5, 26 of the level converter 27 of FIG. 7, and is connected to the ground potential Gnd node. In this variation, because the current of the N-type TFTs 7, 8, 2, 5, and 26 does not flow into the input nodes N7, N8, but flows into the node of the ground potential GND, the input signal VI can be reduced. / VI driving force. The level converter 3 2 in FIG. 10 belongs to the gates of the P-type TFTs 5 and 6 of the level converter 3 shown in FIG. 2 and are connected to the node N5. The P-type TFTs 5 and 6 constitute a current mirror circuit. The same current flows through the P-type TFTs 5 and 6. When the input signal VI, / VI is different from "L i 15 312 / Invention Specification (Supplement) / 92-05 / 921 (M3 80 200306074 level and" Η "level, and N-type TFT7, 8 are turned on respectively In the case of the state and the non-conducting state, the same current as the current flowing in the TFTs 5 and 7 will also flow into the P-type TFT 6 and perform the hole amplification. The output nodes N5 and N6 will be at "L" levels And "Η" level. In this variation, the same amplitude conversion effect as the level converter 3 in Fig. 2 can also be obtained. The level converter 3 3 in Fig. 1 belongs to the level shown in Fig. 6 The gates of P-type TFT5, 6 of converter 2 4 are all connected to node N5. In this variation, the same amplitude conversion effect as that of level converter 2 4 of FIG. 6 can also be obtained. Figure 1 2 The level converters 3 and 4 are those whose sources of the N-type TFTs 7, 8 of the level converter 32 shown in FIG. 10 are grounded. In this modification, the N-type TFTs 7, 8 The flowing current does not flow into the input nodes n 7, N 8 but flows into the node of the ground potential GND, so the driving force of the input signal VI, / VI can be reduced. Figure 1 3 The level converters 3 and 5 are those in which the sources of the N-type TFTs 7, 8, 2, 5, 26 of the level converter 33 shown in FIG. 1 are grounded. In this modification, because the N-type The current flowing through the TFTs 7, 8, 2, 5, 2 6 does not flow into the input nodes N 7, N 8, but flows into the node of the ground potential GND, so the driving force of the input signal VI, / VI can be reduced. In the modified example of FIG. 14, the constant potential generating circuit 36 including the resistance element 17 and the N-type TFTs 9, 10 is provided in common to the complex level converters 3 8, 3 9, .... The constant potential generating circuit 3 6 Between the output node N9 and the node of the ground potential GND, a potential stabilization capacitor 37 is connected. To increase the resistance 値 of the resistance element 17, a resistance element J 7 16 312 / Invention Specification ( (Supplements) / 92-05 / 92104380 200306074 area 'But in this variation, since the constant level generating circuit 36 is commonly provided for the complex level converters 3 8, 39, ..., the overall circuit can be reduced. Occupied area. Level converter 4 in Fig. 15 is added to level converter 3 in Fig. 2. P-type TFTs 41 and 42 are additionally provided. The p-type TFT41 is connected between the drain of the P-type TFT5 and the output node N5, and its gate is connected to the node n 1 1. The P-type TFT42 is connected between the drain of the P-type TFT6 and the output node N6. In the meantime, its gate is connected to node N 1 3. If the input signal / VI rises from 0V to 3 V, the potential of 'node N 1 1 v 1 1 will be V TN + 3 V, making P-type TFT41 appear In the non-conducting state, the n-type TFT 7 is turned on at the same time, and the potential of the output node N 5 becomes OV. Because the p-type τ F T 4 1 is in a non-conducting state 'at this time, the current does not flow from the node N 1 of the power supply potential V C C to the output node N 5, and the potential of the output node N5 is easily reduced to 0V. If the input signal / VI drops from 3 V to 0 V, the potential VI 1 of the node Nl 1 will be VTN, and the N-type TFT7 will be in a non-conducting state. At the same time, the p-type TFT 41 will be turned on, causing the potential of the output node N5 to change It is 7.5V. Furthermore, if the input signal VI rises from 0V to 3 V, the potential V13 of the node N1 3 will be VTN + 3V. The potential becomes 0V. Because the P-type T F T 4 2 is in a non-conducting state at this time, the current does not flow from the node N1 of the power supply potential VCC to the output node N6, and the potential of the output node N6 is easily reduced to 0V. If the input signal vi drops from 3V to 0V, the potential V13 of the node N13 will be VTN, the N-type TFT8 will be in a non-conducting state, and the P-type TFT42 will be turned on, so that the output section 17 312 / Invention Manual (Supplement) / 92-05 / 92104380 200306074 The potential of point N 6 becomes 7.5 V. In this variation, because the potentials of the output nodes N5 and N6 are easily reduced to 0V, the amplitude of the input signal VI, / VI can be reduced by only this part, and the amplitude margin of the input signal VI, / VI can be reduced. Get bigger. The level converters 45 to 55 of Figs. 16 to 26 are those in which P-type TFTs 41 and 42 are added to the level converters 20 to 22, 24, 27, 30 to 35 shown in Figs. 3 to 13, respectively. These variations can also obtain the same effects as the level converter 40 of FIG. 15. All the embodiments disclosed this time are limited to illustrations, and cannot be considered as limiting. The scope of the present invention is not the above description, but is disclosed by the scope of the patent application, and all changes within the meaning and scope equivalent to the scope of the patent application are covered. [Brief Description of the Drawings] FIG. 1 is a block diagram showing a structure of a relevant portion of a mobile phone image display according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a level converter structure shown in FIG. 1. FIG. 3 to 26 are circuit diagrams of modified examples of this embodiment. Fig. 27 is a block diagram of a related part of a conventional mobile phone image display. FIG. 28 is a circuit diagram of the level converter structure shown in FIG. (Description of component symbols)
1 控制用L S I 2 液晶顯示裝置 3 位準轉換器 18 312/發明說明書(補件)/92-05/92104380 200306074 4 液晶顯示部 · 5,6 P 型 TFT 、1 L S I 2 liquid crystal display device for control 3 level converter 18 312 / Instruction Manual (Supplement) / 92-05 / 92104380 200306074 4 Liquid crystal display section 5, 6 P-type TFT,
7 〜14 N 型 TFT 1 5，1 6 電容器 17 電阻元件 20,21，22,24 位準轉換器7 to 14 N-type TFT 1 5, 16 Capacitor 17 Resistive element 20, 21, 22, 24 level converter
23 P 型 TFT 25、26 N 型 TFT ^ 2 7,3 0,3 1,3 2,3 3,3 4 位準轉換器 36 定電位產生電路 37 電容器 4 0 位準轉換器23 P-type TFT 25, 26 N-type TFT ^ 2 7,3 0,3 1,3 2,3 3,3 4 level converter 36 constant potential generating circuit 37 capacitor 40 level converter
4 1,42 P 型 TFT 45〜55 位準轉換器 53 液晶顯示裝置 71 控制用LSI _ 72 位準轉換器 73 液晶顯示裝置 74,7 5 P通道MOS電晶體 76,77 N通道MOS電晶體 GND 接地電位 N1、N5〜N9、N11〜N14 節點 VCC 電源電位 VI，/VI 輸入信號 β 312/發明說明書(補件)/92-05/921043 80 19 200306074 vo，/vo 輸出信號 VTN 臨限電壓4 1,42 P-type TFT 45 to 55 level converter 53 Liquid crystal display device 71 Control LSI _ 72 Level converter 73 Liquid crystal display device 74, 7 5 P-channel MOS transistor 76, 77 N-channel MOS transistor GND Ground potential N1, N5 ~ N9, N11 ~ N14 node VCC power supply potential VI, / VI input signal β 312 / Invention Specification (Supplement) / 92-05 / 921043 80 19 200306074 vo, / vo output signal VTN threshold voltage
312/發明說明書(補件)/92-05/921043 80 20312 / Invention Specification (Supplement) / 92-05 / 921043 80 20