SU813453A1 - Device for integrating peak-like functions - Google Patents

Description

(54) A DEVICE FOR INTEGRATING PICTURE FUNCTIONS of the keys to the blocking input of the following analog-digital converter and connected via a delay element to the second input of the first element I O. The disadvantage of this device is reduced immunity of operation with increased requirements to the accuracy of integration. The purpose of the invention is to improve the noise immunity of the device. The goal is achieved by the fact that, in the device for integrating the peak-like functions, there is a counter connected by a counting input to the output of the first AND element connected by a first input to the output of a code-frequency converter connected by an input to a memory register whose information input connected to the digital output ate the other; An analog-to-digital converter connected by the addition and subtraction outputs to the inputs of an extremum detection unit and connected by an analog input to the device input through the first scaling resistor, as well as through a circuit consisting of the second scale resistor connected in series, moreover, the first output of the extremum detection unit is connected to the control input of the memory register, the second, third and fourth And elements and three flip-flops are additionally introduced, the first output of the block being defined and extrema connected by the second output to the first input of the second element And connected to the first input of the first trigger connected to the output of the second input of the first element And to the second input of the second element And, the stroke of which is connected to the second input of the first trigger, the first input of the second trigger and inputs for zeroing the counter and the memory register connected by the output to the digital input of the following analog-digital converter connected by the addition and subtraction outputs respectively to the third input of the second element And and The third input of the third element And connected by the output to the first input of the third trigger and the second Bxofiy of the second trigger, the output of which is connected to the third input of the first element And and to the first input of the fourth element And connected by the second input to the third output of the extremum determination unit and connected to the output the second input of the third trigger, and the output of the third trigger is connected to the blocking input of the following analog-digital converter, the control input of the control key and the second input of the third element I. Krom This extremum detection unit contains AND elements, a pulse shaper and a reversible counter, the inputs of the first and second AND elements connected by the first inputs to the inputs of the extremum determination unit are connected to the inputs of the reversible counter, the zero outputs of the bits of which are connected to the inputs of the third And element connected inverse output to the second input of the first element I and connected by a direct output to the second output of the extremum detection unit and to the first input of the fourth element I, whose output connected to the first output of the extremum detection unit, and the second input of the fourth element I is connected to the output of the second element I connected to the inverse output of the fifth element I connected to the outputs of the corresponding bits of the reversible counter and connected to the direct output through the pulse shaper to the third output of the block determining extrema. Fig. 1 shows a block diagram of a device for integrating peaked functions; 2 shows a block diagram of an extremum detection unit. The device for integrating the peak-like functions contains the following analog-to-digital converter, 1, extremum detection unit 2, memory register 3, code-frequency converter 4, counter 5, first, second and third triggers 6-8, first, second, third and the fourth element 9-12, the first and second scaling resistors 13 and 14, the control key 15. The extremum detection unit 2 comprises the first, second, third, fourth and fifth elements And 16-20, a reversible counter 21 and a pulse shaper 22. Analog input follow analog-digital transducer .1 is connected to the input of the device through a resistor 13 and through a circuit consisting of a series-connected control switch 15 and a resistor 14. The addition and subtraction outputs of the converter .1 are connected to the inputs of the extremum determination unit 2. The first output 23 connects to the trigger input 6 and the control input of the register 3, the second output 24 - with the first input of the element And 10, and the third output 25 - with the second input of the element And 12 connected by the first input to the output of the trigger 7 and the third lead of the element 9. The folding order and read and converter 1, connected by a digital output to information input of register 3, is also connected respectively to the third input of element 10 and the first input of element 11. The output of trigger b is connected to the second input of element 10 connected to the second input of trigger b, first the trigger input 7 and the zero reset inputs 3 and counter 5; The output of the register 3 is connected to the digital input of the converter 1 and the input of the code-frequency converter 4 connected by an output to the first input of an element AND 9 connected by a second input to the output of trigger b and connected by an output to the counting input of counter 5. The second input of trigger 7 is connected to the output of the element And 11 and the first input of the trigger 8, the output of the trigger 8, connected by a second input to the output of the element 12, is connected to the blocking input of the converter 1, controlling the input of the switch 15 and the second input of the element 11. In the block for determining the extrema of the output And the rows of elements 16 and 17 are connected to inputs of the down counter 21 (corresponding to its subtrahend and summing inputs). The second input of the element AND 16 is connected to the inverse output of the element AND 18 connected by inputs to the zero outputs of the bits of the counter 21. The inputs of the element 20 are connected to the outputs of those bits of the counter 21, which correspond to the number of receiving at the binary representation of the ratio, where Nn is the nearest integer number, rounded up; cJroaif is the maximum interference level acting on the input signal of the integrator; U - quantization step by the level of the following converter The inverse output of the And 20 element is connected to the second input of the And 17 element connected by the output to the second input of the And 19 element. The output of the And 19 element connected by the first input to the direct output of the And 18 element The first output 23 of block 2. The direct output of element AND 18 is connected to the second output 24 of block 2, the third output 25 of which is the output of the former 22 connected to the direct output of element AND 20. The first inputs of element And 16 and 17 are connected to the inputs of the block 2. The pulse shaper 22 s ops output pulse only at the moment of transfer capacity is directly output from the AND gate 20 low uro n in a high level. Consider the principle of action of the block of determination of extrema 2, At the initial moment, when the counter 21 is reset, on the second output 24 of block 2 - high potential, element 16 - is closed by a signal from the inverse output to elements 18, and element 17 is open by a signal with i) the output of the element And 20. Therefore, when the input signal increases, the pulses coming through the addition bus of the converter to the input of block 2 to the first input of the element 16 do not pass through this element I 16. When the function reaches an extremum, the pulses appearing on the subtraction bus converted Atel 1 received via the other input of the unit 2 (first input of AND gate 17 open) to a summing 21.Pervy counter input of the same impulses through the AND gate 19 will be held at the first yield 23 unit 2, which is a feature of the extremum. The same pulse, changing the state of the counter 21 and, accordingly, the state of the element And 18, removes the high potential from the second output 24 of the block 2 and opens the element And 16. If the recorded extremum is a consequence of interference, then the signal at the input of the device decreases by some value relative to the value of the extremum, and this deviation is less than the permissible level of interference (Gtoh-Ya summing input of counter 21, respectively, a signal is received less than Nn pulses, so the element And 20 does not change its state. After The input signal increases again and the pulses from the addition bus of conversion 1 are fed to the subtracting input of counter 21. When the input signal reaches a level corresponding to the time before the interference, the number of pulses received at counter 21 through AND 17 is comparable to the number of pulses which were subtracted from the contents of the counter 21, the passage through the element AND 16, i.e. the contents of the counter 21 will become zero. Therefore, a high potential appears again at the output 24 of unit 2, and element 16 is closed. Thus, block 2 responds to interference on the left-hand side of the peak. When the input function reaches the true maximum, all of the switchings discussed above will occur, however, the input signal after the extremum will decrease by an amount greater than the permissible interference level. The consequence of this will be the accumulation in the counter of 21 numbers of impulses equal to NH. At this point in time, an element 20 is triggered. A shaper 22 connected to the forward output of an element 20 will form at the third output 25 of unit 2

the output pulse, and the signal from the inverse output of the elements And 20 closes the element AND 17 dL of the pulses from the subtraction bus of converter 1. If the signal starts on the right side of the true peak of the input peak, the signal starts to increase due to the interference, then the pulses Converter 1 to the subtracting input of counter 21 will not make the contents of counter 21 equal to zero, since the maximum level of interference code has been accumulated in the counter before. The first of the pulses passing through the addition bus of the converter. .1 through AND 17 to the subtracting input of counter 21 changes the state of this counter and removes the prohibition from AND 17, but the output driver 22 does not produce an output. With subsequent changes in the input signal, the switching process of the block 2 occurs in the same way as described above.

The device works as follows.

In the initial state, transducer 1 operates in the following mode. Counter 21 of block 2, register 3 and c. Counter 5 reset. Triggers 6-8 are also in the zero state. (Circuit set to zero in the drawing is not shown) 4 At the second output 24 of block 2 high potential. The analog input of the converter 1 receives the input signal under study. At the digital output of converter 1, the current code value of this signal is generated. When the input signal increases, the pulses traveling along the addition bus of converter 1 do not generate any signals in block 2 and do not pass through AND 10, as it is closed by a low potential from the single output of trigger 6. When the input signal reaches an extremum, the first the pulse that appeared on the subtraction bus of the converter 1 produces a low potential at the output 24 of block 2, and the pulse of reaching an extremum at the output 23 of block 2. This pulse rewrites, the contents of the counter, which is part of converter 1, in register 3, throws 6 into one position. Extremum impulse through the element. And 11 does not pass, since low potential is supplied from the one output of the trigger 8. Pulses with a frequency proportional to the binary code in register 3, through element 9, which is open for code-frequency converter 4 pulses since flip-flop trigger 6, are accumulated in counter 5.

If the detected extremum is due to interference, then the input signal decreases by some amount less than the allowed value.

the level of interference (then increases. During this period, the pulses on the subtraction and addition bus of converter 1 at the outputs of block 2 do not generate any signals. When the input signal is equal to the value of the detected and detected extremum, a high level of potential is generated at output 24 of block 2). Therefore, the next pulse after this moment on the addition bus of converter 1 through AND 10 sets the register 3 to zero, counter 5 and trigger 6, which will block element 10. The trigger 7 does not change its since it was in the zero position before that.To reliably clean the counter 5, it is possible to include a delay element at its zero-setting input, with a delay equal to the flip-flop time of trigger 6 (not shown).

When the DX input signal reaches its true peak value, all of the switches that occurred during the fixing of the extremum interference will occur in the device. Further, the pulses of the converter subtraction bus 1 accumulate in the reversible counter 21 of block 2 as the input signal decreases. When the input signal passes through a possible noise level, a pulse is generated at the output 25 of unit 2. This impulse throws the 8th trigger. unit position (FIG. 2). As a result, the control key 15 closes, zooms in the input signal, blocks the addition bus of converter 1 and overwrites the recorded extremum value from register 3 into the counter of converter 1 on its digital input. The first input of block 2 is connected to the addition bus of converter 1 after the blocking input, therefore no pulses are sent to the first input of block 2. The reason for rewriting the detected extremum from register 3 to the counter of converter 1 is that when analyzing the detected extremum, the contents of the counter of converter 1 are reduced by the value of N p.

The peak area is determined according to

S fU; j; A. , Г-,, t) dt KAT, where K Const is a constant coefficient depending on the form of the function Ux;

extreme (maximum)

And peak; G is the width of the peak, at some predetermined level of the nA peak; n const -1 is a constant factor The scale of the input signal and, is changed in such a way that the predetermined ordinate pA, with which the rescale function DX -j is compared, will be at the level of the previously recorded maximum. The contents of the counter 5, which accumulates pulses. the moment of extremum, up to the moment of comparison with a predetermined ordinate, will be equal to the area bounded by the input function of the CX axis of the abscissa, with a quantum frequency equal to a constant coefficient K, for example, if it is known in advance, h then the peaks are described by Gaussian functions, then at that, 456,.

The first pulse on the subtraction bus of the converter 1, which appears when DX is compared with the fixed value of the extremum, the passage through element 11, arrives at the second input of the trigger 7, as a result of which the trigger 7 moves and bans. element AND 9. The arrival of pulses from the 4 code-frequency converter in the counter 5 is stopped and the peak area is fixed in the counter. At the same time, the impulse from the output of the element 11 moves to the zero state the trigger 8, which opens the control key 15 and removes the blocking from the addition bus A of the converter -1, i.e. switches parago to the pulse mode; the impulse from the output of the element 11 and so is fed to devices for further processing of information (memory or printer, digital computers, etc.).

Upon further decrease of Ux, pulses on the subtraction bus of converter 1 at the outputs of block 2 do not produce a signal, and besides the above first pulse, other pulses do not pass through element 11. If a peak appears due to interference, then pulses coming through the bus The additions to the input of block 2 do not produce signals at its outputs, since on the reversible counter 21 of block 2, since the moment of determining the true extremum, the Mfi code is stored from which these pulses are subtracted. Therefore, the wider subtraction pulses appearing after the false extremum do not produce an extremum signal at the output 23 of block 2. The device responds in this way to all false peaks on the right-hand side of the true extremum.

With a subsequent increase in the function and k, after reaching the baseline (zero line), further work repeats the entire described output.

The use of the device increases the accuracy of determining the peak area by increasing the size of the device, since in this case a false positive is prevented due to an increase in noise immunity.

Claims (3)

1. A device for integrating peak functions comprising a counter connected by a counting input to the output of the first element I connected by a first input to a code-frequency converter output connected by an input to the output of a memory register whose information input is connected to a digital output of a following analog-digital converter connected by the outputs of addition and subtraction to the inputs of the extremum determination unit and connected a; the tax input to the input of the device through the first scaling resistor, as well as a circuit consisting of the second scale resistor connected in series and a control key, the first output of the extremum detection unit being connected to the control input of the pitch register, which is so that, in order to improve the noise immunity of the device , the second, third, and fourth elements I and three triggers are additionally introduced into it, with the first output of the extremum detection unit connected by the second output to the first input of the second element AND connected to the first input of the first trigger connected home to the second input of the first element I- and to the second input of the second element I, the output of which is connected to the second input of the first trigger, the first input of the second trigger and the zeroing inputs of the counter and memory register j connected by the output to the digital input of the following analog-digital converter, connected by the outputs of addition and subtraction, respectively with the third input of the second element AND the first input of the third element I, connecting the cell output to the first input of the third trigger and the second input of the second trigger, the output of which is connected to the third input of the first element I and to the first input of the fourth element I connected to the second input to the third output of the block determining extrema and connected with the output to the input of the third trigger, and the output of the third trigger is connected to the blocking input of the following angio-digital converter, the control input of the control key and the second input of the third element I. 2. A device according to Claim 1, characterized in that the extremum determination unit contains AND elements, a pulse shaper and a reversible counter, the outputs of the first and second AND elements connected to the inputs of the extremums are connected to the inputs reversible counter zero outputs of bits of which are connected to the inputs of the third And element connected by an inverted output to the second input of the first And element and connected by a direct output to the second output of the extremum determination unit and to the first input the fourth element I / output of which is connected to the first output of the extremum detection unit, and the second input of the fourth element I is connected to the output of the second element I connected to the second input to the inverse output of the fifth element I connected to the inputs of the outputs of the corresponding bits of the reversible counter and connected by a direct output through the pulse shaper to the third output of the block for determining extremes. Sources of information taken into account in the examination 1 .. US Patent No. 3801806, cl. 235-183, 1974. 2. USSR author's certificate for application number 2592433 / 18-24, 0 cl. G 06 G 7/18, 03/20/78. 3. USSR author's certificate number 601703, cl. G About G 7/18, 1976 (prototype). .