SU803109A1 - Telegraphic unipolar signal receiver input device - Google Patents

Description

(54) DEVICE FOR ASYNCHRONOUS DIGITAL INFORMATION TRANSMISSION ON SYNCHRONOUS CHANNEL

COMMUNICATIONS

the home of the registration unit, the input of the first delay line is the second input of the registration unit, and the inhibitory inputs of the first and second NO elements are respectively the fourth and third inputs of the registration unit.

The drawing shows a structural electrical circuit of the proposed device.

The device contains a phase discriminator 1, a controlled divider 2, a master oscillator 3, a recording unit 4 consisting of the first delay line 5, the first element NO 6, the second delay line 7, the second element NO 8, the reading unit 9, the analyzer 10 double gating, AND trigger, AND elements 12, 13, selection block 14, alternating.

The device works as follows.

When the phase of the pulses of the recording frequency fp generated by the divider 2 is mismatched, a lag or advance signal is sent from the first or second output of the discriminator 1, which sets trigger 11 to the state "1 or" O. Simultaneously, with the moment of setting the trigger 11 into one or another state from the output of the analyzer 10 and from the output of block 14. Signals are sent to the second and third inputs of the And 12, 13 elements. If trigger 11 was set to the state "1, then to the block 4, the signal from the output of the first element 12 is supplied, if it has been set to the state "O", then the signal from the output of the second element 13 is fed to block 4.

The lag or advance signals are sent by the discriminator 1 when one of the following four combinations of the binary code is received from the communication channel with the frequency Hk: 0010, 1101 or. 0100, 1011, and in these combinations, the reception of the second and third characters, in combination representing the alternating sign (01 or 10), is performed in one period of the recording frequency fp, due to the fact that the frequency f exceeds the frequency fp so that

,

Receiving alternations for one period of the frequency fp can also be made when the following two binary code combinations are sent from the communication channel: OOP, 1100.

If the reception of the received signal is performed by gating, then out of two alternating signs, received during one period of frequency fp, an incorrect one (repeated, duplicating, previously registered sign or sign to be registered in the next frequency fp) may be registered, as a result of which at the output of block 4, an error is recorded in the received information.

In the proposed device, one or another sign in the alternating sign is registered in

depending on the fixed direction of the mismatch, i.e., depending on the state in which trigger 11 is. So, if trigger 11 was set to state "1, of the two opposite characters received in one frequency period fp, the second, and if trigger 11 was set to the state "Oh, then the first sign of the change sign. This is achieved as follows. In the case of reception for one cycle frequency fp dissimilar

characters to the third inputs of the elements 12, 13 are given a signal from block 14, and to the second inputs is a signal from the analyzer W, indicating that two pulses of frequency lf have occurred (during one period of the frequency fp. If the frequency pulses fp are out of phase with the frequency pulses fpep entering information into the asynchronous interface device (UAS) on the transmission, then the trigger 11 will be set to the position "1, and when receiving for the same period the frequency fp of opposite characters 0, a signal is output from the output of the first element I 12, which arrives at the element NO 8, prohibits writing to node 9 of the first ( on arrival time) of the mark of this sign changes. If the frequency fp pulses ahead in phase pulses of frequency 1, then

 the trigger 11 will be set to the "O" position, and the signal from the output of the element 13 will prohibit the recording on line 7 of the second (by arrival time) sign from the alternating sign.

5 The delay value of line 7 is equal to the duration of one period of frequency f. Line 5 aligns in time the moment of arrival of the signal from the output of element I 13 with the moment of arrival of the second character of the analyzed alternating sign from the communication channel.

5 The value of this delay does not exceed the duration of two to four periods of frequency f.

A sequence of characters, in which some duplicate characters of the transmitted information are eliminated with the help of NO elements, is recorded in node 9, from where it is read by pulses of the clock frequency f.

With p1 Ro 1/2, the probability of the occurrence of a fault at the output of block 4 of the proposed device when receiving alternating sign for one period of the frequency fp during the phasing process is equal to

.

where p is the error in error. communication channel;

q 1 - If there are no errors in the communication channel, i.e., when p 0, there are no devices at the output of block 4 ().

If there is a fault in the communication channel, 5 when p t o,

Rosh r -z / e - /);

), Ro (- /) p,

Claims (2)

Claim 1. A device for asynchronously transmitting digital information over a synchronous communication channel, containing a phase discriminator, the first and second outputs of which are connected via a controlled divider to the first input of the recording unit and to the input of the double gating analyzer, the output of which is connected to the first input of the phase discriminator, the output of the master oscillator connected to another input of the controlled divider, and the second input of the phase discriminator is connected to the second input of the registration unit, characterized in that, in order to increase In order to transfer the signal, a trigger, AND elements, and an alternating isolation block are introduced, while the first and second outputs of the phase discriminator are connected via a trigger to the first inputs of the first and second I elements, 5 outputs of which are connected to the third and fourth inputs of the recording unit, the output of the double gating analyzer connected to the second inputs of the elements And, and the second input of the phase discriminator through the selection block alternating sign is connected to the third inputs of the elements I. 2. The device according to π. 1, characterized in that the registration unit comprises a first delay line, a first NO element, a second delay line, a second NO element and a readout unit connected in series, the readout input of the readout unit being the first input of the registration unit, the input of the first delay line being the second input block registration, and prohibiting inputs of the first and second elements NO are respectively the fourth and third inputs of the registration block.