SU736177A1

SU736177A1 - Self-checking storage

Info

Publication number: SU736177A1
Application number: SU772541249A
Authority: SU
Inventors: Лариса Николаевна Бандуровская; Красимир Георгиевич Вълков (Нрб); Александр Васильевич Городний; Виктор Иванович Корнейчук; Елена Николаевна Сосновчик; Владислав Владимирович Шведов
Priority date: 1977-11-09
Filing date: 1977-11-09
Publication date: 1980-05-25

Description

1one

Изобретение относитс к запоминающим устройствам.This invention relates to memory devices.

Известно запоминающее устройство с само .контролем, содержащее накопитель, регистры адреса и слова, блок управлени , блок контрол 1.A memory device with self control is known, containing a drive, address registers and words, a control unit, a control unit 1.

Недостатком зтого устройства вл ютс большие аппаратурные затраты.The disadvantage of this device is high hardware costs.

Наиболее близким техническим решением к изобретению вл етс запоминающее устройство с самоконтролем, содержащее накопитель , подключенный к регистру адреса и ретистру слова, соединенному с блоком контрол и блоком кодировани , блок управлени , блок декодировани 2. Однако реализаци корректирующих кодов, исправл ющих многократные ошибки, требует значительной избыточности пам ти, т.е. числа дополнительных разр дов дп исправлени ошибок и больших аппаратурных затрат на блоки кодирювани и декодировани , что снижает надежность устройства.The closest technical solution to the invention is a self-monitoring memory device containing a drive connected to an address register and a word reistor connected to a control unit and a coding unit, a control unit, a decoding unit 2. However, the implementation of correction codes correcting multiple errors requires significant memory redundancy, i.e. the number of additional bits dp error correction and high hardware costs for blocks of encoding and decoding, which reduces the reliability of the device.

Если подавл ющее большинство ошибок вызвано отказами типа генератор О и генератор 1, то коррекци ошибок может бытьIf the overwhelming majority of errors are caused by O and O type 1 failures, then error correction can be

осуществлена с меньшей избыточностью накопител .implemented with less redundancy drive.

Целью изобретени вл етс повышение надежности устройства при корре.кции многократных ошибок.The aim of the invention is to improve the reliability of the device during correction of multiple errors.

Достигаетс это тем, что запоминающее устройство содержит регистр сдвига, элементы И, коммутатор и последовательно соединенные дополнительные накопители, вход одного из которых соединен с выходом регистра This is achieved by the fact that the memory device contains the shift register, the elements of AND, the switch and the series-connected additional drives, the input of one of which is connected to the output of the register

10 адреса, выход другого дополнительного накопител подключен к первому входу коммутатора , вход регистра сдвига соединен с выходом блока управлени а - с вторым входом коммутатора, выход которого подклю15 чен к одному из входов регистра слова, входБ элементов И соединены с выходами регистра слова, а выходы - с выходами устройства.10 addresses, the output of another additional accumulator is connected to the first input of the switch, the input of the shift register is connected to the output of the control unit a with the second input of the switch, the output of which is connected to one of the inputs of the word register, inputB of the elements AND, connected to the outputs of the word register, and outputs - with device outputs.

На чертеже изображена блок-схема предлагаемого устройства.The drawing shows a block diagram of the proposed device.

2020

Claims

The device contains the address register 1 with inputs 2, drive 3 with inputs 4 and outputs 5, serially connected additional drives 6 and 7, having INPUTS 8 and 9, respectively, switch 10, P-bit shift register 11, reg word 12, a coding unit 13 having an input 14, AND elements 15, the outputs of which are connected to the outputs 16 of the device, the control unit 17 and the control unit 18. The input 8 of the accumulator 6 is connected to the output of the register 1, the output of the accumulator 7 is connected to the first input of the switch 10. The input of the register And connected to the entrance of block 18, and the output - from the second an input switch 10, which is connected to one of the inputs of the register 12. The inputs of AND gates 15 with compounds vEhodami register 12, memory device operates as follows. The inputs 2 of the register of address 1 are supplied with the address of the cell to which the nexus can be accessed. In the check mode of the accumulator 3, for example, using special programs, the control codes of the switch 0 are determined, which are recorded in the additional accumulator 7, and their address in the accumulator is fixed in the additional drive 6, and for each i cell of the drive 3 there is a corresponding cell of the additional drive 6. When referring to the drive 3, the contents of the corresponding cell of the additional drive 6 are selected, which is the address of the address to the additional puncher 7, the control code of the switch 10 connects the corresponding outputs of register 11 to the register bits of word 12 in accordance with the control code of switch 10. On the numeric channel, the word read from accumulator 3 is sent to the control unit 17, which detects a P + I failure, raises the corresponding outputs of control unit 18. If an error is detected, the control unit 18 drives the corresponding signals to AND elements 15 and the information word is read into the outputs 16. Otherwise, the corresponding outputs of block 17, which are analyzed by control block 1-8 and enable the serial connection of 1 register 11 to the counting inputs, of those bits of the register 1: a word 12, which are indicated by the control code of the switch 10, are refused as bits, B If changing the contents of the next bit to the opposite decreases the number of excited outputs of block 17 (bus fails indication) 4 when checking the contents of word register 12, the control unit 18 Schedules the connection the next time and register 1 to the register 12. The words otherwise restored original value of this bit in the word register 12, and only then is a connection following 1; th discharge. After sequentially connecting all the bits indicated by the control code of switch 10, the result of checking the contents of the register of word 12 to be negative (i.e., there are no excited outputs of block 17). If there are excited outputs of block 17, then new Failures have appeared in the test mode of accumulator 3 and the reading cannot be continued. Thus, the device can correct P + 1 failures. The described memory device allows increasing the effective memory capacity and increasing the reliability of the device when correcting multiple errors. Claims of the invention A self-monitoring storage device comprising a storage device connected to an address reg-raster and a word register connected to a control unit and a coding unit, and a control unit different; topics that, in order to increase the reliability of the device, it contains a shift register, AND elements, a switch and additional drives connected in series, the input of one of which is connected to the output of the address register, the output of another additional drive is connected to the first input of the switch, the shift register input is connected to the output of the block control, and the output - with the second input of the switch, the output of which is connected to one of the inputs of the S. Yuva register, the inputs of the AND elements are connected to the outputs of the word register, and the outputs - to the device outputs. Sources of information taken into account in the examination 1. UK Patent No. 1158010, cl. 0-4 C, 1969.

2. Hetaguroz Ya. A., Rudnev Yu. P. Improving the reliability of digital devices using redundant coding methods. M., Energia 1974, p. 224-229 (prototype).