SU1764053A1 - Multichannel device for current claim servicing control - Google Patents

Abstract

The invention relates to computing and can be used to manage the order of service for subscribers in the order in which their requests arrive. The purpose of the invention is to reduce the amount of equipment and increase the reliability of operation. The device contains channels 1, and in each channel - triggers 2, 7, elements OR-NOT 3 and 6, register 4, comparison circuit 5. In addition, the device contains elements OR 8, 9, delays 10, 15, OR-NOT 12, and 14, counters 11, 13. The device performs service requests in the order of arrival by writing their codes from the outputs of counter 11 to registers 4 and comparing the contents of these registers with the code from counter 13 1 or

Description

The invention relates to computer technology and can be used to control the sequence of customer service in the order of receipt of their requests.

A multi-channel device for servicing requests in the order of arrival is known, which contains channels that include NOT, AND elements, pulse shapers, memory cells, comparison circuits, and the general control circuits include a pulse distributor, delay element, first and second counters, and end sensors maintenance (ed. St. No. 817715).

The disadvantage of this device is the inability to service simultaneously received requests.

There is also known a device for servicing applications in the order of receipt, containing two groups of triggers, four groups of AND elements, a group of counters, five OR elements, a group of comparison circuits, a trigger, two AND elements, an NOT element, a pulse generator, a delay element, and a reverse counter (automatic St. No 1434436).

The disadvantage of this device is the large amount of equipment and the low reliability of operation with the simultaneous receipt of interrogation signals, since in this case it is possible to form a service signal on its several information outputs.

Closest to the invention in technical essence is a multichannel device for managing service of applications in the order of receipt, containing an OR element, an AND element, a delay element, an OR-HE element, first and second counters, an end-of-service sensor, and four triggers in each channel, two elements And, a memory cell and a comparison circuit (ed. St. No. 1456956).

The principle of operation of this device is based on servicing applications in the order they are received by writing subscriber numbers stored in the first counter to memory cells and comparing the output signals of the memory cells with data stored in the second counter. When several requests are received simultaneously, customer service is performed in the order of their priority.

A disadvantage of the known device is the large amount of equipment.

The purpose of the invention is to reduce the volume of equipment and increase the reliability of the operation of the device.

This goal is achieved by the fact that the second OR element and the second delay element are introduced into the device for managing the service of requests in the order of receipt, and the ORINE element is introduced into each channel. the output of which is connected to the input of the register entry of its channel and to the input of the second OR element, the output of which is connected to the input of the second delay element, the output of which is connected to the clock input of the first counter and the first inputs of the elements OR-NOT channels whose second inputs are connected to the inverse outputs of the second triggers of its channels, the output of the comparison circuit of the Mth channel (M = 1, K-1) is connected to the (M + 1) -th inverse input of the element And the channels from (M + 1) -th to the Kth and the corresponding input of the first element OR, the clock input of the second counter is connected to the output ohm of the OR-HE element, the first input of which is connected to the output of the first OR element, the second input of the AND element is connected to the second input of the OR-NOT element, the reset inputs of the first channel triggers and is the input to the end of service of the device. the clock inputs of the first triggers are connected to the output of the first delay element, the output of the And element of each channel is connected to the information input of the first trigger of its channel.

The invention allows to reduce equipment due to the exclusion of two triggers from each channel and to increase the reliability of operation due to the prevention of violations of the sequence of service of incoming requests

The drawing shows a structural diagram of the proposed device.

The device contains channels 1, and in each channel, a second trigger 2, OR-NOT 3 elements, register 4, comparison circuit 5, AND element 6, and the first trigger 7. In common control circuits, the device contains OR elements 8 and 9, the second element delays 10, the first counter 11, the element OR NOT 12. the second counter 13, the element And 14, the first delay element 15 and the input 16 of the end of the service device. The device also has request inputs 17 and outputs 18.

The device operates as follows. In the initial state, a single signal acts at the input 16 of the end of the service, zero signals are present at all other inputs and outputs of the device, and all memory elements are reset.

Service requests could arrive at the request inputs of the device 17 at random times. Suppose that simultaneously at the inputs of the device 17, except for the first one, request signals were received in the form of a signal of logical 1. Then the triggers of 2 jscex channels, except for the first one, are switched to the single state along the rising edge of the request signals. As a result, at the second inputs of the corresponding OR-NOT 3 elements, a single signal is replaced at zero and a single signal is formed at their outputs. The leading edge of this signal in the register 4 of each channel, except the first, is entered in the contents of the counter 11 (in this case, all 0). In addition, a single signal from the outputs of the OR-NOT 3 element through the OR element 9 triggers a delay element 10. In the last digit of the indicated registers 4 “1” is entered, as a result of which a single signal is generated at the outputs of these discharges. This single signal sets the corresponding trigger 2 to the zero state, after which at its outputs the zero signal is changed to the single one and the signal is removed from the output of the corresponding OR-NOT 3 element. At the same time, after some time necessary for transients in the registers 4, an ’T’ appears at the output of the delay element 10, which blocks the operation of the AND-NOT 3 elements at the first inputs, and 1 is added to the contents of the counter 11.

After writing to the registers 4 of the above channels the code 00 ... 0 from the output of the counter 11 and the logical 1 ”in their last digit, the code 100 ... 0 from the outputs of these registers goes to the first group of inputs of the corresponding comparison circuits 5, to the second group of inputs (except for the last input) the code 00 ... 0 is received from the outputs of the counter 13. At the last input of the second group of inputs of the indicated comparison circuits 5, a unit level is supplied from the bus of the logical unit of the device. As a result, at the outputs of the comparison circuits 5, in addition to the comparison circuit 5 of the first channel, a single signal is generated, which is fed to the first input of the corresponding element And 6, to the corresponding input of the element OR 8 and to the inverse inputs of the elements And 6. of the subsequent channels. Thus, all the And 6 elements, except for one (in this case, the And 6 element of the second channel), will be blocked. A single signal will be generated at the output of the And 6 element of the second channel, and after a while, necessary for the end of transient processes in the respective comparison circuits 5 and And 6 elements, a single signal will appear at the output of the delay element 15. On the leading edge of this signal, the trigger 7 of the second channel will switch to a single state. A single signal from the output of this trigger goes to the corresponding output 18 of the device for servicing the second subscriber. At the same time, a single signal from the output of the specified trigger 7 goes to the zero input of the register 4 of the second channel and resets it to its original state. At the output of the last bit of this register, a single signal changes to zero, and thus, this channel is ready to receive the next request, and at the output of the second channel comparison circuit 5, a single signal changes to zero, as a result of which the block from this channel is removed from the inverse inputs of the elements And 6 subsequent unattended channels. At the output of element And 6 of the servicingambgo of the second channel, a single signal is changed to zero, and at the output of element And 6 of the subsequent third channel, a single signal appears. However, this will not lead to the triggering of trigger 7 of this channel, since at this time there is no change in the control signal at its C-input. At the beginning of the service, a single signal from the input 16 of the end of the service is changed to zero, which blocks the And 14 element at the second input and resets the trigger 7 of the second channel to the zero state.

At the end of service of the second channel at the input 16 of the end again appears a single signal. The blocking from the second input of the element 14 14 and the R-inputs of the triggers 7 is removed. As a result, at the output of the AND element 14, a single signal is again formed, which triggers the delay element 15. The leading edge of the single signal; formed at the output of the delay element, 15, the trigger 7 of the third channel will be set to a single state. A single signal from the output of the trigger 7 of this channel is supplied to the corresponding output 18 of the device for servicing the third subscriber. In the future, the operation of the device will proceed as described above.

If, after receiving and servicing the above requests, the first request for input 17 of the device received a service request from the first subscriber, then it will only be serviced after servicing previously received requests. In this case, the leading edge of a single signal formed at the output of the OR-NOT 3 element of the first channel will rewrite the code 00 ... 01 from the outputs of the counter 11 to register 4 of this channel, the last bit of which will be written 1 ”. Moreover, the comparison circuit 5 of the first channel does not work, since its second group of inputs will contain the code 00 ... 00 from the outputs of the second counter 13 .. The next code of the queue 00 ... 10 will be written to the first counter 11. The zero code on the second counter 13 will be stored until a single signal is output to the last output 18 of the device, which allows servicing the last K-th subscriber. Thus, in the case under consideration, only after servicing all previously received requests, the device can proceed to servicing the request received later from the first subscriber. It happens as follows. At the beginning of the service of the Kth subscriber, zero signals will be present at all inputs of the OR 8 element, as a result of which a single signal is changed to zero at its output. This signal will remove the lock from the first input of the OR-NOT 12 element and block the And 14 element at the first input. Then, at the input 16 of the end of service, the single signal is changed to zero, which will reset the trigger of channel 7 and will ensure the formation of the output of the OR-NOT element 12 single signals. The latter will set 00 ... 01 in counter 13 with its leading edge, which will correspond to the queue code formed from the request signal of the first subscriber and stored in register 4 of the first channel. After that, the comparison circuit 5 of the first channel is triggered and a single signal is generated at its output, which, through the And 16 element of the first channel, prepares the trigger 7 of this channel for the information input. In addition, this single signal through the OR element 8 blocks the passage of the single signal through the OR-NOT 12 element and prepares the operation of the And 14 element at the first input. At the end of the service of the Kth subscriber, a single signal appears at the input 16 of the device, as a result of which the element is triggered Delay 15, a single signal is recorded in the trigger 7 of the first channel. In the future, the first subscriber will be serviced similarly to that described above. At the end of the service of this subscriber, the code 00 ... 10 is written to the second counter 13, which will correspond to the next request or group of requests received at inputs 17 during the processing of the first request.

Thus, the proposed device, having a smaller amount of equipment, provides higher reliability of operation by avoiding violations of the sequence of servicing requests. Using the proposed device can reduce the amount of equipment by eliminating two triggers from each channel.

Claims (1)

Claim A multichannel device for managing the service of applications in the order of arrival, containing the first OR element, the first and second counters, the OR-NOT element, the I element, the first delay element and K channels (K is the number of request sources), and in each channel, the And element, first and second triggers, register and comparison scheme. moreover, in each channel, the group of information inputs of the register is connected to the group of outputs of the first counter, the group of outputs of the channel register is connected to the first group of inputs of the circuit for comparing its channel, the second group of inputs of which, in addition to the last input, is connected to the group of outputs of the second counter, the output of the first OR element is connected with the first input of the And element, the output of which is connected to the input of the first delay element, the input of the end of the service of the device is connected to the reset inputs of the first channel triggers, the first inputs of the And the signals are connected to the outputs of the circuits for comparing their channels, the last inputs of the second groups of inputs of which and the information inputs of all registers are connected to the bus of the logical unit of the device, the request inputs of which are connected to the clock input of the second triggers of the channels, the output of the first trigger of each channel is the output of the device and connected to the reset input register of its channel, the last discharge of which is connected to the reset input of the second trigger of this channel, characterized in that, in order to reduce the amount of equipment and To increase the reliability of the operation of the device, the second OR element and the second delay element are introduced into it, and the ORINE element is inserted into each channel, the output of which is connected to the input of the channel register entry and to the input of the second OR element, the output of which is connected to the input of the second delay element, the output which is connected to the synchro input of the first counter and the first inputs of the elements of OR channels, the second inputs of which are connected to the inverse outputs of the second triggers of their channels, the output of the comparison circuit of the M-th channel (M = 1, K-1) is connected to ( + 1) -th inverse input of the AND element with (M + 1) -th through the K-th channel and the input of the first OR element, the clock input of the second counter is connected to the output of the OR-NOT element, the first input of which is connected to the output of the first OR element, the second the input of the AND element is connected to the second input of the OR-NOT element, the reset inputs of the first channel triggers and is the input of the end of service of the device, the clock inputs of the first triggers are connected to the output of the first delay element, the output of the And element of each channel is connected to the information input of the first trigger of its channel.