SU1638793A1 - Multichannel programmable pulse generator - Google Patents

Abstract

The invention can be used to build broadband multi-channel programmable pulse sequence generators in automation and control systems. The purpose of the invention is to expand the functionality by introducing a multi-cycle mode of operation while simultaneously forming several pulse sequences is achieved by connecting the counter outputs of 15 cycles through multiplexer 28 to the information inputs of the memory block 29, in fw of which the reference values of the cycle number codes and their current values are stored. . The end of cycle processing is determined by comparison unit 18. The pulse sequence formation program is stored in memory block 3. The device also contains a generator 1, a pulse distributor 2, a start bus 4, a data bus 5, a write bus 6, a zero zero dog 7, an output bus 8, an I-bus 9, an OR element 10, an installation bus 11, a zero bus 12, a trigger 13 , address 14 counter, AND element 16, buffer register 17, AND 19 element, buffer register 20, OR-NE 21 element, control bus 22, multiplexer 23, triggers 24, 25, AND-OR-26 element, control bus 27 , element OR-NOT 30, element AND 31, bus 32 records, element AND 33, element OR-NOT 34, trigger 35, element OR 36, shaper 37 pulses, element OR 38, ale ent OR NOT 39, element 40, trigger 41, 2 Il. with g (L with eb with 00 with with with Figure 1

Description

The invention relates to a pulse technique and can be used to build wide-range multi-channel programmable generators of pulse sequences in synchronization systems, automated monitoring and control, measuring instruments and installations.

The purpose of the invention is to expand the functionality by introducing a multi-cycle mode of operation with the simultaneous formation of several pulse sequences.

Figure 1 presents the functional diagram of the multi-channel programmable pulse generator; in fig. 2 - time diagrams of his work.

The pulse generator contains the generator 1, the pulse distributor 2, the memory block 3, the start bus 4, the data bus 5, the write bus 6, the zero bus 7, the output bus 8, the write bus 9, the OR element 10, the installation bus 11, the zero bus 12 , trigger 13 counter 14 addresses, counter 15 cycles element AND 16, buffer register 17, block 18 comparison, element AND 19, buffer register 20 3 element OR-NOT 21 bus 22 control, multiplexer 23 triggers 24 and 25, element AND-OR- IE 26, control bus 27, multiplexer 28, memory block 29, OR-NOT element 30, AND element 31, write bus 32, And element 33, element DO-NOT 34, a trigger 35, an OR gate 36, pulse generator 37, an OR gate 38 OR-NO element 39, AND gate 40 and trigger 41.

The output of the generator 1 is connected to the first input of the pulse distributor 2, the third input of which is the start bus 4. The third input of the distributor 2 pulses is connected to the zero bus 7, the inputs of the preset-buffer registers 17 and 20, the second inputs of the OR-NO elements 21, 34 and 39 and the second input of the OR element 38. The first output of the distributor 2 pulses is connected to the first input of the element OR 10 and the first input of the element OR NOT 34, the output of which is soy

It is connected to the input of the preset trigger 35, the direct output of which is connected to the counter enable input of 15 cycles and through the img generator 37

five

0

5 0 .Q

5 Q

five

five

pulses with the first input of the element OR 36, the output of which is connected to the clock input of the counter 15. pulses, the input of the preset of which is connected to the output of the element OR-NOT 39, “the first input of which is connected to the output of the element AND 40 and the input of the trigger setup 41, the inverse output of which is connected to the first input of the AND-OR-HE element 26, the transistor of which is connected to the resolution enable input of the address 14, the outputs of which are connected to the address inputs of memory blocks 3 and 29. The second output of the distributor 2 pulses is connected to the first inputs of elements AND 16, 19 and 33 and to the first inputs of elements OR-NE 21 and OR 38. The third output of the distributors 2 pulses is connected to the clock inputs of the triggers 24 and 25 and the first input of the element 40 the second input of which is connected to the output of the comparator unit 18, the first inputs of which are connected to the outputs of the counter 15 cycles and the first inputs of the multiplexer 28, and the second inputs are connected to the outputs of the buffer register 17, the information inputs of which are connected to the information inputs of the counter 15 iklov and outputs the block memory 29, whose data inputs are connected to outputs of the multiplexer 28, whose second inputs are connected to data inputs of block memory 3, the first inputs of the multiplexer 23 and data bus 5. The address input of the multiplexer 28 is the control bus 27. The fourth output of the pulse distributor 2 is connected to the first input of the element AND 31, the output of which is connected to the first input of the element OR-NOT 30, the second input of which is the recording bus 32. The output of the element OR NOT 30 is connected to the resolution input of the memory block 29. The resolution input of memory block 3 is a write bus 6, and the fourth output is connected to the second inputs of elements 16 and 19, the third outputs of memory 3 is connected to information inputs of the buffer register 20, the clock input of which is connected to the output of element 19, the second the output of memory block 3 is connected to the inf9RMa- tional input of the trigger 24, the output of which is connected to the third input of the I-ИШ-fffi 26 element, the second input

which is connected to the direct output of the trigger 25, the information input of which is connected to the first output of the memory block 3, to the second inputs of the elements 31 and 33 and the input of the comparison block 18, the fifth outputs of the memory 3 are the output bus 8 . The second input of the element OR 10 is the recording bus 9, and the output is connected to the clock input of the address counter 14, the information inputs of which are connected to the outputs of the multiplexer 23 whose address input is the control bus 22. The preset inputs of the flip-flops 24 and 25 are connected to the output of the OR-NOT 21 element. The fourth input of the AND-OR-HE element 26 is connected to the direct output of the trigger 13, the installation input of which is the installation bus 11 and the preset input is the zero bus 12. The outputs of the buffer register 20 is connected to the second inputs of the multiplexer 23. The output of the element And 33 is connected to the second input of the element OR 36 and the clock input of the trigger 35, the inverse output of which is connected to the J-input, and the K-input - to the common bus. The output of the element And 16 is connected to the clock input of the buffer register 17. The output of the element OR 38 is connected to the input of the preset trigger 41.

The pulse generator works as follows.

Consider the process of forming a real time diagram for the four output channels (Fig.2i-m). After the passage of n pulses in channel I, a pulse should form in channel II. Further, after the passage of m pulses in channel II, a pulse should be formed in channel III. After passing to the pulses in channel III, a pulse must be formed in channel IV. Further, this timing diagram must be repeated an infinite number of times.

Pre-generator must be programmed.

Programming is carried out under computer control through a standard interface. At address 1, as determined by address counter 14, the following information is recorded in blocks 3 and 29 of memory:

in the memory block of block 3, corresponding to the 1st channel of the bus 8 and even, 10

387936

at the output of block 3, G1 is recorded;

the binary number 1 is written in the memory cells corresponding to the third outputs;

in the remaining memory cells of block 3 are written 0

The IB memory block 29 at address 1 records a binary code corresponding to the number of pulses that need to be issued on the 1st channel, i.e. binary code of n

At address 2, the following information is recorded in blocks 3 and 29 of memory jc:

the memory cells of block 3, corresponding to bus 8, third outputs and second output, are written

 the memory cell corresponding to the first 20 output of memory block 3 is recorded 1 (the presence of the Cycle 3 command), in the remaining memory cells this is

0

the first block is recorded

O. 5 is recorded at memory block 29. At address 3, the following information is recorded at memory blocks 3 and 29:

the memory cells of block 3 corresponding to the 1st and 11th channels of bus 8 and the fourth output of block 3 are recorded

A binary code of the number 1 (return address code) is recorded in the memory cells of block 3 corresponding to the second outputs of block 3; the memory cells of this block, corresponding to the second and first outputs of block 3, are written O,

The binary code of the number tp is recorded in the memory cell of block 29.

At address 4, the following information is recorded in blocks 3 and 29 of memory:

in the memory cell corresponding to the first output of block 3 is written

five

0

five

in the rest of this memory

0

five

one

block write O

in the memory cell of block 29 is written O,

At address 5, the following information is recorded in blocks 3 and 29 of memory:

the memory cells of block 3, corresponding to the 1st – III channels of the bus 8 and the fourth output of block 3, are recorded

The binary code of the number 1 (the return address code) is recorded in the memory cells of block 3, corresponding to the third outputs of block 3; in the memory cells of this block, the corresponding

the second and first outputs of block 3 are recorded Otf;

The binary code of the number k is written in the memory cell of block 29.

At address 6, the following information is recorded in blocks 3 to 29 of memory:

in the memory cell corresponding to the first output of block 3 is recorded in the remaining cells of the memory of this block

in the memory cells of block 29 are written O.

At address 7, the following information is recorded in blocks 3 and 29 of memory:

in the memory cells of block 3, corresponding to the 1st - IVth channels of the bus 8 and the fourth output of block 3, are recorded

in the cell memory block. 3, corresponding to the third outputs of block 3, the code of the number 1 (return address code) is recorded; the memory cells of block 3, corresponding to the second and first outputs of block 3, are also recorded

The number 0 is written in the memory cell of block 29.

At address 8, the following information is recorded in blocks 3 and 29 of memory:

111 is written in the memory cell corresponding to the second output of block 3 (the presence of the command Cycle 2) in the remaining cells of the memory of this block

in the memory cells of block 29 are written O.

This completes the programming of the multi-channel programmable generator. The principle of operation of the generator is to loop certain predetermined memory cells of the memory block 3 a predetermined number of times. The number of cycles is determined by the information recorded in the memory unit 29 and the cycle counter.

In the initial state, all the triggers and counters are reset.

The generator 1 generates a continuous sequence of square-wave square-wave pulses in accordance with FIG. 2a. The Start signal arriving at the bus 4, the distributor 2 forms a four-pulse timing diagram in accordance with figb-d. By pulse I1, arriving at the clock input of the counter 14 addresses through the element OR 10, the counter

14 addresses are set to state 1 by addressing the first memory locations of memory blocks 3 and 29. Through the element OR-NOT 34, the same impulse confirms the zeroed state of the trigger 35. This action, carried out by the impulse I1, ends. At the same time in the first

0, bus channel 8, a single potential is formed.

Next, the distributor 2 generates the pulse I2, which, confirms the zeroed state of the flip-flops 24,

5 25 and 41. In addition, since a single potential is present at the fourth output of memory block 3, the number 1 from block 3 parameters is written to buffer register 20 via element 19.

This number is the return address, which is subsequently rewritten into the address counter 14. The code of the number of pulses (number n) is rewritten into the buffer register 17 from memory block 29.

Pulses FROM and I4 do not change the state of the elements and blocks of the generator, since the corresponding permissions are not received from block 3 of the memory.

Next, the distributor 2 again generates pulses I1-I4. By pulse I1, the address counter 14 enters state 2 and addresses the second memory cells of memory blocks 3 and 29.

In this case, in the first channel of the bus 8, a zero potential is formed (thus, the first of the n pulses of the sequence is formed). In addition, at the first output of the memory block 3, a single potential is formed, which further allows the operation of the trigger 25, the elements 31 and 33 and the block 18 of the comparison. Since the trigger 35 is still in the zero state, the counter

15 cycles is in parallel code recording mode, and the pulse

0 I2, having passed through the elements AND 33 and OR 36, rewrites the parallel code from the memory block 29 into the counter of T5 cycles. In this case, it will be the number 0. The rear edge of the pulse I2

5, the trigger 35 is set to 1 and translates the counter 15 cycles from the parallel code recording mode to the sequential counting mode. On the falling edge of the I2 impulse

0

The transmitter 37 generates a pulse, which, having passed through the element OR 36, adds +1 to the counter 15 cycles, i.e. the cycle counter now stores the number 1.

The impulse FROM sets the trigger 25 to one state. In this case, a zero potential is formed at the input of the resolution of the address counter 14, and it switches to the parallel code recording mode. However, the parallel code is written to it only in the next cycle of operation of the distributor 2. Since the code in the buffer register 17 (the number n) does not correspond to the code in the counter 15 (number 1), the output potential of the comparison unit 18 is zero does not pass through the AND element and does not change the states of the trigger 41 and the counter 15.

Pulse I4 causes the number to be overwritten from counter 15 through multiplexer 28 to memory block 29. Thus, at the end of this cycle of operation of the distributor 2 at address 2, the current code (one) of the cycle counter is stored in memory block 29.

Next, the distributor forms the next cycle. However, since the flip-flop 25 is in the single state, the address counter 14 is in the parallel code recording mode and the impulse I1 through the multiplexer 23 translates the code from the buffer register 20 (in this case, the number 1), i.e. blocks 3 and 29 of the memory are again addressed to the cells with number 1. In the first channel of bus 8, a single potential is again formed, i.e. a second pulse starts to form from among p. The actions described below are repeated. In this case, at the beginning of each corresponding cycle, from block 29 to counter 15, the current value of the counter of 15 cycles is written, and at the end of the same cycle (by pulse I4) to memory 29, the new current value of the counter of 15 cycles is written. In the buffer register 17 of the memory block 29, in each respective cycle, the same code (the number n) is overwritten all the time, since this code is stored in a memory cell, the contents of which cannot be changed.

After the n cycles have expired, the contents of the 15 cycles counter become equal to the contents of the buffer register g 17, and a single potential is formed at the output of the comparison unit 18, which allows the pulse TO to pass through the AND element 40. At the same time, the trigger 41 and the counter 15 cycles. The address counter 14 is set to the sequential counter mode, and in the next cycle of operation of the distributor 2, pulse I1 adds +1 to the counter5 address 14 instead of overwriting it with a parallel return address code. In the address counter 14, the code of the number 3 is located, and addressing of the memory cells of the blocks 3 and

0 29 with the address 3. At the same time, in the 1st and 11th channels of the bus 8, unit potentials are formed.

Pulse I2 writes the return address code (number 1) to the buffer register 20 from memory block 3, and the number of hectares is written to the buffer register 17 from memory block 29. Further operation of the generator occurs according to the described algorithm: in the next work cycle, distribution 2 (the value of the address 14 counter is 4) zero potentials are formed in the 1st and II channels of bus 8. The current code of the number of cycles is written to the counter 15 from the memory block 29 (at first it will be the number 0). Next, +1 is added to this number, and the new counter value of 15 cycles is rewritten into memory block 29.

0 (in memory location 4). In this case, the trigger 25 determines parallel writing to the address counter 14, and in the next cycle of operation of the distributor 2, the transition to ad5 res 1. The further operation of the programmable generator is similar to that described.

Due to the organization of a two-way exchange of current values of the number of cycles between the counter 15 cycles and the memory block 29 (namely, its cells with addresses 2.4 and 6), it is possible to embed cycles into cycles, and the number of possible investments It is only the volume of the memory block 29. Thus, when building a memory block 29 on 4K IC chips with a capacity of 4K, the maximum number of possible investments is 2048, which makes it possible to form very complex time diagrams. In this example, the number of attachments is 3. It uses only 6 memory cells.

Further, these normalized cycles are invested in an infinite loop, and the entire timeline is repeated until a forced stop of the generator 1 or the distributor 2 occurs. The infinite looping occurs due to the fact that in the corresponding memory slot with address 8 (and it is the bit corresponding to the second output of memory block 3) the unit is recorded (Cycle 2 command). Therefore, the trigger 24 is set to 1, and in the next distributor operation cycle, the return address code (in this case, 1) is written to the address counter 14. In addition, several programs for generating various time diagrams can be stored in the memory of the programmable generator and can be automatically changed during the operation of the generator.

Claims (1)

Invention Formula Multichannel programmable pulse generator, containing a generator, the output of which is connected to the first input of the pulse distributor, the first output of which is connected to the first input of the first OR element, the output of which is connected to the clock input of the address counter, the information inputs of which are connected to the outputs of the first multiplexer, the first inputs of which are connected with the information inputs of the first memory block, whose address inputs are connected to the outputs of the address counter and the address inputs of the second memory block, output which is connected to the information inputs of the loop counter, the second, third elements OR, the first trigger, characterized in that, in order to expand its functionality, the fourth element OR, the first to the fifth elements, AND, the first, second buffer registers, the second Fifth triggers, first through fourth elements S 0 five 0 five 0 five 0 five OR NOT, the second multiplexer, the pulse shaper, the comparison unit, the AND-OR-NOT element whose output is connected to the address enable input of the address counter, the second inputs of the first multiplexer are connected to the outputs of the first buffer register, clock. the input of which is connected to the output of the first element AND, the first input of which is connected to the second output of the pulse distributor, to the first input of the first element OR NOT, to the first inputs of the second, third AND elements and to the first input of the second OR element, the output of which is connected to the preset input the first trigger, the inverse output of which is connected to the first input of the AND-OR-NOT element, the second input of which is connected to the direct output of the second trigger, the clock input of which is connected to the clock input of the third trigger, to the third output the pulse distributor and the first input of the fourth element AND, the output of which is connected to the installation input of the first trigger and the first input of the second element OR NOT, the output of which is connected to the preset input of the cycle counter, the clock input of which is connected to the output of the third element OR, the first input of which connected to the output of the pulse generator, the input of which is connected to the direct output of the fourth trigger and to the enable input of the cycle counter, the outputs of which are connected to the first inputs of the comparison unit and the first input the second multiplexer, the second inputs of which are connected to the first inputs of the first multiplexer, the fourth output of the pulse distributor is connected to the first input of the fifth AND element, the output of which is connected to the first input of the third OR-NOT element, the output of which is connected to the resolution input of the second memory block, informational inputs of which are connected to the outputs of the second multiplexer, the output of the third trigger is connected to the third input of the AND-OR-NOT element, the fourth input of which is connected to the direct output of the fifth trigger, the first the th output of the pulse distributor is connected to the first input of the fourth element OR NOT, the output of which is connected to the preset input of the fourth trigger, the K-input of which is connected 13 with a common bus, J-input with an inverse output, and a clock input with the second input of the third OR element and the output of the second element AND, the second input of which is connected to the gate input of the comparison unit, with the second input of the fifth element AND the output of the first memory block and the information input of the second trigger whose preset input is connected to the preset input of the third trigger and to the output of the first OR-NOT element, the second input of which is connected to the second input of the pulse distributor, to the preset first, second th buffer registers, with the second inputs of the second, fourth elements OR NOT and with the second input of the second element OR,  , Jq 20 3879314 the second output of the first memory block is connected to the information input of the third trigger, the third outputs of the first memory block are connected to the information inputs of the first buffer register, the fourth output of the first memory block is connected to the second input of the first And element and the second input of the third And element, the output of which is connected the clock input of the second buffer register, the outputs of which are connected to the second inputs of the comparison unit, the output of which is connected to the second input of the fourth And element, the outputs of the second memory block are connected to information inputs of the second buffer register.  Ping jUHtpeaua 1-PLPL111ShLLLLLL .... . .. . P .. I ... LTL MZR . t Hints in MvBHttJI -r-l -...- t