SU1626429A1 - Phase corrector - Google Patents

Description

(21) 4674977/09

(22) 05.04,89

(46) 02.02.91. Bul M b

(72) A.N. Medvedev

(53) 621.394.662 (088.8)

(56) USSR Author's Certificate M 1160578, Clo H 04 L 7/02, 1984.

(54) PHASE CORRECTIVE DEVICE

(57) The invention relates to telecommunications. The purpose of the invention is to improve accuracy. The faer-corrective device contains a driver, Mr. 1t, triggers 2, 8 and 10, emails OR 3 and 4, emails And 5

and 6, the inverter 7 and the IS-NE 9. The phase change is carried out in the device by adding or subtracting pulses in the output sequence. This changes the instantaneous frequency of the output pulses by changing the follow-up period of several of them. The number of phase cycles of the output pulses per unit time varies. The device corrects the phase both in the direction of advance and in the direction of lag relative to the initial value. 1 silt

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The invention relates to telecommunications and can be used in high-speed receivers of discrete information, in equipment for synchronous data transmission, for example, in collective use systems as an executive element of automatic digital phase control systems.

The purpose of the invention is to improve accuracy.

The drawing shows an electrical diagram of a phase correction device.

The phase-correction device contains a master oscillator 1, a trigger 2, the first and second elements OR 3 and 4, the first and second elements AND 5 and 6, the inverter 7, the first additional trigger 8, the element AND-HE 9 and the second additional trigger 10 "

Phase correction device works as follows.

The device performs a phase change by adding or subtracting pulses in the output sequence. In this case, the instantaneous value of the frequency of the output pulses changes due to a change in the follow-up period of several of them. The number of phase cycles of the output pulses per unit of time changes if the digital divide frequency is connected to the output of the device in question, then the phase of the output pulses of the divider will change in the direction of advancing or lagging behind the initial one with a discrete equal to the period of the output pulses of the phase-correcting device under consideration, and the number of discretes will be equal to added (for advance) or subtraction (for lag) pulses in the output sequence of this device.

In the initial state (in the absence of phase correction), the master oscillator 1 generates a sequence of pulses, the follow-up period of which is two times less than the follow-up of the output pulses of the device in the absence of correction (Ti 2Tsg). The control signals on the first and second devices are absent, so the output of the element IS-HE 9 is logical 1, and the inverse output of the second additional trigger is logical O (since its S-output has

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О from the first input of the device).

Logical O from the inverse output of the second additional trigger 10 is fed to the second input of the second element OR 4, the first input of which receives output pulses of the device passing through this element to the C input of the first additional trigger 8. When the device is turned on, this trigger is set to either other state. Let it be logical 1 for the inverse output and logical O for the direct one. Then one of the elements 5 and 6 opens at the third input for the passage of signals, and the other closes (in this case, the element 5 is open and the element 6 is closed). At the same time, the pulses from its generator 1 arrive at the trigger input 3 of the trigger (T -type), through the inverter 7, since the trigger 2 operates on a given pulse front. Example 3 divides the frequency of the HI two master oscillator pulses. Thus, at the outputs of trigger 2, two mutual inversions of a sequence of pulses of the type meander are formed with the following period of the device (in the absence of correction) of the output pulses of the device, which are used to obtain the And 5 and 6 of the two pulse sequences of the period Ti, shifted one relative to the other by half a period (on Gi / 2). For this, signals from the corresponding output in trigger 2 (on element 5 - from inverse, on element 6) from direct, and to the first inputs of both elements 5 and 6 - inverted pulses of master oscillator 1 (from inverter 7) with period T, g . In this case, the pulses are passed to the output of the elements And 5 and 6, to the third input of which logical 1 is fed from the corresponding output of the first additional trigger 8 (in this case, the pulses in the initial state are at the output of the first element 5). The output pulses of the elements And 5 and 6 through the first element OR 3 pass to the output of the device. These output pulses through the second element OR 4 arrive at the C-watcher of the first additional trigger 8

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and depending on the state of its I and K inputs, it can change the state of its outputs. But in the initial state at the I- and K-output of the first additional trigger 8 logical O, therefore the state of its outputs on a given edge of pulses arriving at its clock input does not change

If it is necessary to make a phase correction, the control signal is fed to the first input of the device, to the second input of the device — logical O. A case is considered when a pulse sequence from the output of the first element And 5 passes to the device output. the first input of the first additional trigger 8 is set to logical 1 at the first input of the control signal device and this trigger starts to operate in the division mode and the frequency of the pulses arriving at its clock input, triggered on a given front of these pulses. These pulses come through the second element OR 4 from the output of the device, so after installing the control signal at the first input of the device, on the trailing edge of the very first next output pulse of the device, the first additional trigger 8 switches to the opposite state (logical 1 on the forward output, logical O - inverse). In this case, the first element And 5 is closed for the passage of pulses, and the second element And 6 - opens, and its output pulse, shifted by lolperid relative to the previous one, passes to the output of the device.

Thus, in the case of advance phase correction, the phase cycle duration of the device output pulses is reduced from T to. Since the control signal still acts on the I and K inputs of the first additional trigger 8, this trigger on the trailing edge of the pulse already shifted to Ti / 2 again switches to the initial state, and the device passes the pulse again from the output the first element And 5. The phase cycle between adjacent output pulses is again equal to TC / 2, Thus, during the time Ti at the output of the mouth

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Two impulses are formed, not one, as in the case of no correction. This is equivalent to a phase shift of the output pulses by discrete equal to the leading side.

A similar phase correction in the direction of advance continues in the device as long as the control signal is present at the first input. With the end of this signal, a logical O is established at the I and K inputs of the first additional trigger 8, and the first additional trigger 8 does not change its state at the given edge of the next output pulse that arrives at the C input of this trigger, and all the subsequent pulses go from the output of one of the elements II 5 or 6 and a constant period Ti The number of pulses added to the output sequence of the device is equal to the number of pulses formed by trigger 2 during the control present signal.

The element AND-HE 9 and trigger 10 are not involved in the operation of the device when the phase is adjusted in the direction of advance. When adjusting the phase in the direction of lagging relative to the initial value of the gains; the signal is also applied to the first input, d of the device, and a logical 1 is set at the second input of the device. Consider the case of a phase correction in the side lag by one sample (phase correction gack). At the same time, the output of the pulsed output device must be removed if the imlulos. As in the previous case, the output of the device before the start of the correction let the pulses pass from the output of the first element I 5.

With the appearance at the first input of the control signal device, element 9 obtains permission for the group to go to its output, the output km-pulgs of the device, the arrival} at the second point of this element. Simultaneously, the 1 and K-inputs of the first additional trigger 8 become logical 1, prepares this trigger for operation in the division mode by two frequencies of pulses arriving at the 6th clock input through the second element OR 4 from the device output. The first next output pulse

the device begins to arrive at the C input of the first additional trigger 8, since at the second input of the second element OR 4 is logical O, the first additional trigger 8 does not operate from the leading edge of this pulse (the trigger 8 on the C input is triggered only by the falling edge of the pulse voltages from logical level 1 to logical level O). At the same time, the inverted output pulse of the device appears at the output of the AND-HE element 9 and arrives at the D input of the second additional trigger 10c. The C input of this trigger receives the pulses of the master oscillator. In this case, the fronts of the inverse pulse from the output of the NANDI element 9 are delayed relative to the fronts of the pulse of the oscillator 1 for 4C-J time, where tg is the delay time for signal propagation in one logical element of the device

The 4TE value is obtained from the assumption that the signal delays in the inverter Y, the AND elements (5 or o), the first element OR 3, and the AND-HE element 9 are the same. Therefore, the front edge of the pulses of the master oscillator 1 (the leading edge of the pulses of the inverter 7) arrives at the time of the presence of a logic O at the D input of the second additional trigger 10. Therefore, the inverse output of the second additional trigger 10 is established, logical 1. Before provided during operation without correction by logical O at the S input of the second additional trigger 10, and at the beginning of the control signal, confirmed by the front of the first next pulse of the master oscillator, since at the output of the element AND-NE 9 before this was logical 1. Logic 1 from the output of the second additional trigger 10 confirms logical 1 established at the output of the second element OR 4 with the arrival of the device’s output pulse to its first input, With the end of this pulse at the first input the second element OR 4 at its output — logical 1 is saved; therefore, the operation of the first additional trigger 8 on the trailing edge of the HI pulse occurs.

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The state of the outputs of the first additional trigger 8 does not change, the output of the first element AND 5 still remains connected to the output of the device. During the formation of the leading edge of the next pulse of the master oscillator 1, the output pulse of the device is absent, therefore the D input of the second additional trigger 10 - logical 1, and on this front of the pulse of the master oscillator 1 the second additional trigger 10 is set to logical O, passed through the second element OR 4, is sensed at the C input of the first additional m 8 iggera the trailing edge of the pulse, so the first additional trigger 8 changes the state of its outputs is reversed. At the same time, the output of the second element AND 6 is connected to the output of the device through the first element OR 5, but by this time the pulse that could pass through this element to the output of the device had already ended, and thus one pulse was subtracted from the output sequence as Sy. Subsequently, with the termination of the control signal at the first input of the device, the state of peruguo to the second additional triggers 8 and 10 does not change, and the output starts to receive pulses from the output of the second element 6, and moreover, they are separated from the previous i.-i Chrome Ti / 2. This is equivalent to a phase shift of the output pulses on the discrete, equal to Tjr, in the direction of the lag. All subsequent output pulses after correction will have a constant period.

Claims (1)

Invention Formula A phase correction device containing a master oscillator, a trigger, two OR elements, and the output of the first OR element is an output of the device, characterized in that, in order to catch 1 accuracy, the first and second additional triggers are introduced, the inverter, the first and second elements, and the element NAND, the first of which is connected to the I and 1C input-MnjiepBoro of the additional trigger and S-input of the second additional trigger and is the first input of the device, while the output specifies the generator is connected to the clock input of the second additional trigger and through the inverter to the clock input of the trigger and the first inputs of the first and second elements AND, to the second inputs of which are connected respectively the inverse and direct outputs of the trigger, and the outputs of the first and second elements AND through the first element OR are connected to the first input of the second element OR and the second input of the NAND element, the third input of which is the second input of the device, and the output of the element NAND is connected to the D-input of the second additional trigger, whose R-input is the input of the unit potential of the device, and the inverse output of the second additional trigger is connected to the second input of the second OR element, the output of which is connected to the clock input of the first additional trigger, direct and inverse outputs of which are connected to the third inputs of the second and first elements, respectively.