SU1626419A1 - Device for checking the performance of superheterodyne radio receivers - Google Patents

Abstract

This invention relates to a radio technique. The purpose of the invention is to increase the reliability of the control while reducing the time of the control. The device contains an input signal simulator 1 consisting of an intermediate frequency generator 2, a balanced modulator 3, a controlled attenuator 4, electronic switches 5, 7, 8 and Yu and mixers 6 and 9, a control signal generator 11, a controlled delay element 12 , the balanced demodulator 13, the filter 14, the threshold unit 15, the indicator unit 16, the memory unit 17, the control unit 18. The control is carried out in two stages. At the first stage, the superheterodyne receiver 19 is monitored as a whole, and at the second stage, monitoring is performed element by element. All device operation is automatic. 1 hp f-ly, 2 ill. i (L of Fig 1

Description

The invention relates to a radio communication technique and can be used in various radiotelephone and radiotelegraphic communication systems for monitoring a superheterodyne receiver path. The purpose of the invention is to increase the reliability of the control while reducing the time of the control.

FIG. Figure 1 shows the structural electrical circuit of the device proposed; in fig. 2 shows an embodiment of the control unit.

The superheterodyne receiver operability control device (Fig. 1) contains an input signal simulator 1, consisting of intermediate frequency generator 2, balanced modulator 3, controlled attenuator 4, first electronic switch 5, first mixer 6, second and third electronic switches 7 and 8, a second mixer 9, a fourth switch 10, a pilot signal generator 11, a controllable delay element 12, a balanced demodulator 13, a filter 14, a threshold unit 15, an indicator unit 16, a memory unit 17, and a control unit 18. Superheterodyne receiver 19 consists of high-frequency amplifiers 20, first mixer 21, first intermediate frequency amplifier 22, second mixer 23, second intermediate frequency amplifier 24, detector 25 and first and second local oscillators 26 and 27.

The control unit 18 (FIG. 2) contains an AND element 28, a trigger 29, a control key 30, a shift register 31, and a delay element 32.

The device works as follows.

After turning on the power while monitoring the superheterodyne receiver 19. the elements and blocks involved in the control are set to zero with & (Fig. 1). At the same time, at the outputs of the shift register 31 of the control unit 18 (FIG. 2), there are no signals (i.e., zero is recorded in bits 1-4) the trigger 29 is set to zero, and the control key 30 controlled by this trigger 29 is open, due to what are the clock pulses

wired from generator 11 does not pass on

clock input register 31 shift. Due to the lack of control signals at the inputs of the first, second, third and fourth electronic

Q with

0

0

five

switches 5, 7, 8, and 10 last connect the elements of the simulator 1 to each other and connect it to the superheterodyne receiver 19. Due to the lack of control signals at the control inputs of the controlled attenuator 4 and the memory block 17, the controlled attenuator 4 provides the greatest attenuation the power of the signals passing through it, and the controlled delay element 12 is the maximum delay of the generated pseudo-random sequence (SRP) input to the filter 14.

Superheterodyne detector 19 is monitored in two stages. At the first stage, a higher level control is performed, during which the path of the entire superheterodyne receiver 19 is checked, and at the second stage, a lower level control is performed when its individual nodes are checked for serviceability.

The operability check of the entire superheterodyne receiver 19 does not differ from the performance monitoring carried out in a known device. The control signal, which is modulated at the output of the balanced modulator 3 by the pseudo-random sequence of generator 11 PSP sinusoidal carrier, generated by generator 2, is fed to the input of controlled attenuator 4, through the first electronic switch 5 to the input of the first mixer 6, and through the second and third electronic switches 7 and 8 to the input of the second mixer 9. The first and second mixers 6 and 8 of the simulator 1 convert the frequency of the generator 2 to the frequency of the superheterodyne receiver 19.

The generated control signal is fed through the fourth electronic switch 10 to the input of the superheterodyne receiver 19 (to the input of the amplifier 20). This signal passes successively through the first mixer 21 and the amplifier 22 of the first intermediate frequency, the second mixer 23 and the amplifier 24. From the output of the amplifier 24, the signal goes to the inputs of the detector 25 and the balanced demodulator 13. In addition to the control signal carrying information on the state of the high-frequency path and coming from the output of the amplifier 24, to the balanced demodulator 13 is fed

unmodulated second intermediate frequency. From the output of the balanced demodulator 13 to the input of the filter 14, a reconstructed pseudo-random sequence is applied. The second input of the filter 14 through the controllable delay element 12 is supplied with an undistorted pseudo-random sequence from the output of the generator 11. The decision on the state of the superheterodyne receiver 19 is made by the threshold unit 16 when comparing the response of the filter 14 with a predetermined threshold. The result is displayed on the indicator unit 16. Thus, in the case of the health of the superheterodyne receiver 19, the Norm transparency may be turned on, and in the event of a malfunction, the Failure.

In the second case, i.e. in the event of a malfunction of the superheterodyne receiver 19, a lower level of operation is performed, i.e. individual receiver nodes. When any of the blocks of the superheterodyne receiver 19 fails, a pulse appears at the output of the threshold unit 15, which is fed not only to the indicator unit 16 but also to the information input of the control unit 18. When the time of occurrence of this pulse coincides with the clock pulses of the generator 11, a pulse appears at the output of the element 28 of block 18, which triggers the trigger 29 to a new state, in which the output of the trigger 29 sets a logical unit that translates the control key 30 in a closed state. From this point on, the clock pulses are allowed access to the synchronization input of the shift register 31.

At the same time, the information input of the register 31 through the delay element 32 (the delay time is determined by the pulse passing time from the output of the threshold unit 15 along the described circuits) receives a pulse generated by the threshold unit 15. As a result, the corresponding output of the shift register 31 appears . This unit that is supplied to the indicator unit 16, and from other outputs to the unit 17, the controlled attenuator 4 and the first electronic switch 5. The first electronic switch 5 disconnects the controlled output of the attenuator 4 from the first mixer 6 and connects it to the input usi0

five

0

A superheterodyne detector 19 is inserted 24. The delay time of the controlled delay element 12 in both these and other cases is set to ensure coherent addition of the pseudo-random sequences in the filter 14.

The attenuation threshold of the controlled attenuator 4 is chosen in each case so as to ensure the same level of the signal at the input of the threshold unit 15 while monitoring different nodes. After this, the amplifier 24 is checked, which does not differ from the sequence described.

When a failure is detected at the output of the threshold unit 15, a pulse appears that, before the malfunction in the amplifier 24 is eliminated, the superheterodyne receiver 19 nodes are monitored by transferring the trigger 29 to a new state, at which the clock pulses stop moving to the shift register 31. In the display unit 16, a failure is appearing on the OFCO 2. In the case of a health condition, the amplifier 24, i.e. in the absence of a pulse at the output of the threshold unit 15, the shift register 31 is transferred to the next state, as a result of which the control action is removed from the input of the first electronic switch 5, and the control signal is sent to the second electronic switch 7, the command to start the ignition of the banner. , the controllable attenuator 4 and the controllable delay element 12 are brought into new states, and then the second mixer 23 and the amplifier 24 are checked.

Thus, the remaining nodes of the superheterodyne receiver 19 are checked before the failure is detected.

I

Claims (2)

1. A device for monitoring the health of a superheterodyne receiver, containing a series-connected test generator , a signal and a delay element connected in series by a balanced demodulator, the first input of which is connected to the output of the amplifier of the second intermediate frequency of the superheterodyne 0 five 0 five receiver, the filter, the second input of which is connected to the output of the delay element, the threshold unit and the indicator unit, the input simulator consisting of the first and second mixers, the first inputs of which are connected respectively to the outputs of the second and first heterodyne of the superheterodyne receiver, sequentially connected intermediate frequency, the output of which is also connected to the second input of the balanced demodulator, and a balanced modulator, the second input of which is connected to the output of the control signal generator , characterized in that, in order to increase the reliability of the control while reducing the monitoring time, a memory block is inserted, the output of which is connected to the control input of the delay element, the control block, the synchronization and information inputs and the first output of which are connected respectively to the second outputs of the control generator signal and the threshold unit and the second input of the indicator unit, and in the input signal simulator four electronic switches are introduced and a controlled attenuator, the information input connected to the output of the balanced modulator, and the output is connected to the information input of the first electronic switch, the first output of which is connected to the second input of the first mixer, the output of which is connected to the information input of the second electronic switch, the first and second outputs of which are connected to the second mixer superheterodyne receiver and information input 0 5 Q five The third electronic switch, the first and second outputs of which are connected respectively to the input of the amplifier of the first intermediate frequency superheterodyne receiver and the second input of the second mixer, the output of which is connected to the information input of the fourth electronic switch, the first and second outputs of which are connected respectively to the input of the second mixer of the superheterodyne receiver and input superheterodyne receiver, the second output of the first electronic switch is connected to the input of the amplifier of the second line The second, third, fourth, fifth, and sixth outputs of the superheterodyne receiver, the control unit, are connected respectively to the control inputs of the memory unit and the controlled attenuator, the first, second, third, and fourth electronic switches, and the control signal generator is in the form of a generator pseudo-random sequence, and the delay element is controlled. 2. The device according to claim 2, wherein the control unit is designed as a delay element and an AND element connected in series, the first input of which is connected to the input of the delay element, a trigger, a control key and a shift register, the clock input of which is connected to the output of the delay element The outputs of the shift register are the outputs of the control unit, the synchronization and control inputs of which are respectively the control input of the control key and the first and second inputs of the element I. P l fi.g