SU1626400A1 - Device for separating errors out of digital test signals - Google Patents

Abstract

This invention relates to a wireline technique. The purpose of the invention is to improve the accuracy of error allocation by detecting slips and interruptions in communication. The goal is achieved by introducing an input signal processing unit, which implements the multiplication function by a generator polynomial and fixes the synchro-sync failures, respectively. The signals from the block are fed to the inputs of the link break detection block and the slip detect block, which form information about the presence of slip and breaks of the link. The device is characterized by the execution of an input signal processing unit. 1 hp ff, 1 ill.

Description

The invention relates to telecommunications, in particular to error isolation devices.

The purpose of the invention is to improve the accuracy of error allocation by detecting slips and interruptions in communication.

The drawing shows an electrical block diagram of the device.

The device contains an error corrector 1, a pseudo-random sequence generator 2, a comparator 3, a slip detection block 4, an input signal processing block 5, a key 6, a communication break detection block 7 including a counter 8 and a trigger 9.

Block 5 processing of the input signal contains the first 10, second 11 and third 12 modulo two modulators, shift register 13, trigger 14, counter 15 and the element OR 16.

The device works as follows

At the beginning of operation, the generator 2 forms a sequence, asynphase with the incoming one. As a consequence, errors are output at the output of comparator 3 even in the absence of errors in the incoming signal. The shift register 13 and modulators 10, 11 modulo two form a multiplication unit for a generator polynomial. At its output (output of modulator 11 modulo two), errors are also highlighted at the beginning of the operation due to the initial arbitrary state of the shift registrar 13. With these errors, the trigger 14 is set to one state, and the counter 15 is reset to the initial state with the level of the logical unit at the output. This output of counter 15 cannot change earlier than the error sequence of the shift register 13 is filled, since in this case the interval between any two adjacent errors is always less than the capacity of counter 15. Therefore, the output of the OR 16 element also has a logical unit level that in the interval between the two errors, the trigger 14 can be set to the zero state.

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Thus, from the second output block D to the control input of the error key 6 enters the level of the logical unit, allowing each error to pass from the comparator through the key 6 to the equalizer 1, where each character of the incoming signal that does not coincide in the current clock interval is inverted with the symbol of the reference sequence. Thus, generator 1 forms a sequence with the same phase shift relative to the incoming one.

This mode of operation of the device continues until the register 13 is filled with the error-free abrupt arrival of the sequence to it. Thereafter, the output signal of the adder 11 triggers the 14 is set to the zero state. At the output, the counter 15 is also set to a logical zero if the interval with no errors in the incoming signal is longer than the filling time of the counter. In this case, the output of block 5 will be a signal with a level equal to logical zero, prohibiting correction of the incoming signal by corrector 1. Then, at the output of generator 2, a sequence is formed that is in phase with the incoming signal, and the process of correct error extraction from the passing sequence - nosti. Each error in the incoming signal is also highlighted at the output of the second sum 11, sets the level of the logical unit at the second output of block 5. This unit allows the correction of the error legs of the symbol at the input of the generator 2, thereby maintaining the synchronization of the generator 2 in the presence of errors in the incoming signal.

In this mode of operation of the device, in the presence of an error pulse at the first input of the b / w 4 slip detection, its second input will necessarily be the level of a logical unit that prohibits the passage of the error signal. Therefore, at its output and at the output, the device will slip at a logic zero level.

In the presence of slippage (violation of the synphase of the incoming and reference sequences), the process of restoring synchronization occurs. Therefore, the time will come when the logical zero level is at the second input of the slippage detection unit 4 (the shift register 13 is again filled with an error-free sequence and the counter 15 is full), and at its first input there are errors due to the asynchronous incoming and reference sequences. These errors

passage d through block 4 to the exit. Device slippage, signaling that there was a slippage.

Communication interruption in transmission systems can occur in a double way. In the first case, this is a signal that has no transitions (fronts), and this can be either a logical zero or a logical one. In the second case, such a signal occurs only at the beginning of the interruption, and during the rest of the interruption time, due to the action of the AGC, a random sequence of pulses appears due to noise. In both cases, the counter 8 is triggered and outputs a logic zero level at the output, because when the connection is interrupted, regardless of what signal level at the device input (zero or one), at the output of modulo 12 modulo two will be required and counter 8 will count to overflow. The trigger 9 fixes the interruption of communication, the beginning of which is determined by the zero level of the signal from counter 8, and the end by the level of logical zero at the second output of block 5, because during the interruption of communication at this output the level of logical one will be required. Indeed, when the connection is interrupted as a logical unit at the device input, after filling the shift register 13 with this signal at the output of modulator 11 modulo two, the level of the logical unit is constant, and therefore, the same signal will be at the output of the OR 16 element.

During a break in the form of a logical zero after filling with this signal the shift register 13 at the output of modulator 11 modulo two will be the logic zero level, however, at the OUTPUT of the element OR 16 there will still be the level of the logical unit, T1k as when filling the shift register 13 with the zero signal trigger 14 is set to one state and the entire break will remain in this state due to the prohibition of setting it to the zero state by a logical zero at the control input three, hera 14.

When the communication is interrupted in the form of a random sequence of pulses, the logical unit at the output of the element OR 16 will be supported by the logical unit from the output of the counter 15, since in this case the modulo two output error interval is less than the filling time of the counter 15. Thus, when the connection is interrupted in any form, it will be fixed as a logical unit at the output of the trigger 9 and the output of the device interrupt.

When the connection is interrupted, the generator 2 retains its phase due to the presence of a logical unit at the second input of the corrector 1. Thus, when the connection is interrupted, the correct error selection occurs.

The error isolator is also operable with a test signal in the form of a periodically repeating arbitrary combination of binary symbols. In this case, in block 5, the adder 10 modulo two is excluded, i.e. the output of the last (nth) bit of the shift register 13 is connected to the first input of the adder 11 modulo two. Thus, for the case of a periodic binary combination of symbols, it is assumed that the node multiplying the generator polynomial consists of an n-bit shift register 13, whose information input and the output of the last bit are connected to the corresponding inputs of modulo-two.

Claims (2)

1. A device for isolating errors from a digital test signal, comprising a serially connected error corrector, the input of which is the device input, a pseudo-random sequence generator, a comparator, the second input of which is combined with the device input, and a key whose output is connected to the second input of the error corrector, characterized in that, in order to increase the reliability of error allocation by detecting slippage and interruptions in communication, a slippage detection unit is introduced, the output of which is Slippage ustoyst- are output va, and a first input connected to the output of the comparator, which is the output device errors, the input signal processing unit connected in series, the input of which is combined with the device input, and the second output are connected to the second input of the slip detection unit and the control input of the key, and the communication break detection unit, the second input of which is connected to the second output processing unit input signal, and the output is the interrupt output of the device. 2. The device according to claim 1, wherein the input signal processing unit comprises serially connected shift register, the input of which is the input of the input signal processing unit, the first modulo two, the second input of which is connected to the corresponding output of the shift register, the second modulo two, the second input of which is connected to the input of the shift register, trigger, the second the input of which is connected to the input of the shift register and the OR element, the output of which is the second output of the input signal processing unit, and the second input is connected to the counter input, the control input of which is connected to the output of the second modulo two, and the third modulo two , the first, the second inputs of which are connected respectively to the input and the corresponding output of the shift register, and the output is the first output of the input processing unit.