SU1619277A1 - Device for checking pulse trains - Google Patents

Abstract

The invention relates to automation and digital technology and is intended to test complex synchronization units, controllers, information sensors used in automated control systems, information processing, and communications. The memory size of the device is reduced by providing a one-time recording of information in the memory block for the entire packet of pulses of the monitored sequence to one of the inputs of the device, and recording in the memory block information about the dimension of the packet of pulses. The aim of the invention is to enhance the functionality by providing control of multi-bit pulse bursts. The goal is achieved by introducing a counter, an OR element, a one-shot. 2 Il.

Description

The invention relates to automation and digital technology and is intended to test complex synchronization units, controllers, information sensors used in automated control systems, information processing, and communication.

The purpose of the invention is to expand the functionality of the device by controlling multi-bit pulse bursts.

Figure 1 shows the functional diagram of the device; figure 2 - the timing diagram of his work.

The device contains a block of 1 memory of the number of pulses, the first 2 and second 3 counters, the first 4 and second 5 switches, the decoder 6, the element OR 7, the one-shot 8, the output 9 errors, the inputs 10 of controlled sequences, the input 1 write resolution, the group of inputs 12 setting the number of the controlled sequence, the group of outputs 13, 14 of the memory block 1.

Memory unit 1 is a static type ROM. It is intended for storing pulse packet sequence control programs. When the address arrives at the input of memory block 1, the input number code is generated at its output 13, which will receive the next i-th burst of monitored sequence at the next time (the code size is determined by the number n of inputs 10), and output 14 a code of a number is formed, the addition of which with the number of pulses in the packet gives a number at which

WITH

to sl

The second estimator 3 generates an overflow pulse at its output.

Counter 2 is used for recording, storing, modifying, and issuing an address for memory block 1 Recording the start address of the monitored sequence that arrives at the group of information inputs of counter 2 from device 12, takes place on the falling edge of the pulse that enters the record enable input of counter 2 s input 1 device. The address is modified by increasing the previous address by the falling edge of the pulse coming from the overflow output of counter 3 to the counting input of counter 2.

Counter 3 is designed to count the number of pulses in the i-th packet of the monitored sequence. The code (N -) (where N is the number of overflow), which enters the information input of counter 3 from output 13 of block 1 there tp, is recorded on the falling edge of the pulse arriving at its synchronous input from the output of one-oscillator 3. When a pulse arrives from the output of switch 4 on the counter input of counter 3 increases its state by one.

The switch 4 serves to generate a pulse to the counting input of the counter 3, if the incoming pulse at the device input 10 corresponds to a controlled sequence of pulse packets.

Switch 5 generates a pulse on the output 9 error, if received at one of the inputs 10 of the device does not belong to the controlled sequence.

The decoder 6, in accordance with the code received from the output 13 of the ROM 1, generates input signals to the inputs of the switches 4 and 5, which makes it possible to distinguish the pulses belonging to and not belonging to the controlled sequence.

The element OR 7 is designed to control the one-shot 8.

The latter forms on its output a pulse with a duration that provides

termination of transient processes

write address to counter 2 and read

the information on it from the ROM 1. The one-vibrator 8 generates a pulse for writing to the counter 3,

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The device works as follows.

Prior to operation, the device memory elements are set to zero. The circuit of the initial installation in FIG. 1 is conventionally not shown. In counter 2, from input 12, the starting address of the monitored sequence is recorded from the pulse received at input 11,

From counter 2, the address is fed to the input of memory block 1, from which output code 13 is read, for example 10.i, which is fed to decoder 6, and from output 14 of block 1, (N -) f code is received on the information input of the counter 3.

At the same time, the sync pulse arriving at input 11 is controlled by a single-oscillator at its output a pulse, according to which the code (N -)) from output 14 of block 1 is written into counter 3.

In accordance with the code received at the input of the decoder 6, it generates a single signal at the ith output and zero signals at the others. As a result, the 1st output signal of the decoder 6 opens the i-and information input of the switch 4 and closes the i-th information input of the switch 5.

When a packet arrives at the device input 10.i (i.e., if the controlled sequence is correctly implemented), the pulses through the switch 4 will flow to the counting input of counter 3, increasing its state by one. When the last v pulse of a packet arrives at the output of counter 3, an overflow pulse is generated, according to which counter 2 increases its state by one. In accordance with the new address from unit 3 exit

13 on the inputs of the decoder 6 is considered the code number of the input, which should receive the next packet of pulses (for example, input 10.J), and from the output

14- on the information inputs of the counter 3 code (N - 1).

An overflow pulse from the output of the counter 3, received through the element OR 7 to the input of the one-shot 8, will generate at its output a pulse, using which a code (N - 1) is written to the counter 3.

5J

If the controlled sequence is distorted and the next impulse is received at another input (for example 10.K), then this impulse will not pass to the output of switch 4, and through the switch 5 will arrive at output 13 of the device and generate an error signal (Fig. 26).

If simultaneously with a pulse arriving at the input, in accordance with the controlled sequence, a pulse not belonging to the controlled sequence arrives at any other input, this impulse will still pass to the output of the switch 5 and will generate an error signal at output 9.

At the end of the controlled sequence from block 1, zero codes will be read from outputs 13 and 14. As a result, all the outputs of the decoder 6 will have zero signals, and the switch 5 will be open to all inputs. Therefore, any pulse received at the inputs 10.1-10.p device will generate an error signal at the output 9 of the device

Claims (1)

Invention Formula A device for controlling pulse sequences containing a memory block of the number of pulses, a first counter, two switches and a decoder, the i-th information input (i 1, ..., n, where n is the number of monitored device sequences) of the first switch connected to i is the second information input of the second switch and is the ith input 0 five 0 2776 the controlled sequence of the device, the group of outputs of the number of the controlled sequence of the device is connected to the group of information inputs of the decoder, v. the decoder moves are connected respectively to the control inputs of the first switch and respectively to the inverse control inputs of the second switch, the output of which is the error output of the device, characterized in that, in order to expand the functionality of the device by controlling multi-bit pulse bursts, into it the second counter, the OR element and the one-shot are entered, the group of the bit outputs of the first counter is connected to the group of address inputs of the memory block of the number of pulses, the write enable input and the first counter is connected to the first input of the OR element and is the recording enable input of the device, the output of the OR element is connected to the input of the one-oscillator, the output of which is connected to the recording enable input of the second counter, the overflow output of which is connected to the counting input of the first counter and the second input of the OR element, the group of outputs of the number of pulses of the monitored sequence of the memory block of the number of pulses is connected to the group of information inputs of the second counter, the output of the first switch is connected to counting input of the second counter, the group of information inputs of the first counter is a group of inputs the job number ustroystvl controlled sequence. five 0 five 0