SU1615703A1 - Series one-digit binary adder - Google Patents

Abstract

The invention relates to computing and can be used in computer processors and other devices for processing discrete information, for example, in devices of discrete automation and preprocessing of measurement information. The purpose of the invention is to expand the field of application by providing self-timed operation. The adder contains the inputs of 1 paraphase codes of the discharge values of the terms, three AND-OR-NOT 2,3,4 elements, two AND-NOT 5 and 6 input elements, two pairs of AND-NOT 7.8 auxiliary elements and AND-OR-NOT 9 and 10, and the outputs of the paraphase discharge code of the sum of 11 and 12. 1 Il.

Description

telsch g-is computed °. : computer processors and others: Discrete processing devices. Formations, for example, in devices of discrete automatics and preliminary S: Z measuring instruments. The purpose of the invention is the expansion of the field of application of consecutive one-digit binary adders by ensuring self-synchronization. mode of operation.

 Nalk / is represented by a function If of a serial one-I bit binary adder. I A sequential one-bit split | Binary adder contains direct and (p-raFazny) inputs of 1 weak | HEMs, three elements of AND-RSHI-TsE 2 - i two elements-NOT 5 and 6, the first trigger containing two elements AND 1 7 and 8. The second trigger, containing two elements I-SHI-NOT 9 pr

: s yy ° - p-b, g

Zykod 12 devices, and the inputs of the first element AND-OR-NOT 2 are connected to the inputs 1 of the device so that one group of inputs of the element H-IOTi-HE is connected to the first three and second inverse, inputs t |: lagged , the second group of inputs of the element I-SHSh-NOT is connected to the first inverse and second direct inputs of 1 Addendum.

: The operation of the adder occurs in the Responsive Request-Response, with .this sum- .top can be in two states: | ix: idle and working, and each of these states can be projected into any an arbitrary time instant according to the results of the analysis of the ratio of the values of the input and output variables. Denote the inverse inputs of 1 adder by a and b, and n | r mye - by a and b. The direct output 11 of the adder will be denoted by, and and | the reverse output 12 - by S / B the initial non-working state of the sum of its inputs and outputs; the values of the signals correspond to the non-working code of OTHER combinations of input and output: O O 2G S Oh, which in the following name the spacer. Consequently, the presence of 7 subchannels at the input and output of the summa- ness indicates the idle state of the adder and its readiness for

1615703

ten

15

20

25

thirty

35

40

45

0

five

receiving input information and its conversion. The supply of working code combinations corresponding to some bit values of the summands to the input of the adder (a b) initiates the start of the adder into the phase of setting up a working state for which the unambiguous sign is the absence of a spacer at the input and zero at the output of the adder; 2 The setup phase lasts until the output signal .f 2 is obtained, after which the adder goes into a working state. Resetting the input signals of the adder into the spacer leads to the beginning of the quenching phase of the working state. A sign of this phase is the spacer on the adder and the output signal. After the blanking phase is completed, the adder returns to its original inoperative state with zero spacers in the input and output and is ready to receive and convert information in the next business cycle.

The adder works as follows.

For convenience, we denote the outputs of the first and second input elements AND-NOT 5 and b, respectively, through z and. At the output of the first element AND-OR-NOT 2 - through C. Let us also assume that the logical functions (x, x) are implemented at the outputs of the AND-HE elements 8 and 7 of the first pair of auxiliary elements. For these variables, the following functional dependencies are valid:

W; 2 AG, C (awfb).

The state of the first RS-flip-flop, formed by the first pair of auxiliary elements I-HE 7 and 8 (x, x)

(0,1) can change on one and only one set of values of input variables: a b 1. In this case, the value of variable y is reset to O, which causes the variable X to be set to 1, and the trigger switches to the ( x, x)

(1.0). On all other sets of values of input variables (a - b a b) the state of the trigger (x, x) (0,1) remains unchanged. Another initial state of the trigger (x, x) (1.0) can change only on the input set of bit values of the components a b 0, i.e. with a - b 1. With this variable

5161

the output of the element AND-HE 5 takes the value O, and the trigger switches to the state (xD) (0.1). Consequently, at the outputs of the first pair of auxiliary elements, AND-HE 8 and 7, the value of the logical function is formed.

X, PGVab X,

where X is the value of the transfer signal to the highest bit of the sum, obtained by the bit values of the terms, taking into account the magnitude of the transfer signal from the lower bit of the sum P. Thus, the trigger on the first pair of auxiliary elements IS-NE 7 and 8 stores the value of the transfer signal from the lower bit of the sum when the spacer is at the input of the adder, and when applying a certain set of digit values of the terms and switching the adder to the working state, the new transfer signal is generated and stored in the high bit of the sum. At the same time, the xy and kz conjunctions generated at the inputs of the AND-ShZH-NE 3 and 4 PS elements are the values of the output signals of the AND-HE elements 7 and 8 and the AND-NE elements 5 and 6, in the idle state of the adder, respectively: xy P and XZ p, since y Z 1, and upon transition of the adder to the working state, take the values xy JP6 V ab) (ab) Pb and XZ (reVab) (ab) PCj.

The second trigger is formed by the second pair of auxiliary elements.

AND-ILY-HE 9 and 10. In the idle state of the adder, the state of the second trigger is always inverse with respect to the state of the first trigger on the first pair of auxiliary elements AND-HE 7 and 8. Its output signals P from the output of the AND-OR element NOT 9 and P from the output of the element AND-OR-NOT 10 are fed to the inputs of the corresponding groups of inputs AND of the element AND-OR-NOT 4 and 3, the second inputs of which receive the signal Cj from the output of the AND-OR-NOT 2 element. conjunctions of the form 0 FG and A P {J. In the idle state of the adder, the indicated conjunctions take the values P, fo P, since tf 1.

Thus, for the outputs of the AND-OR-HE elements 3 and 4, you can write

57036

the following expressions: for idle., adder state

 Hu PVP 0,

  xzV06 PVP O, and for the operating state of the adder

ten

S xy V i PGVPG,

  xz Vo6 РБУРСГ.

Consider the operation of the adder when applying, at its input, different values of the bits of the components and at different initial states of the first and second triggers corresponding to the single and zero values of the stored transfer signal. When applying the bit values of the terms such that a b, starts after setting the working state of the adder. The values of the variables z and y at the outputs of the input elements AND-NOT-5 and 6 do not change their single value. The value of CJ output of the signal of the I-11PI-HE 2 element changes. It takes the value 0. This leads to a change in the signals and inverse outputs of the adder, since the output signal of the AND-OR-HE 3 and 4: 2 P, 2 P elements changes, i.e. for the stored value of the transfer signal (PiP) - CjO) the output signal of the 2 O and 2: 1 adder, for (P, P) (0.1) 321, the output signals S and

 ABOUT.

In any case, the stored value of the transfer signal remains unchanged. The output signal output, S 7 S, completes the phase of setting the adder to a working state, which for various values of bits has a length of 0

, a and b

2t, where is the delay time of one logical element. Resetting the inputs of the adder into the spacer will initiate: the beginning of the quenching phase, during which a single value of the variable J is restored at the output of the AND-OR-NOT 2 element, which causes the output signals of the AND-ILI-HE 3 and 4 elements to be reset to the spacer, and therefore and output adder: 2 O u2 0.

The accumulator returns to its original non-operating state. The quench phase continues. Fully working

five

| Adder's cycle for a b b is 1–2 2C time.

I Assume that the zero-bit values of the following are entered into the input of the adder: 1. The phases, and the first setting starts with switching the input element AND-NOT 5 and resetting the value of the variable in O, and C at the outputs of the elements AND-NOT 6 and AND-OR-NOT 2 remain equal to 1 fees change. How will ZO affect the state of the first trigger unambiguously determined by its initial state (x, x). If the initial state is the zero state (x, x) (0.1), which corresponds to the storage of the zero value of the transfer signal (P, P) "(0.1), the value of | O does not cause a change in the - | then neither the elements AND-NOT 7 and AND-OR-NOT 9 of the first and second triggers on the first and second pairs of auxiliary elements. Both triggers remain in their initial states. At the same time, z h О leads to the fact that all input | conjunctions of the AND-OR-NOT 4 element accept zero values, causing the switching of this element to 1. On

When a unit of unit bit inputs of the components a b 1 0 arrives at the input, the states of the AND-NE 5 and AND-OR-HE 2 elements do not change, the values of the variables z and О remain equal to 1. The installation phase begins with the switching of the element 25 AND- NOT 6 and reset in O the value of the variable y: y O. If the initial state of the first trigger corresponds to a single value of the stored transfer signal (x, x) (1,0), reset

The output of the adder is set to the signal in O. The value of the variable is not 1al 2al and 2: 1, because the output of the state on the first Noah of the signal of the AND-OR-NOT 3 element remains unchanged. The installation phase lasts in the phase of quenching, and the second trigger occurs. They remain in their original state. At the same time, with O, it turns out that all

| resetting the initial input conjunctions of the AND-OR-NOT element

DGNTA S g nnr) and Ai 9 11 ". . ".. .. l

i-NOT 5 with recovery z 1 1 Conjunction xz takes the value 1, which causes a reset to O of the output signal of the AND-OR-NOT element 4. The output of the Totalizer goes to the zero spacer. Quench Phase Duration 2. The total operating cycle of the adder 2C - 2,

If the first trigger is in the state (x, x) (1,0) and a b

3, and it switches to state 1. At the output of the adder, a signal S 1 and 2 0 is set. The installation phase lasts 2 s. The quench phase includes dd the restoration of the initial state of the element AND-NOT 6 and the variable y in the value 1. If y 1, a reset occurs. About the AND-OR-NOT element 3 and the output of the adder to the zero spacer.

O, the transition of the variable z to O-call-D5 The quenching phase continues. Flying switching element AND-NOT 7 to 1, the total duty cycle of the adder 2 2 + 2f Which leads to a change in the original

If at y O it turns out that the initial state of the first trigger (x) (0,1), i.e. stored at zero 5Q ° s value of the carry signal, ele. The IE-NE 8 switch to state 1 and causes the first trigger to switch to state (x, x)

. -. ™ (). The state of the second trigger in the state (x, x) (0.1) of the time remains unchanged, and all conjunctions are zeroed for the time being switched off.

the zero value of the variable y. The new state of the first trigger (x, x) of the state of the first trigger, which transitions to the state (x, 1c) (0.1). The specified switching of the first trigger does not cause the switching of the second trigger due to the blocking effect of the zero value of the re-; men1 | oh Z. Locking the first trig; the input element AND-OR-NOT 3 and the output of the adder signal is set

, E: 1 and 2 0.

 o 0) / causes all

0

 The installation phase is completed in Ab time. In the blanking phase, the initial state of the AND-NOT 5 element is restored, J is variable z takes the value I, which causes the second trigger to switch to the new state: the AND-OR-9 element switches to O, which causes the setting to 1 AND-OR -NE 10. The second trigger enters the state (P,) "(0,1). The new state of the second flip-flop leads to a reset in O of the signal at the output of the AND-OR-HE 3 element, and the zero spacer is set at the output of the adder. The quench phase continues. 4. Full operation cycle of the 4C adder.

When a unit of unit bit inputs of the components a b 1 0 arrives at the input, the states of the AND-NE 5 and AND-OR-HE 2 elements do not change, the values of the variables z and О remain equal to 1. The installation phase begins with the switching of the element 5 AND- NOT 6 and reset in O the value of the variable y: y O. If the initial state of the first trigger corresponds to a single value of the stored transfer signal (x, x) (1,0), reset

five

0

o in o the value of the variable does not affect the state of the first

The value of the variable does not affect the state of the first

and second triggers. They remain in their original state. At the same time, with O, it turns out that all

input conjunctions of an AND-OR-NOT element

input conjunctions of an AND-OR-NOT element

one ". . ".. .. l

3, and it switches to state 1. At the output of the adder, a signal S 1 and 2 0 is set. The installation phase lasts 2 s. The quench phase includes the restoration of the initial state of the element AND-NOT 6 and the variable y in the value 1. If y 1, the reset of the AND-OR-NOT 3 element and the output of the adder into the zero spacer occurs.

The quench phase continues. Full adder cycle 2 2 + 2f

the zero value of the variable y. H state of the first trigger (x, x)

 o 0) / causes all

the input conjunctions of the AND-OR-NOT 4 element are set to O and its code switches to 1. At the output of the adder, the signal O n - 1 is set. The installation phase is time 41. The blanking phase begins with the restoration of the initial state of the element AND-NE 6, at which I. This causes the switching of the state of the second trigger: the AND-OR-HE element 10 switches to O, which causes the setting to 1 I-1SHI-NOT 9 element and switching the second trigger to the state (P, P) (1,0). Switching the second trigger triggers a new input conjunction (J of the AND-OR-NOT 4 element, and its output signal switches to O. The output signal of the adder is reset to the spacer. Quench phase lasts for the full operating cycle of the adder

4 2r 4C + 4

Claims (1)

Invention Formula A sequential one-bit binary adder containing inverse and direct inputs of the paraphase codes of the summand components, the first and second AND-OR-NOT elements, and the inputs of the first AND-OR-NOT element are connected to the inputs of the adder in such a way that one group of the first inputs - of the first element I-IZH-NOT connected to the first direct and second inverse inputs of the terms, the second group of inputs of the first element AND-OR-NOT connected to the first inverse and second direct inputs of the components, the output of the first element AND-OR- NOT - with the first entrance of the first group moves the second AND-OR-NO element whose output is connected to a direct output of the adder, characterized in that, in order to expand the application area five 0 five about Q five due to the provision of self-synchronous ..., the mode of operation, the adder contains the third element AND-1SHY-NOT, two elements H-NOT, the first trigger containing two elements AND-NOT, the second trigger containing two elements I-IL1 -NE , moreover, the output of the first and second elements AND-NOT of the first trigger is connected to the first input of the second and first elements, respectively, AND-NOT of the first trigger, the output of the first and second elements AND-OR-NOT of the second trigger, Hera is connected to the input of the first group of inputs of the second and second respectively the first element AND-OR-NOT the second trigger, the first and the second inputs of the first and second elements AND-NOT are connected respectively to the inverse and direct inputs of the adder's components, the outputs of the first and second elements AND-NOT are connected to the second input of the first and second elements, respectively, AND-NOT of the first trigger, s, first the input of the second group of inputs, respectively, of the first and second elements AND-OR-NOT of the second trigger and with the first input of the second group of inputs of the third and second elements AND-OR-NOT, respectively, the output of the first and second g elements of the first trigger is connected to the second input of the second a group of inputs of the first and second elements I-1-CHI-NO of the second trigger, respectively, and with the second input of the second group of inputs of the third and second elements AND-OR-NE, respectively; the output of the first and second elements I-1I-NO of the second trigger is connected to the second input of the first group of inputs, respectively, of the third and second elements AND-OR-NOT, the output of the first element AND-OR-NOT is connected to the first input of the first group of inputs of the third Element AND-OR-NOT. the output of which is connected to the inverse output of the accumulator.