SU1610279A1 - Digital recorder of recurrent signals - Google Patents

Abstract

The invention relates to the field of instrumentation and can be used to measure amplitude and time parameters of repetitive signals in a wide frequency range. The goal - improving measurement accuracy - is achieved by introducing into the device a comparators, a "fast" sawtooth generator, reference voltage sources, a source follower, a multiplexer, counters, amplifier, trigger, digital-analog converter, and OR and OR-NOT elements, as well as related links. 4 il.

Description

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The invention relates to instrument engineering and can be used to measure amplitude and time parameters of repetitive signals in a wide frequency range.

The purpose of the invention is to increase the accuracy of measurement of repetitive signals.

FIG. 1 shows a block diagram of a digital recorder; in fig. 2 is a block diagram of the control device; in fig. 3 — generator, forming a fast saw-tooth voltage — in FIG. 4 - time diagrams that show the operation of a digital recorder.

The block diagram of the recorder is shown (Fig. 1) contains an attenuator 1, a sampling and storage device

2, analog-to-digital converter

3, storage register 4, memory 5, address counter 6, control digital-to-analog converter 7, control device 8, first comparator 9, counter 10, generator of a fast sawtooth voltage 11, trigger 12, element OR 13, multiplexer 14, code counter - analog converter 15, digital-to-analog converter 16, amplifier 17, second comparator 18, bus Analog input 19, Start bus 20, signal bus Read 21, Reset signal bus 22, digital information output of recorder 23, analog information output od 24 Ready signal bus 25 and bus synchronization signal Level 26, wherein the input attenuator 1 is connected to the bus 19, an analog input, and the output to the input sampling device and the storage 2 and the non-inverting input of the first comparator 9, the output sampling device and storing

2 is connected to the analog input of the analog-digital converter 3, the control input of the storage sampling device 2 is connected to the output 2 of the control device 8, the control input of the analog-digital converter 3 is connected to the output 3 of the control device 8, I14) the output output of the analogue the digital converter 3 is inputted to the data of the storage register 4, and the control input of the latter is connected to the output Data readiness of the analog-digital converter 3 and simultaneously with the input 3 of the control device 8, and the information output storage hub 4 is connected to the data input of memory 5, the address input of memory 5 is connected to the output of address counter 6 and to input 4 of control device 8, the counting input and input of zero setting of address counter 6 are connected to outputs 2 and 5 respectively of control device 8 , the information output of the memory device 5 is connected simultaneously with the digital input of the Control digital-to-analog converter 7 and to the bus 23 The digital output of the recorder, the output of the digital-to-analog converter 7 is connected to the bus 24 Analog output of the recorder, a control / write / memory control input 5 connected to the output 4 of the control device 8, inverting the first input of the first comparator 9 is connected to the bus 26 A synchronization level and its control input connected to the output 1 of the control 8, the output of the comparator 9 is set to the counting input of the counter 10, and the control input of the latter is connected to the output of the multiplexer 14, the output of the counter 10 is connected to the input T of the control device 8 and to the input 1 of the fast sawtooth generator 11, and the input 2 p the last one is connected to the output of the trigger 12 and at the same time the same output of the trigger 12 is connected to the counting input of the code counter of the digital-analog converter 15, to the first information and control inputs of the multiplexer 14, the inputs of the unit to the single and zero state of the trigger 12 are connected, respectively, to the outputs 2 and 3 fast sawtooth generators

11 and at the same time the output 3 of the latter is connected to the second information input of the multiplexer 14, and video 1

the generator of the fast sawtooth voltage 11 is connected to the non-inverting input of the second comparator 18, the inverting input of the latter is connected to the output of the amplifier 17, and the input

the latter is connected to the output of a digital-to-analog converter 16, the digital input of which is connected to the output of the counter of the code of the digital-to-analog converter 15, and the control

the input of the latter is connected to the output of the element OR 13, the inputs of the element of RSHI 13 are connected - one to the output 5 of the control device 8, and the other to the output of the overflow of the code counter

digital-to-analog converter 15, the output of the second comparator 18 is connected to input 2 of control device 8 and, finally, inputs 5, 6 and 7 of control device 8 are connected respectively to buses Reading 21, Start, 20 and Reset 22, and output 6 of control device 8 is connected to Bus Ready 25.

The control device 8 (FIG. 1) can be implemented according to the scheme shown in FIG. 2, and includes in the trigger 27, an OR-NOT 28 element, a recording pulse shaper 29j an element OR 30, a counting pulse shaper 31, a backstop element

32, pulse shaper reset

33, an end-of-write pulse driver 34, a final address register 35, a comparison element 36, wherein the setup input to the trigger state 27 is input 6 of the control device and connected & bus 20 Start, and the reset input of the trigger 27 is connected to the output of the pulse former Reset 33, simultaneously the output of the latter is the output 5 of the control device 8, the inverse output of the trigger 27 is connected to the input of the OR-HE element 28, and the other input

f of the latter is the input 1 of control device 8, the direct output of trigger 27 is connected to the inputs of the write pulse drivers 29 and the write end 34, the output of the OR-NOT element 28 is the output 1 of the control,. and the second input of the write pulse generator 29 is the input 3 of the control unit 8, the output of this generator 29 is the output 4

the control unit 8, the inputs of the element OR 30 are connected to the inputs 2 and 5 of the control device 8, and the output to the input of the counting pulse generator 31, and the output of the latter is connected to the output 2 of the control unit Hang the input of the delay element 32, and the output of the last one is output 3 of the control unit 8, one of the inputs of the pulse former Reset 33 is the seventh input of the control device 8, and the other is connected to the output of the driver 16102796

strokes 3 and 2 of the generator of the sawtooth voltage 11, the input 1 of the generator of the fast sawtooth voltage 11 is the control for the keys S4 and S3, the key block 41, the latter is controlled through the inverter 42, respectively, the input 2 of the generator of the fast sawtooth 11, Q control for keys S2 and through inverter 43 for S1 key block 41.

The registrar works as follows.

After switching on the voltage of the write end of the write end 34, the output of the last, 5th signal and a signal reset to the bus

it is the output 6 of the control device 8, the input 4 of the control device 8 is connected to the input of the comparison element 36, and the other input of the latter is connected to the output register of the final address 35 and finally, the output of the comparison element 36 is connected to the input of the imager pulse end of record 34. I

The generator of a fast sawtooth voltage 11 (fig. 1) can be implemented according to the scheme shown in fig. 3, and includes a source of discharge 37 of capacitance C1, a source of reference voltage -ZV 38, a source of reference voltage + ЗВ 39, a source of charge 40 of capacitance C1, keys 4 1, inverters 42 and 43, a source follower 44, and also the third 45 and fourth 46 comparators, the output of the source of discharge 37 is connected via keys S1 and S2 of the key block 41 to the output of the reference voltage source -ZV 38 and to the capacitance C1, respectively, simultaneously the output of the reference voltage source -ZV 38 is connected to the inverting the input of the third comparator 45, the output of the voltage source ZV 39 is connected simultaneously via the key S3 of the key block 41 to the output of the source of charge of capacitance 40 and to the inverting input of the fourth comparator 46, in addition, the output of the source of charge 40 through the key 84 of the block of keys 41 is connected to capacitance C1 and to the input of the source repeater 44, the output of the source repeater 44 is connected to the non-inverting inputs of the third

20

25

thirty

22 to the input 7 of the control device 8 (FIG. 1) and, accordingly, to the pulse shaper Reset 33 (FIG. 2), the latter generates a pulse of a predetermined duration, which is triggered by the trigger 27 (FIG. 2), and coming from output 5 The control device 8 (Fig. 1) at the input of setting the address counter to zero to zero and through the WN 13 element to the input of the counter of the D / A converter 15, sets them to the initial (zero) state. A start signal then arriving at the 20 Start to input 6 of the control device 8 triggers the trigger 27 (FIG. 2), thereby initiating the recorder operation in the recording mode. At the direct output of the trigger 27, a logical unit is set enabling the drivers 35 of the write pulses 29 and the end of the recording 34. A logic zero is set at the inverse output of the trigger 27, which, arriving at one of the inputs of the OR-NO element 28, sets at output 1 of the control device 8 (FIG. 1) the level of the logical unit, which, acting on the control input of the first comparator 9, permits its operation, i.e. the strobe pulses are generated at the moments of signal transition through the level of the reference voltage, set by bus 26; synchronization level.

FIG. Figure 4a shows the analog input signal to the non-inverting input of the first comparator 9, where it is compared to the synchronization level voltage and implemented.

45

50

45 and the fourth 46 comparators and its transition points at a given time is output 1 gene level, as shown in fig.4b. By

the nth signal coming from the output of the comparator 9 to the input of the counter 10,

Rotor fast ramp voltage 11, the outputs of the data of the comparators 45 and 46 are respectively the output of the latter formed by the CHI-

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strokes 3 and 2 of the generator of the sawtooth voltage 11, the input 1 of the generator of the fast sawtooth voltage 11 is the control for the keys S4 and S3, the key block 41, the latter is controlled through the inverter 42, respectively, the input 2 of the generator of the fast sawtooth 11, Q control for keys S2 and through inverter 43 for S1 key block 41.

The registrar works as follows.

After switching on the voltage of the pit, 5 and giving a signal Reset on the bus

, 5 no signaling and bus reset

20

five

0

22 to the input 7 of the control device 8 (FIG. 1) and, accordingly, to the pulse shaper Reset 33 (FIG. 2), the latter generates a pulse of a predetermined duration, which is triggered by the trigger 27 (FIG. 2), and coming from output 5 The control device 8 (Fig. 1) at the input of setting the address counter to zero to zero and through the WN 13 element to the input of the counter of the D / A converter 15, sets them to the initial (zero) state. A start signal then arriving at the 20 Start to input 6 of the control device 8 triggers the trigger 27 (FIG. 2), thereby initiating the recorder operation in the recording mode. At the direct output of the trigger 27, a logical unit is set to enable the drivers of 5 write pulses 29 and the end of recording 34. At the inverse output of the trigger 27, a logical zero is set, which, arriving at one of the inputs of the OR-NO element 28, sets at output 1 of the control unit 8 (FIG. 1), the level of the logical unit, which, acting on the control input of the first comparator 9, permits its operation, i.e. the strobe pulses are generated at the moments of signal transition through the level of the reference voltage, set by bus 26; synchronization level.

FIG. 4a shows the analog input signal to the non-inverting input of the first comparator 9, where it is compared to the synchronization level voltage and can be converted

five

0

5 cops go through the specified level, as shown in figb. By

the nth signal coming from the output of the comparator 9 to the input of the counter 10,

at the end of the last CHI- is formed

logic unit, which is fed to the input 1 of the generator of a fast sawtooth voltage 11 and to the input 1 of the control device 8, where this signal goes to one of the inputs of the OR-NOT 28 elements (FIG. 2), while the output of the OR-NOT element 28 and respectively at the exit. 1, the control unit 8 (FIG. 1) appears at a logic level zero, prohibiting the operation of the first comparator 9. At the same time, the signal from the output of the counter 10 to the input 1 of the generator sawtooth 11 controls the keys S4 and S3 - key block 41 (fig.Z). At the moment of entering the level of the logical unit, the S4 key closes and the linear source starts from the charge source 40; The charge of capacitor C1 (Fig. 4d), -key S3 is controlled by the same signal, but through inverter 42, and, therefore, it is opened. The linear signal taken from capacitance C1 through the downstream repeater 44 enters the non-inverting input of the comparator 45 and 46, as well as the output 1 of the fast sawtooth generator 11 (figure 1), and from there the non-inverting input of the second comparator 18 At the moment when the signal at the output of the source follower 44 (FIG. 3) reaches + 3V, the fourth comparator 46 will operate, and accordingly, at its output and output 2 of the fast sawtooth generator 11, the level of the logical unit (FIG. .4d), this signal is input installation in a single state of the trigger 12 (figure 2), raises it and right there from its output enters the input 2 of the generator of a fast sawtooth voltage 11 and switches the keys S2 and S1 of the key block 41 (FIG. 3), and the logical level unit closes key 2 and, via an inverter 43, opens the key .S1, capacitance C1 is quickly discharged through the discharge source. the capacitor 37. The output signal from the trigger 12 (Fig. 1) is also fed to the multiplexer 14, generating a control signal for the counter 10, which resets it to the zero state, and since the output signal of the counter 10 controls the keys S3 and S4 (Fig. 3) of the generator of a fast sawtooth voltage 11, then, therefore, the key S3 will be closed, and the key 84

open, i.e. The strb-pulse shaping circuit will be ready for the arrival of a new trigger pulse.

In addition, at the time of actuation

trigger 12 (FIG. 1) each time a pulse arrives at the input of counter 15, which increases its output code by one, increasing the counter code of the digital-to-analog converter 15

leads to the formation of a digital-to-analog converter 16 at the output stage and this signal is amplified by the amplifier 17, each time increasing the reference voltage — at the inverting input of the comparator 18. Thus, c. The next cycle the moment of strobe formation will be shifted to / itc (fig.4g). From the output of the comparator 18 strobe-pulse act5

0

0

em to control device input 2

8, where the element OR 30 (FIG. 3) is fed to the shaper of the counting pulse 31, the pulse from the output of the last is fed to the output 2 of the control device 8, from the output 2 of the control device 8 (FIG. 1) this pulse goes to the control input of the device sample and store 2 and to the counting input of the address counter 6, and through 5 the delay element 32 is fed to the start input of the analog-to-digital converter 3. In this case, the next address code of the memory cell 5 is generated,

5 which is set to its address entry. By the signal End of conversion from analog-to-digital converter 3, input to the control of the storage register

40 4, the conversion result code is entered into the last one and at the end of this signal is set at the information input of the memory device 5.

45

Claims (1)

Invention Formula  A digital recorder of repetitive signals containing a series-connected attenuator, a sampling and storage device, an analog-to-digital converter, whose information output is connected to the information input of the storage register, and the output of the latter to the information input of the storage device, an address counter connected to the address input of the memory device whose output is digital The recorder has a smooth information output and is simultaneously connected to the input of a control digital-analog converter, the output of which is an analog information recorder output, characterized in that, in order to improve the measurement accuracy of repetitive signals, two comparators, a control device, a counter, an OR element, fast sawtooth generator, multiplexer, trigger, digital-to-analog converter code counter, digital-to-analog converter and amplifier, and non-inverting input voltage One of the first comparator is connected to the output of the attenuator, a. the inverting input of the first comparator is connected to the signal bus of the synchronization level, and its output is connected to the counter input of the counter, the control input of which is connected to the multiplexer output, and the output of the counter is connected to the first control input of the fast sawtooth generator and to the first input control device, the first output of the fast sawtooth generator is connected to the non-inverting input of the second comparator, and the output of the amplifier is connected to the inverting input of the second comparator, and the output of the second comparator is connected to the second input of the control device i; the second output of the fast sawtooth generator is connected to the installation input to the unit trigger state; the output of which is connected to the second control input of the fast sawtooth generator, to the first information and control inputs of the multiplexer, as well as to counting input code counter digital five Yu 0 five 0 five 0 the analog converter, the second information output of the multiplexer and the setup input to the zero state of the trigger are connected to the third output of the fast sawtooth generator, the input setting to the zero state of the code counter of the D / A converter is connected to the output of the IZH element, one input of which is connected to the overflow output of the code counter digital-to-analog converter, and the other input - with. the fifth output of the control device, the information output of the code counter of the digital-analog converter is connected to the information input of the digital-to-analog converter, the output of which is connected to the amplifier input, the first output of the control device is connected to the control input of the first comparator, the second output of the control device is connected to the counter input of the counter the address and control of the input of the sampling and storage device, the third output of the control device is connected to the trigger input of the analog-digital converter, output Data readiness of which is connected to the control input of the storage register and to the third input of the control device, and the fourth input of the latter is connected to the information bus of the address counter, the fourth output of the control device is connected to the write / read control input of the storage device, five output from the setpoint About the address counter, and the sixth output is connected to the Ready signal, the sixth input of the controllers is connected to the Start-up, fifth to the bus. Reading and the seventh input of the control devices — to the bus. grew up 35 Fi.Z