SU1608694A2 - Device for information searches - Google Patents

Abstract

The invention relates to computing, and can be used in automated information and reference systems. The purpose of the invention is to increase the reliability of the device by reducing information loss. The device contains registers, decoders, memory blocks, pulse distributors, triggers, summing counters, reversible counter, OR elements, AND elements, delay elements. The device has first and second information inputs, a synchronization input, an address read input, an address record input, a group of request inputs, a poll input, a write enable input, a start input, an information output, a group of information outputs, a result readiness output. 3 il.

Description

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retention relates to computing technology, can be used in automated information-reference systems and in the improvement of the device IIBT.CB. No. 1399768.

invention - povyshenie na and devices at the expense of shortening information, fig. 1 shows the structure of the device; in fig. 2 - pn scheme of the first distribution of pulses; in fig. 3 - structure of the second distributor

cx (; ma

pulses

Responsible 1, First 6, 9 and n

The device (Fig. 1) contains the first second 2 and third 3 registers, 4 and second 5 decoders, the first second 7, third 8, fourth UY 10 memory blocks, the first 11

and second 12 pulse distributors,: first 13, second 14 and third 15 triggers, first 16 and second 17 summing counters, reversible counter 18, first 19 and second 20 elements OR, first 21, second 22, third 23, fourth 24, P 25th and 6th, 26 elements AND, the first, second and third groups of elements OR 27 - 29, the first, second, third, fourth and fifth groups of elements AND 30 - 35,

the first 36, the second 37, the third 38, the fourth., the third 39, the fifth 40, and the sixth 41 delay elements. The diagram (Fig. 1) also shows the first 42 and the second 43 in-. Formational inputs, syncP1 input 44, address reading input 45, address recording input 46, query input group 47 and 48, polling input 49, input

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50 write resolution, start input 51, information exit 52, group of information outlets 53 and 54, and exit 55 recognized the result readiness (nodes and elements of the distinguishing part

g

The proposed device is circled in FIG. 1 dotted line).

In addition, FIG. 1 shows the enable input 56, the group of setup inputs 57, the clock output 58, the first 59, the second 60, the third 61, the fourth 62 and the fifth 63 clock outputs and the group of clock outputs 64 of the first pulse distributor 11, the clock input 65, a group of setup inputs 66, a clock output 67, a group of readout resolution outputs 68, the first 69 and the second 70 clock outputs: the second pulse distributor 12 pulses.

The first pulse distributor 11 (Fig. 2) contains a pulse generator 71, the first 72 and second 73 elements AND a group of elements H 74 and 75, the first 76 and second 77 elements OR, three delay elements 78 - 80. The second dispenser 12 pulses (Fig. 3) contains a group of triggers 81 and 82, a group of elements And 83 and 84, element And 85, element OR .86, two elements 87 and 88

delays. one

one

Inputs 43 and 44, the device is connected to the data transmission path between the control objects of a complex automated control system.

Messages written to register 1 contain attribute and information parts. Part of the signs classifies the information part.

The device works as follows.

The operation of the device in which register 1 is connected to the data transmission path begins with the arrival at the input

51 start pulse, which through the OR element 19 passes to the input of the installation in 1 flip-flop 13, sets it to one state. A high potential from the direct output of the trigger 13 is fed through the input 56 of the first pulse distributor to the first input of the element I 72, to the second input of which the output of the generator 71 pulses is connected.

The first pulse from the generator 71 passes through the element AND 72 and further through the element OR 76 enters as

0

five

0

five

0

five

0

five

0

five

output 59 of the first pulse distributor and at the inputs of the elements

And 73 - 75. Considering that trigger 14 is in the initial state, its forward output will have a low potential, which blocks the passage of a pulse from output 59 through element 21. And elements 73 and 75 are connected to the outputs of the decoder 4, high potential on one of the output tires which determines the state of the indicated elements.

Assume that no messages were received from the data transmission path to register 1, then the decoder 4 will fix its state by issuing a high noTeHiyiana to the first of the inputs 57 of the distributor 11 pulses, and this high potential opens element 73 and one. pulse generator 71 from the output of the element OR 76 will pass through the element AND 73 to the output 61 of the distributor 11 pulses and then through the element OR 19 to the input of the installation in 1 trigger 13, confirming its single state.

Since the trigger 13 with a high potential keeps the AND 72 element in the open state, the pulses of the generator 71 continuously poll the states of the AND 73 - 75 elements.

As soon as a message code is recorded in register 1, the decoder will record this moment with a high potential at one of the outputs. Suppose a high potential arrived at the second of the inputs 57 of the distributor 11 pulses. This potential opens element 74, through which the generator pulse 71 from the output of the OR element: 77 passes both to the first of the outputs 64 and through the element OR 77 and the delay element 80 (on which the pulse is delayed by the sampling time of the memory unit 7) to the output 63 of the distributor 11 pulses and further to the input of the installation in the O of the trigger 13, resetting it to the initial state.

From the output 64 of the distributor 11 pulses, the polling pulse arrives at the input of the fixed cell of the memory block 7, made in the form of a persistent memory, where the initial address of the memory zone where the input information from the register 1 is to be stored. The content of the fixed cell is rewritten

with rest

limiter

to register elements

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delays.

On This And 21

impulse from output 63; 11 pulses from block 7 2, the outputs of which through ШШ 27 are connected to the discharge of the input of block 6. The parallel impulse from the output of the element

the time of the formation of the address in pe 2 2 delayed by the element, from the output 62 of the distributor of the coils, is fed to the input of record 6, recording the input message at the specified address ..; le recording the message is the same name from the output of element 79, being

at element 78, for the time I of the message, in block 6, the installation enters the initial state — registrar 2 and trigger 14, and an interrogation of the state ITOB I 73-75.

Would: sod block 6 through output 52 of the connection with the computer complex of the control object (not shown) continuously at a predetermined interval

polls the block with 6 pulses, arriving at input 49. These sy systas set the trigger 14

the state in which the potential is opened by an electron 21. The pulse from the output of 59 races of the pulses enters the AND 21 at the beginning of the cycle the interrogation of the pulse passes through the input element of the group of elements And 30,

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Item #:

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VC

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20, as well as being skipped through the OR element 86 and the delay element 88 to the output 69 of the distributor 12 (on the element 88, the pulse is delayed by the sampling time of block 8). Impulse with resetting the address of the readout message of the 35th move of the element .OR 86 falls on VKO40

and through the delay element 37, which delays the pulse by the time of setting the address, to the readout control input of unit 6, from the output of which information is fed to the output 52 of the device.

In the PC, these data are used as input parameters of the functional tasks of the control system, according to which solution the obtained results are given out at the input 42 and further to the information input of the block 9, In addition, the input 46 is fed the address of the record received by the help, and to the input 50 - 5 (the write control pulse, which; post: to one of the inputs of the AND element 22, which is controlled by a trigger 15 on the other input) tea, then the trigger 15 is reset to zero t absence of direct ob--, increments of users to 9. The latter "e leads to passage through

You set them to O of all the flip-flops 81 and 82, and threw them, and the pulse from the output of element 88, delayed by element 87 by the delay time of register 3, goes to output 67 of the distributor 12.

Pass through the element OR 20, the pulse arrives at the input of the installation in 1 of the trigger 15, sets it to 1, and thereby removes the high potential from the input of the element And 22.

In parallel, the pulse from the first of the outputs 68 of the distributor 12 is fed to the read input of the corresponding cell of the fixed memory block B, made in the form of a ROM, where the address of the subscriber who requested the certificate is stored, and the address of the memory zone where the requested information is stored. The read code from the output of block 8 is written to register 3 with the help of a pulse received from the output 69 of the distributor 12, after which the address code of the subscriber is fed to the input of the decoded 55

0

pulse element AND 22, which sets the write address from input 46, and, delaying on delay element 38 at the time of setting the address, enters the record control input of block 9, recording the result obtained from VK:

In addition, a pulse from output 55, arriving at the input of the VC interrupt, signals the recording of the result in block 9.

The search for references stored in block 9 is obtained from the workplaces of various control objects through the inputs 47 of the device and then through the inputs 66 of the distributor 12 pulses.

Let us assume that the request arrived at the first of the inputs 66 of the distributor 12. Then the request pulse sets the trigger 81 to a single state, in which it opens the high-potential element AND 83, to the second 5 input of which, from input 65, a generator pulse 71 the output 69 of the distributor 11. This pulse passes through the element AND 83 and further through the output 68 of the distributor 12 to the inputs of the block 8 of memory and the element OR

five

0

0

20, as well as being skipped through the OR element 86 and the delay element 88 to the output 69 of the distributor 12 (on the element 88, the pulse is delayed by the sampling time of block 8). Impulse from the stroke of the element .IL 86 falls on WKO

You set them to O of all the flip-flops 81 and 82, and threw them, and the pulse from the output of element 88, delayed by element 87 by the delay time of register 3, goes to output 67 of the distributor 12.

Pass through the element OR 20, the pulse is fed to the input of the installation in 1 trigger 15, set it to 1, and thus removes the high potential from the input element And 22.

In parallel, the pulse from the first of the outputs 68 of the distributor 12 is fed to the read input of the corresponding cell of the fixed memory block B, made in the form of a ROM, where the address of the subscriber who requested the certificate is stored, and the address of the memory zone where the requested information is stored. The read code from the output of block 8 is written into register 3 with the help of a pulse received from the output 69 of the distributor 12, after which the address code of the subscriber is fed to the decrypted input

thirty

pa 5, which, in accordance with the input code, transmits a high potential to the outputs of the respective groups of elements 32 and 33, and the code of the address of the memory zone is fed through the elements 28 to the address input of the memory block 9. At the same time, a clock pulse from output 67 is fed to the read input of block 9, thereby submitting the code of the read help through the corresponding groups of elements 32 and 33 to that of outputs 53 or 54, which corresponds to the subscriber who requested the certificate.

The same pulse from output 67, kept on element 36 for the duration of reading data from block 9, is fed to the input of register 3 and sets it to its original state, preparing it for a new cycle of operation. , „

A message recording pulse arriving at input 44 passes to the first input of an AND 23 element, the second input of which is connected to the inverse output of an AND 26 element. 25

A reversible counter 18 is designed to store the number of M messages waiting to be processed. Since before starting operation, the contents of counter 18 are zero, then all its direct outputs have a low potential value that falls on all inputs of the AND 25 element, which results in a high potential value at its inverse output. At the inverse output of the AND 25 element there is i 35 a high value is amusing in all cases when at least one bit of the counter 18 is zero, which corresponds to the ratio .40

M 2%

where m is the number of bits. counter 18, equal to the number of bits of each of the counters 16 and 17, and equal to 45 bits of the word of block 10. In all these cases, a high value of the potential from the inverse output of the element And 25 opens the element And 23 for the passage of message recording pulses 50.

i Thus, the first of the message recording pulses passes through the element 23 to the summing input of counter 16, thereby increasing its contents by one, which is the address of the first zone free for recording in block 10. This address is passed through the pulse va0

with "

five

50

five

writing a message delayed on element 39 for the duration of the counter 16, through groups of elements 34 and 34 and 29 on the address, input of block 10. An impulse from the output of element 39, going to the recording permission input of block 10, provides an entry to this block specified on the information input 43 of the device. In addition, the pulse from the output of the element 39, entering the summing input of the counter 18, increases by one its content M.

In the case when in block 10 there are free zones for recording messages waiting to be processed, the pulse of recording messages ensures the memorization of the message that came with it. In case the block 10 is filled with messages, as evidenced by the single state of all bits of the counter 18, the low potential value from the inverse output of the AND 23 element prevents the message recording pulses from passing through the AND 23 element, which makes it impossible to record the message in the filled block 10 memories.

Similarly to the described above (for element And 25), the inverse output of element And 26 contains a low potential value in the case when 1 number M of waiting messages is zero, and a high potential value for any other values of M.

The impulse from the output of the element 37, which provides reading from block 6 of the information to be transmitted to the VC, goes to the first input of the element 24, the second input of which is connected to the inverse output of the element 26. Therefore, the impulse from the output of the element 37 ) passes through .element I 24 if and only if the number M of waiting messages is different from zero. At the same time, the reading pulse of the message increases the content of the counter 17 to one, i.e. the address of the read word of block 10 (the initial value of the contents of the counter 17 is one less than the contents of the counter 16, i.e. the write address). Delaying on the element 40 for the time of modification of the contents of the counter 17, the pulse of reading the message ensures the passage of the contents of the counter 17 to the address input of the block 10 and the formation at the information output of the block 10 of the code of the first of the expected message processing. This code

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i9. 1608694

Claims (1)

from jubilant it gets to the information in the soda of register 1 and is written to this register by means of a pulse from the output of the delay element 40 delayed by element 41 on the sampling time of the block K). In addition, the pulse from the output of the delay element 40, falling on the subtracting input of the reversible counter 18, reduces its content M by one; those. The number of waiting messages. In the case when there are waiting messages in block 10, the read pulse of its conversations is provided by rewriting the first of these messages into register 1. If in block 10 there are no pending messages, the state of register 1 zeroed by the message reading pulse does not change. Invention Formula Device for information pisska auth.St. No. 1399768, characterized in that, in order to increase the reliability of the device by reducing information losses, a third AND element is entered into the device, the first input of which is the synchronization input of the device, the fourth AND element, the first input of which is connected to the output of the second delay element, the fourth the delay element, the input of which is connected to the output of the third element I, the fifth delay element, the input of which is connected and 1en with the output of the fourth element, the first summing counter, the count of which input is connected to the output of the relay element ment And, the second is summed - I11 counter, the counting input of which is connected with the output of the fourth element I, the fourth group of elements AND, the 40 first inputs of which are connected to the outputs of the first summing counter And the second inputs of the fourth group of elements I connected with the output of the fourth iCTO delay element , the first group of elements I, the first inputs of which are connected to the inputs of the second one, which is summed up to the input of the second input of the input of the second input. 20 25 thirty 45 to t5. 08694 40 ten the second inputs of the fifth, a group of elements And are connected to the output of the fifth delay element, a third group of elements OR, the first inputs of which are connected to the outputs of the fourth group of elements AND, and the second inputs of the third group of elements OR are connected to the outputs of the fifth a group of elements And, a reversible counter, the summing input of which is connected to the output of the fourth delay element, and the subtracting input of the reversible counter is connected to the output of the fifth delay element, the fifth element And, whose inputs are connected to the direct output reversible counter, the output of the fifth element And is connected to the second input of the third element And, the sixth element And, the input of which is connected to the inverse output of the reversible counter, the output of the sixth element And is connected to the second input of the fourth element And, the sixth delay element, the input of which is connected to the output the fifth delay element, and the output is connected to the synchronization input of the first register, the fifth memory block whose recording input is connected to the output of the fourth delay element, the read input of the fifth memory block is connected to the output the fifth delay element, the inputs of the address bits of the fifth memory block are connected to the outputs of the third group of OR elements, 5 the information input of the fifth memory block is the second information input of the device, the information output of the fifth memory block is connected to the information input of the first register, the fifth synchronizing output of the first pulse distributor is connected to the second setup input of the second register, the first synchronizing output of the second pulse distributor is connected to the synchronous input of the third register . 20 25 thirty five .one five