SU1603420A1 - Device for exercising memory - Google Patents

Abstract

The invention relates to automation and computing and can be used to train memory and professional selection of control system operators. The purpose of the invention is to expand the didactic capabilities of the device by determining the duration of storage of information in the RAM. The device contains a block of 1 presentation of educational information, a shaper of 2 binary codes, a block 3 for setting standards, a block 4 of control, a block 5 for analyzing responses, an operator panel 6 and a block 7 for registration. The introduction of the shaper 2 binary codes, as well as the execution of the control unit 4 and the response analysis unit 5, determine the duration of storage of the material in the test memory of the subject. 2 hp f-ly, 8 ill.

Description

(Rig.;

The clock pulses from the output of the generator 18 enter the counter 19 and through the element 22 (the delay time of which is equal to the response time of the counter 19) to the information input of the prohibition element 21. Since the control input of the element 21 receives a zero potential from the output of the counter 19, the pulse from the output of the element 21 is fed to the input of the generator 17 and to the inputs of the register 3 and the register 25

The invention relates to automation and computing and can be used to train memory and professional selection of control system operators.

The purpose of the invention is to expand the didactic capabilities of the device.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a functional diagram of the proposed device; in fig. 3 - functional 10 ra 14 block 1. Pulses from the output of the generator of the binary code generator; Naratora 17 served on other inputs refig. 4 - functional scheme of the block master 8 and register 14, ensuring in them

management; in fig. 5 - functional-write binary code combination,

on the analysis block diagram; in fig. 6 - Upon receipt of the ninth clock imfunctional diagram of the operator's console; pulse to the input of the counter 19 at the output in FIG. 7 is a functional block diagram of the last overflow pulse,

which arrives at the input of the delay element 23, the control input of the prohibition element 21, the input of the register 32 of block 5 (by shifting the contents by one bit), numbers), the driver 2 binary codes, 20 to the first input of block 4, to the second input of the block 3 tasks of standards, block 4 of the control element I 30 (but will not pass further,

since at its first input there is zero potential) and at the first (counting) input of counter 25, fixing the record of the first number in register 14 of block 1. At the output of element 21 of driver 2, the ninth clock pulse does not work. The progress of the code sequence in registers 8 and 14 is delayed by one clock cycle. The delayed pulse from the output of element 23 returns 18 clock pulses, the counter 19, 30 pushes the counter 19 to its original position, the element NOT 20, the prohibition element 21, the next eight clock pulses continue to write the binary random sequence to registers 8 and 14, and The clocked pulse causes the appearance of an overflow pulse (polling) at the output of counter 19, which will pass to the input of counter 25 of block 4 (fixing the recording of the second two-digit number in register 14 of block 1) and to the second input of AND 30 element. first in ho39 "Answer, trigger 40 button 41" Change 0 de element AND 30 has a single and element OR 42. Potential (due to "code sequence units from the outputs of the fourth register group 8), then the pulse from the output of the AND 30 element will pass to the second inputs g elements And 11 and 12 of block 3, the first inputs of which are connected to the outputs of the Comparators 9 and 10, respectively. Binary code combinations are applied to the inputs of the first groups of comparators 9 and 10 from the outputs of the first and second groups, the registration from its output is fed to all 50 pa 8, and to the inputs of the second groups from the device outputs, including the inputs of the third group. and the fourth group of the registrar one 50. The impulse from the output of one 8, respectively. In comparators 9

the new vibrator 50 sets the triggers 26, and 10 successively crawls 38, 40 and 47, counters 25, 29, 43 and 45 and register binary code combinations from 8 and 14 to the initial state of the corresponding register bits of the register 8,

The zero potential from the trigger output 26 55 ensures the occurrence of a single flow-block 4 is fed to the input element NOT 20cial at the output of the comparator 9 (if the former 2, the single potential first digit of the first number is less than the output of which starts the 18. digit of the second number) or comparative registrations: in FIG. 8 is a functional diagram of the power on node.

The device contains a block 1 of presentation of educational information (two-digit

laziness, block 5 of the analysis of answers, the console 6 learner and block 7 of the registration.

Block 3 contains a register 8, comparators 9 and 10, the elements And 11 and 12 and the element OR 13.

Block 1 contains a shift register 14, decoders 15 and an indicator 16.

Shaper 2 contains a pseudo-random sequence generator 17, gene 22 and second 23 delay elements and the element OR 24.

Block 5 contains the counter 25, the trigger 26, the first - the third element OR 27-29, the element And 30 and the element 31 of the delay.

Block 6 includes a memory register 32, an EXCLUSIVE OR element 33-33, an OR element 34, an AND element 35, a prohibition element 36 and a delay element 37.

Remote 7 contains the triggers 38, buttons

Block 8 includes a counter 43 (cycles) and a timer 44 consisting of a counter 45, a time stamp generator 46, a trigger 47, and an OR 48 element.

The memory switch assembly contains a toggle switch 49 and a potential one-shot 50.

The device works as follows.

Turn on the power switch 49. For example, the clock pulses from the generator 18 output go to counter 19 and through element 22 (the delay time of which is equal to the response time of counter 19) to the information input of the prohibition element 21. Since the control input of the element 21 receives a zero potential from the output of the counter 19, the pulse from the output of the element 21 is fed to the input of the generator 17 and to the inputs of the register 3 and the register 14 of unit 1. The pulses from the output of the generator 17 are fed to the other inputs of the retor 10 (if the first digits of both numbers are equal and if the second digit of the first number is less than the second digit of the second number). If the second number is less than or equal to the first, then the unit potential at the outputs of the comparators 9 and 10 is absent. Pulse “polling from the output of the counter, 19 will move the contents in register 32 of block 5 by one bit.

If the second number is greater than the first, then from the outputs of one of the comparators (9 or 10) a unit potential will be applied to the corresponding first input of the element 11 11 or 12. The impulse of the poll, received from the output of the counter 19 of the driver 2 at the second inputs of the elements 11 and 12, will pass through the element OR 13 at the input of the register 32 of the block 5. The impulse of the interrogation received a little earlier at the input of the GI register 32, on the falling edge of the clock pulse will write “1 to register 32.

The arrival of the next polling pulse (in the absence of a signal at the outputs of comparators 9 and 10) will shift “b in register 32 by one bit.

After writing to the register 14 of the block 1 on the tenth of the output of the counter 25 of the block 4, the overflow pulse arrives at the input of the delay element 31 and at the input of the trigger 26, transferring the latter to the unit state. A single potential from the output of the trigger 26 goes to the input of the element NOT 20 driver 2, turning on the generator 18, to the control input of the unit 1, highlighting 16 lines of ten numbers, and to the input of the timer 44 of the block 7, throwing the trigger 47 into one state and will start a 46 timestamp generator. The counter 45 starts counting time. The delayed impulse from the output of the element 31 will return the counter 25 to the initial state, and the impulse applied to the third input of block 7 will register the first cycle in the counter 43.

The test subject (operator) in the presented string of two-digit numbers sequentially (from left to right) compares the arranged numbers to each other and, when finding a number greater than the previous one, presses the button 39 of the console 6 located below this number.

When a certain button 39 is pressed, the corresponding trigger 38 is transferred and a single potential from its output is applied to the second input of the corresponding element EXCLUSIVE OR 33 of block 5.

Having determined in the row of indicators 16 of block 1 all numbers greater than the previous one and “having deleted them by pressing buttons 39, the subject memorizes the last in the row in order to compare it with the first number

next line, and then presses the button 41 "Change.

If the subject has determined all numbers in the row (“crossed out”) correctly, then

the outputs of the elements EXCLUSIVE OR 33 and the output of the element OR 34 there will be a zero potential. The impulse from the trigger output 40 after pressing 41 through the first output of the delay element 37 of block 6 (the delay is equal to the response time of the element 35) goes to the information input of the prohibition element 36, the control input of which is supplied with zero potential from the output of the element 35. Impulse c the output of the prohibition element 36 will go through the element OR 29 of the block 4 to the input of the trigger 26, ensuring the appearance of a zero potential at its output.

Flashing numbers on indicators

0 16 of block 1 is terminated, and at the output of the element HE 20 of the former 2, a unit potential appears, which starts the generator 18, as a result of which the second line is formed for

5 shows to the subject and determining in it numbers greater than the previous one, with entry in register 32 of memory 4 of block 4, flashing the second row, etc., i.e., the process is repeated as described above. Delayed pulse from the second

The 0 output of the element 37 will go to the input of the element OR 42 of the console 6 and will return the triggers 38 and 40 to the initial state.

If the subject at least one number in the line identified the wrong (clicked

5, the wrong button 39), then at the output of the element OR 34, a potential is applied that is applied to the first input of the element 35. When the button 41 is pressed, the flip-flop 40 changes to a single state. A single impulse from the output of the trigger 40 is fed to the second input of the element I 35 and to the input of the element 37 of block 5, the pulse from the first output of which is fed to the information input of the prohibition element 36 simultaneously with the pulse from the output of the element 35 that arrives at the control input of the element 36 . At the output of element 36, there is no signal, thereby preventing (and forming) the next line of numerical information. Impulse output

0 of the element 35 and will go to the input of the trigger 47 of block 7, transferring it to the zero state. The zero potential will turn off the generator 46, stopping the flow of time marks to the counter 45. Timer 44 fixes the time from the moment of starting work

5 (presenting a numeric string) before finding the error, and counter 43 - the number of the cycle. (NUMERIC numbers given during this time).

0

The initial settings of which are the inputs of the second OR element, the output of which is connected to the R input of the trigger, the S input of which is connected to the output of the counter.

Claims (1)

The invention is an OR element whose inputs are 1. A memory training device with information inputs of a block, and a learning approach that contains a presentation unit, is connected to the first input of the I element, the information, the student console, the task-second input block is connected to the counting of standards, the control unit, the unit is a real input of the counter, and is the synchronization and response analysis unit, the main input of the unit, the inputs of which information input is connected to the output of the standard setting unit, and the first output connected to the first information input of the registration block,,,, the second and third information inputs connected through the delay element with the input connected to the first and second of the third element OR, the output of which is the output of the control unit, the first output connected to the input of the initial set which is connected to the control input of the counter - a block of presentation of educational information, that delays and a trigger are output, characterized in that, in order to increase the number of units, to increase the didactic capabilities of the device, the binary-3 generator is entered into it. A device according to claim 1, characterized by codes, the first and second outputs, which are connected to the information input-contains a register, the information input from the dam of the presentation information module, and the recording inputs of which are corresponding and a unit for setting standards, and, for information and synchronization, the output is connected to the synchronizing inputs of the block, and the outputs are connected to the inputs of the control unit and the educational information analysis unit, the information inputs of the group and the read input are connected to sponds outputs console "with the learner, and the second and third outputs respectively connected to data input keypad and an input of the initial setting of the control unit, data inputs of which are connected to the group They are not connected to the first inputs of the EXCLUSIVE OR elements, the second inputs of which are the information inputs of the block group, and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of which is the read input of the block and through the delay element is connected to the information input the input by the alev-outputs of the group of the unit for setting standards, the zoment of the BAN, the control input of which the input of which is connected to the third is connected to the output of the element AND, the output of the control unit. delay and ele2 coagulant. The device according to claim 1, characterized by a ban, are the outputs of the block, in that the control unit contains the initial settings of which are the inputs of the second OR element, the output of which is connected to the R-input of the trigger, the S-input of which is connected to the output of the counter. the OR element, whose inputs are the information inputs of the block, and the output is connected to the first input of the AND element, the second input of which is connected to the counting input of the counter and is the synchronizing input of the block, the inputs are connected through the delay element with the input of the third OR element, the output of which is connected to the initial installation input of the counter, the outputs of the AND element, the delay element and the trigger are the outputs of the block, 3. The device according to claim 1, wherein the educational information analysis block contains a register, the information input and recording inputs of which are respectively the information and synchronization inputs of the block, and the outputs are connected to the first inputs of the EXCLUSIVE OR elements, the second inputs of which are information inputs The block group and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of which is the read input of the block and through the delay element is connected to the information input of the BAN element whose control input fPiie 2 ig. 3 29 H I Vuz 4 FIG. five azig.6 Fie.7