SU1690205A1 - Fiber optical data transmission system - Google Patents

Abstract

The invention relates to information transmission techniques. The purpose of the invention is to provide the interfacing of a fiber optic line with a computer network. The fiber-optic information transmission system contains on the transmitting side a master oscillator 14, a shift register 12, a shaper 13 of a code and an electro-optical converter 15, and on the receiving side an optoelectronic converter 17 and a selector 18 of a clock frequency and code. The goal is achieved by the introduction of the pulse polarity selector 1, the elements OR 2-5, the address informant 6, the information encoder 7, the address register 8, the information register 9, the counter 10, the drivers of the write pulses 11, the shift register 19, the decoder 20, the decoder 21 sync signals, information decoder 22, address memory block 23, element OR 24, shapers 25 of a bipolar code, counter 26, RS flip-flop 27, demultiplexer 28, terminal block 29, Information input-output in the system is performed with a bipolar code. Information is transmitted through only one of the channels word for word, each word consists of 14 bits. Instead of the first bit, which is always G in each word, the channel address is transmitted, so the recovery of the first bit to the shaper 11 occurs with the arrival of the clock, 1 slug. (Ls

Description

The invention relates to techniques for the transmission of information, can be used for fasting? os n vi V. local information and computing networks v. it is intended, in particular, to provide information exchange between control devices / several peripheral devices in complexes of display devices of the EC 7920 type.

. The purpose of the invention is the provision of interfacing a fiber optic line with a computer network.

The drawing shows a block diagram of the proposed transmission system.

The transmission system contains a pulse polarity selector, OR elements 2-5, address encoder 6, information encoder 7, address register 8, information register 9, counter · 10, write pulse generator 11, shift register 12, code generator 13, oscillator 14, electro-optical converter 15, communication lines 16, optoelectronic converter 17, clock and code separator 18, shift register 19, decoder 20, clock decoder 21, information decoder 22, address memory fleas 23, OR element 24, bipolar code generator 25, s etchik 26, RS-trigger 27, demultipleksor28, terminating unit 29.

The transmission system operates as follows.

The transmission system is designed for bi-directional transmission of signals in a complex of type EC 7923.

Up to 8 displays, previously connected to the rack via a copper cable, are connected to the control rack through the proposed fiber optic system. Information is transmitted in a bipolar code, input and output of information is carried out at one point, the possibility of implementing a higher speed of 360 versus 150 kbit / channel.

Each unidirectional transmission channel in the system operates as follows.

At any time, information can be transmitted t-zlto through one of the · cialosis, input-output of information in the system is carried out by a big-code. Information is transmitted word by word, each word consists of 14 bits, the first bit of a word is always 1. A bit of information is transmitted by two unipolar pulses. The pulse duration is Ti = T / 4, where T is the period of the signal, the duration of the pause: between words T _o = ¹ T.

The sync signal is passed before each word k5 - '. The UN nation ή! _0._

The first bit of the signal in each word is always 1. Instead, a 4-bit channel address is transmitted. The information bits of the signal are encoded with 4-bit packets 1011 for ”0 and 1101 for * Ί. Information-free measures are filled with zeros. To avoid possible failures when accepting a long combination of zeros, the pause is filled with the combination 0 ... (15 zeros) ... 01. The choice of a 4-bit address for 8-channel information exchange improves transmission reliability. The address is chosen so that for any two channels they differ from each other no less than in dzushbits.

The input information of each channel of the selector 1 is converted and two sequences of the TTL level corresponding to the positive and negative pulses of the input bipolar signal. Only one channel can work at a time, no information is available on all the others at this time. On the element OR 2 and the encoder circuit 6 address? signals are received, according to the positive state of the bipolar signal, to the element OR 3 - corresponding to negative.

The outputs of elements OR 2 and 3 are fed to two inputs of the information encoder 9, which also performs the functions of a phase analyzer, determining which of the two pulses passed first. The encrypted information goes to the information register 9 and to the OR 4. element that combines both outputs ”for the subsequent operation of the counter. 10 and the shaper 11 of the write pulses.

The 4-bit address goes to register 8 of the address. The registers work in parallel and are combined on the OR element 5, the output of which is supplied to the register 12. The shaper 11 generates a write pulse ps for each input information big. Thus, before the first bit ’, which takes part of the pause before the word, the clock signal is written in the word, and instead of the first bit, which is always · 1, the channel address is recorded. Pauses between code combinations that occupy only an hour of the clock interval are filled with zeros.

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The counter 10 is installed at the input of the installation with input information coming from the output of the OR element 4, in the absence of input information (pause between words) sets the shaper 11 to its initial position for recording the first bit in the next word.

Shaper 13 moves converts the output information in the NRZ code to the code ’’ Manchester.

1690'205

The master oscillator 14 generates a fundamental frequency.

The input information from the output of the Converter 17 is fed to the input of the clock isolator 18 and the code, the outputs of which are connected to the inputs of the shift register 19, From the parallel outputs of the register, the information goes to an address decoder, information decoder 22 and a clock decoder 21,

With the arrival of the clock signal information is stored by the memory unit 23, the RS trigger is transferred and allows the passage of information to the demultiplexer 28.

The outputs of the decoder 22 are connected to the inputs of the shaper 25 of the components of the bipolar code, the outputs of which are connected to the inputs of the demultiplexer 28. The outputs of block 23 determine the passage of information to the corresponding channel.

The outputs of the decoder 22, together with the output of the decoder 21, are input to the installation of the counter 26. In the absence of information (pause between words), a signal appears at the output of the counter 26, which sets the RS-trigger to its initial state, which prohibits the passage of information to the demultiplexer 28.

The generated constituent signals of the bipolar code from the outputs of the corresponding channels of the demultiplexer 28 are sent to the terminal block 29. At the output of the corresponding channel, the information in the bipolar code enters the external communication line.

As mentioned above, instead of the first bit, which is always 1 in each word, the channel address is transmitted, so the restoration of the first bit on the former 25 occurs with the arrival of the clock pulse.

Claims (1)

Claim An optical fiber information transmission system containing on the transmitting side a master oscillator, a shift register, and a series-connected code generator and an electro-optical converter, and on the receiving side, a series-connected optoelectronic converter and a clock and code isolator, which is different . that, in order to ensure the coupling of the fiber optic line with the calculated. 5 connected in series with a pulse polarity selector, an address encoder, an address register and a first OR element, the output of which is connected to a shift register input, a second 10 OR element, an information encoder, a third OR element, a counter, a recording pulse generator, and encoder, as well as the fourth OR element, the input of which is connected to the outputs Negative pulses of the polarity selector, and the output of the fourth OR element - with another input of the information encoder, the inputs of the third ele The OR gate is connected to the information inputs of the encoder, and the output of the third OR gate is connected to the start input of the write pulse shaper, the write output of which is connected to the inputs of the shift register and address register, the output of the master oscillator is connected to the clock inputs of the shift register code shaper, address register, a counter and an encoder, the output of which is connected to the second input of the first OR element, and on the receiving side, serially connected shift registers, an address decoder, an address memory block, and a demul typlexer, sequentially connected clock decoder and RS-trigger, serial information encoder, OR element and counter, as well as a bipolar code generator, the outputs of which are connected to the inputs of the demultiplexer, the output of the clock isolator and code are connected to the inputs of the shift register 40 and the Reset inputs of the counter, shaper of the bipolar code, address memory block, the outputs of the information encoder are connected to the inputs of the shaper of bipolar code, the outputs of shift register 45 are connected to moves encoder and decoder timing information, output RS-flip-flop is connected to the control input of the demultiplexer, the decoder input clock signal is coupled to inputs of the recording unit 50 or the memory element address, and a code generator biimpulsnogo.