SU1677842A1 - Reversible pulse distributor for controlling step motor - Google Patents

Abstract

The invention relates to electrical engineering and can be used to create a highly adaptive discrete electric drive based on three-, four-, five-, and six-phase stepper motors. The purpose of the invention is to expand the operational capabilities by increasing the number of switching modes. The distributor contains a clock bus 2, control buses 3, reverse 4, turning on 21 stepper motors, four buses 7-10 for selecting the tact of switching, two buses 5, 6 for selecting the stepping motor (SM), binary counter 1, four AND-11 elements 11 14, a permanent storage device (ROM) 20, two elements IL & 15, 16. two multiplexers 18, 19 and an inverter 17. In accordance with the information on the input buses from the ROM 20, the code combinations are selected according to the specified switching mode of the windings of the selected SD. opportunity is reached bla Odar provide additional six SM switching modes when the total number of modes equal to 20. 1-yl. g

Description

The invention relates to the control of electric machines and can be used to create a highly adaptive discrete electric drive based on three, four, five and six-phase stepper motors.

The purpose of the invention is to expand the operational capabilities by increasing the number of switching modes.

The drawing shows a functional diagram of a reversible pulse distributor for controlling a stepper motor.

A reversing pulse distributor for controlling a stepper motor contains a binary counter 1 associated

clock input (C), counting input inputs (V) and counting direction settings (± 1) with clock bus 2, control buses 3 and reverse 4, first 5 and second 6 buses of stepper motor selection (SD), first 7, second 8, the third 9 and the fourth 10 buses of the selection of the tact of switching, connected to the first inputs of the first 11, second 12, third 13 and fourth 14 AND-NOT elements, first 15 and second 16 OR elements, inverter 17, first 18 and second 19 multiplexers, respectively and a permanent storage device (ROM) 20, the first and second outputs of which are connected The first inputs to the first 15 and second 16 elements, respectively, OR, the second

ABOUT

VI VI

00

Ј

ho

the inputs of which are connected to the outputs of the first 18 and second 19 multiplexers, and the outputs are used respectively as the first and second outputs of the distributor, the third, fourth, fifth and sixth outputs of which are the corresponding outputs of the ROM 20, the enabling input (/ J connected to the bus) 21 switching on the stepper motor, the first address input is connected to the output of the first element AND-NOT 11, the second input of which is connected to the output of the second element AND-NO 12, the second input of which is connected to the output of the first digit of the binary counter 1, the turns of the second, third and fourth bits of which are connected respectively with the second, third and fourth address inputs of ROM 20, the fifth address input of which is connected to the output of the third AND-NOT element 13, the second input of which is connected to the output of the fourth AND-NOT element 14, connected to its second input with the output of the first bit of binary counter 1, the first information input of which is connected to the high potential bus, the second information input is combined with the first (minor) address inputs of the first 18, second 19 multiplexer c and connected to the first bus 5 of the SM selection, the third information input is connected to the output of the inverter 17, the input of which is connected to the second bus 6 of the selection of the SD and is connected to the fourth information input of the binary counter 1 and the second (senior) address inputs of the first 18 and second 19 multiplexers, the first, second, third and fourth information inputs of the first multiplexer 18 are connected respectively to the fourth, fifth, sixth and seventh outputs of ROM 20, the first and fourth information inputs of the second multiplexer 19 in the case of As a ROM 20, chips with a low active output level are connected to a high potential bus, i.e. these inputs are applied to the level of logical units, the second and third information inputs of the second multiplexer 19 are connected respectively to the sixth and seventh outputs of the ROM 20.

A reverse pulse dispenser for controlling a stepper motor operates as follows.

The type of motor used in the stepper motor drive and the corresponding counter module of the binary counter 1 is determined by a combination of two potential signals supplied to the first 5 and second b bus of the SD selection. Taking into account the logical unit on the first information input of the binary counter 1 and the inversion of the signal arriving at the third information input of the counter 1 from the second bus 6 of the SM selection via the inverter 17, the binary inputs corresponding to the specified counting module are generated on the data inputs Di, D2, DA, Ds of the counter .

When a potential resolution enable signal is applied to bus 3

0 binary counter 1 starts counting the clock pulses arriving at its counting input, operation depending on the level of the potential signal on bus 4 of the reverse in the addition or subtraction mode. At the individual outputs of binary counter 1, a binary address code is generated that is fed to the address inputs of ROM 20, and the signal from the output of the first bit of counter 1 can pass to the first or

0 fifth address inputs of ROM 20 only in the case when the first inputs of the first 11 and second 12 elements are NOT (i.e., the first and second 8 buses of the selection of switching tact) or the first inputs of the third 13 and

5 of the fourth 14 I-NOT elements (i.e., the third 9 and fourth 10 buses of the tact selection of commutation) will be supplied with high-level enabling signals (logical units). In each of these cases, when

0 applying a low level enable signal to the bus for switching on the SM, i.e. on the enable input of the ROM 20, the readout of the information recorded in the ROM occurs for each clock pulse and thereby

5, asymmetrical switching modes are implemented. In the remaining cases, both on the first and on the fifth address inputs of the ROM 20, a high or low level signal is constantly maintained, i.e. logical unit or logical zero, as a result of which the information recorded in ROM 20 is read for each odd or even even clock pulse, which ensures the implementation of symmetric modes

5 switching. A variant of the corresponding firmware of the ROM 20. For which one K 155 REZ chip is used (a ROM with 32x8 bits organization and one-time electrical programming) is given in

0 tab. one.

The signals on the first and second outputs of the distributor, i.e. at the outputs of the first 15 and second 16 elements OR, providing the addition of low OR signals

5 levels are formed when the distributor operates from the signals at the first and second outputs of the ROM 20 and the output signals of the first 18 and second 19 multiplexers. Accordingly, the combination of potential signals at the address inputs of the multiplexers 18

and 19, i.e. signals on the first 5 and second 6 buses of the selection of the SM, through which the counting module of binary counter 1 is simultaneously set, the outputs of the first 18 and second 19 multiplexers pass one of the output signals of the ROM 20 and the signal of the logical unit or the signals of the outputs of the ROM 20. Dependence of the counting module of the binary counter 1 on the potential signals on buses 5 and 6 of the SM selection, the type of SM and switching modes implemented for the selected SM depending on the potential signals on the tires 7-10 of choice aktnosti commutation instances for direct counting are presented in Table. 2

When the potential signal level on the reverse bus 4 changes, the address code generated by the binary counter f changes in the reverse order, ensuring that the information recorded in ROM 20 is read in reverse order, which leads to the reverse of the stepper motor and its rotation in the opposite direction. The fixed station of the step motor, if necessary, is provided by applying a potential signal to prohibit counting on the distributor control bus 3. If in this mode a high level inhibit signal is applied to the bus 21 for switching on the SM, then on all outputs of ROM 20, regardless of the state of the address inputs, signals of the same (high) level appear, which causes the appearance of the same signals on all outputs dah of the distributor, ensuring the delimitation of the windings of the stepper motor with preservation of the information on the status of the distributor in the counter.

Thus, this pulse distributor for controlling a stepper motor has a broader operational capability than the known technical solutions. The total number of switching modes of stepper motors realized by the proposed distributor is 20, which is more than 40% greater than the number of modes provided by the prototype. For the most common four-phase stepper motor, the proposed distributor provides all possible modes of four- and eight-stroke windings,

Claims (2)

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