SU1675943A1 - Device to synchronize and separate the data - Google Patents

Abstract

The device relates to the field of digital magnetic recording, in particular to a device for synchronization and selection of data reproduced from a magnetic recording medium. Reproducible from a magnetic disk information is fed to the input 7 of the data. To perform the initial capture of the frequency and phase of the reproduced data, control signal 8 is supplied with the signal necessary for capturing the duration with a unit operating level. The device’s phase-frequency comparator 1 compares frequencies and phases at the data input .7 with pulses at the output of the controlled oscillator 3 or only phases. Due to this, the structure of the device is simplified. 2 h. n. f-ly, 3 ill. L ETS75 &t; J

Description

This invention relates to the field of digital magnetic recording.

The purpose of the invention is to simplify the device and expand its functionality by introducing a data extraction function.

FIG. 1 is a diagram of a device for synchronizing and extracting data; in fig. 2 - time diagrams of his work; in fig. 3 - timing diagram of the logical unit.

For convenience of description, the links in FIG. 1 and their corresponding timing diagrams in FIG. 2 and 3 are designated by the letters of the same name A ... T.

The device contains a phase-frequency comparator 1, an integration block 2, a controlled oscillator 3, a divider 4 frequencies, a trigger 5, a logical block 6. There are data input 7, control input 8 and data output 9,

Phase comparator 1 contains triggers 10 and 11 with a common reset through the element AND NOT 12 and the element And 13, the trigger 14, the element OR 15, and the one-shot 16, forming a pulse with a high operating level. The pulse duration of a single-vibrator is chosen equal to half the period of the signals of the controlled oscillator.

The logic block consists of a trigger 17, the D and C inputs of which are respectively the first and second reference inputs of the logic block, the inverter 18, the input of which, together with the first input of the AND-19 element, is connected to the signal input of the logical block, AND-NOT elements 20 and 21 are the triggers 22-24, with the inertial output of the trigger 24 being the output of the logic block.

Initial synchronization in the device is carried out in the synchronization field of the reproduced data array, which is a sequence of zeros, i.e., regular pulses with a period twice as long as the sync signals from the output of the controlled oscillator 3. To capture the input 8 control signal is given the required duration with a single operating level (Fig. 2, a).

When the front of the next pulse arrives from the inverse output of the divider 4 frequency, trigger 5 is activated and disables the one-shot 16, keeps trigger 14 in reset state. Trigger 10 is activated by each pulse of the data signal (B), and trigger 11 by each pulse of the signal (D) output divider 4 frequencies. The reset of both triggers occurs through the elements AND-NOT 12 and AND 13 after both of them are cocked.

In this mode, the phase frequency comparator performs frequency and phase

a comparison. Depending on the phase difference of the compared signals (B and D in Fig. 2), it forms either the output of the trigger 10 or the output of the trigger 11 pulses of a duration equal to the delay between the compared signals. The impulses from the output of the trigger 11 pass through the element OR 15 to the output of the phase-frequency comparator. The pulses (E and G in Fig. 2) from the output of the phase-frequency comparator are conducted to the corresponding increment of the output voltage (I) of the integrator 2 and correct the frequency of the controlled generator 3 in the direction of the phase difference compensation, To the end of the signal A at

0, control input 8, the device is in phase mode, in which the edges of the feedback signals (D) from the output of the frequency divider and the input signal (B) coincide in time.

5B the tracking mode, the device switches on after the termination of the control signal (A) and the switching of the trigger 5 into the unit state (Fig. 2.6), enabling the operation of the trigger 14, the radar 16 and holds it

0 cocked condition trigger 11. In this mode, phase error signals appear at the output of the phase comparator only after the arrival of each input pulse, due to which it does not respond

5 at the frequency of the input signals and is able to work with the coded data signal. The phase adjustment of the signals of generator 3 is carried out on the basis of a comparison of the durations of the charge and discharge pulses

0 from the output of the phase-frequency comparator 1. The duration of the charge pulse is equal to the delay between the front of the input signal and the front of the sync signal from the inverted output of the controlled oscillator 3, and the duration of the discharge pulse is fixed by a single vibrator and is equal to half the period of the signals of the controlled oscillator 3. If, for example, Since the next data input signal / signal is late for the time At relative relative to its nominal position (indicated by the dotted line) position (Fig. 2, c), then the output of the one-vibrator 16 causes a pulse of a fixed duration And the output flip-flop 10 - pulse at

5 duration (Fig. 2, e, g). This pair of pulses, acting on the inputs of the integration unit 2, leads to a decrease in its output voltage (Fig. 2i) and, consequently, to a decrease in the frequency of the output clock signals.

On fig.Z shows the timing diagram of the logical unit. Its signal input receives pulses (G) from the second output of the phase-frequency comparator, equal in duration to half the period of the signals of the controlled oscillator 3. Pulses (D) are output to the D input of the trigger 17, which is the first reference input of the logic unit . The C input of this trigger, which is the second reference input of the logic block, receives pulses from the inverse output of the controlled generator 3. The trigger 17 shifts the pulses from the 4 frequency divider by 1/4 period, forming the so-called data windows (K), located symmetrically relative to the nominal positions of the data signals (their fronts) (G). In the absence of data signals, both the AND-NE 20 and 21 valves are open, so the output signal (P) of the trigger 22 repeats the signal (K) from the output of the trigger 17.

The value of the digital data symbol carried by the signal input of the logical block of pulses of the MPM code depends on which shelf: low or high voltage of the signal. the data window is the front of this pulse. The gates AND-NOT 20 and 21 and the inverter 18 serve to ensure that only the signal front is taken into account when selecting a symbol, and its duration does not play a role. This is due to the fact that during the operation of the data pulse, the state of the trigger 22 (P) cannot change. Thus, if the front of the data pulse falls on the low zero shelf of the window signal (R), then the output of the INE element 19 does not produce a pulse, i.e. a zero symbol is fixed. If the front of the data pulse (L) falls on a high unit window signal shelf (K and P), then at the output of the NE-NE element 19 a zero pulse (P) is formed with a duration equal to the data pulse duration (L). This pulse resets both triggers 23 and 24, i.e., a pulse with a high unit level begins to form at the data output. The front of the next window signal (K) re-energizes trigger 23, and if the data pulse in the next window does not appear, then after it ends (after the clock signal period G), the trigger 24 returns to its original state.

If two are continuous, as shown in FIG. 3 or more units, then logic level 1 is held at data output 9. Thus, the input MFM data of the logic block is converted into BVN data.

Claims (2)

Invention Formula 1. A device for synchronizing and extracting data, containing serially connected phase-frequency a comparator, an integration unit, a controlled oscillator and a frequency divider, a direct output connected to the first reference input of the phase comparator, and a trigger with a D input connected to the control signal bus, the signal input of the phase comparator connected to the input bus data, characterized in that, in order to simplify the device and expand its functional capabilities by introducing the data extraction function, a logic block is entered into it, the first reference input of which is connected to the output divides L frequency, the second reference input - with opor0 by direct input from the phase frequency comparator and the inverted output of the controlled generator of the torus, a signal input - to the second output of the phase frequency comparator, and an output - to the output data bus isolation when 5 this C-input of the trigger is connected to the inverse output of the frequency divider, and the output to the control input of the phase-frequency comparator. 2. Device pop. 1, distinguishing - 0 with that. that the phase comparator is made in the form of the first and second triggers, the D inputs of which, together with the one-shot reset input, are connected to the control input, and the C-inputs serve respectively 5 second and first reference inputs of the phase-frequency comparator, as well as the third trigger, the C input of which is connected to the one-shot trigger input and the signal input of the phase comparator, AND, AND-NOT, OR, the inverse output of the first trigger through element VI, another input which is connected to the output element AND-NOT, is connected to the S-input of the second trigger R-input of the third trigger, y 5 of which the D-input is connected to the bus of the logical unit, and the output to the first output of the phase-frequency comparator, the R-input of the first trigger and the first input of the NAND element, the first input of the OR element 0 to the output of the one-shot, its second input together with the second input of the element is NOT connected to the inverse output of the second trigger, and the output is connected to the second output of the phase comparator. 53. The device pop. 1, characterized by that the logic block consists of the first trigger, the D input of which is the first reference input of the logic block, the inverse and direct outputs of the first trigger are connected to the second inputs of the first and second AND-N, respectively, the first inputs of which are connected to the output of the inverter, the outputs of the first and the second elements AND-NOT are connected to the S- and R-inputs of the second trigger, respectively, and the inverse output of the second trigger is connected to the second input of the third AND-NOT element, the first input of which, together with the input of the inverter, is connected to the signal at the input of the logic unit, the output of the third element 0 NID is connected to the third and fourth trigger R inputs, the third trigger D input is connected to the logical unit bus, the C input is connected to the forward output of the first trigger, and the output is connected to the fourth trigger D input, the combined C inputs of the first and the fourth flip-flops are connected to the second reference input of the logic unit, the inverse output of the fourth flip-flop is the output of the logic unit. $ ig. 2 about .about Mr. jnjiJiJi-rLrmjiJT to / | and 11G ..о „о Ж J f  JlJ4Jnjnj Lrl n r P P