SU1660187A1 - Radio communication system - Google Patents

Abstract

The invention relates to radio and can be used to communicate central and peripheral stations with time division channel. The aim of the invention is to increase the efficiency of use of a communication channel capacity. The central station contains receivers 1 and 2, block 3 of the station number memory, control block 4, block 5 of information extraction and generation, address code selector 6, clock signal generator 7, address code generator 8, transmitter 9, keys 10 and 11, and OR element 12. The peripheral station contains a receiver, a sync signal decoder, an address code decoder, a timer, a frequency switch, a control unit, an address code generator, an information extraction and generation unit, a transmitter, and keys. The purpose of the invention is achieved by the fact that the central station, receiving requests from peripheral stations on a separate frequency, organizes a queue of service requests in block 3 of the memory of station numbers, which, if there is a time resource, are serviced by control block 4. 2 hp ff, 4 ill.

Description

ON O O

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The invention relates to radio communications and can be used to communicate central and peripheral stations over a time division channel.

The aim of the invention is to increase the efficiency of use of a communication channel capacity,

FIG. 1 shows a structural electrical circuit of a central station; in fig. 2 is a structural electrical circuit of the peripheral station; Fig. 3 is a structural electrical circuit of the central station control unit; Fig. 4 is a structural electrical circuit diagram of the station number memory at the central station.

The central station contains (FIG. 1) first 1 and second 2 receivers, block 3 of station number memory, block 4 of control, block 5 of extracting and generating information, address code selector 6, clock generator 7, address code transmitter 8, the first 10 and second 11 keys, the element OR 12.

The peripheral station contains (Fig. 2) the receiver 13, the sync signal decoder 14, the address code decoder 15, the timer 16, the frequency switch 17, the control unit 18, the address code generator 19, the information extraction and generation unit 20, the transmitter 21, the first 22 and the second 23 keys.

The central station control unit 4 (FIG. 3) comprises a signal converter 24, a timer 25, a switch 26, a write pulse driver 27, a first delay line 28, a read pulse driver 29, a channel occupancy driver 30, a second delay line 31, an OR element 32.

Block 3 of the memory of station numbers contains (FIG. 4) register 33, write cycle shaper 34, delay line 35, fronterer 36, first decoder 37, N flip-flops 38, N elements AND 39, first 40 and second 41 elements OR, shaper 42 write addresses, read address shaper 43, switch 44, memory block 45, buffer block 46, second decoder 47, OR-NOT 48 element.

The radio system operates as follows.

Information is transmitted from a central station (CA) to a peripheral one at frequency fi, reception of a request from a non-central station from a peripheral station (MS) is made at frequency fa, and information is received at a central station at frequency b.

If there is information on the CA to transmit to the MS, the block 5 for extracting and generating information at its second output generates a signal that is fed to the fourth input of the control block 4. Simultaneously, the selection and formation unit

information on its fourth outputs generates the address of the called station, which is fed to the sixth inputs of the control unit 4. The latter translates this address to the address code selector and to the address code generator, where the signal from the seventh output of the control unit 4 controls this address and is transmitted to the communication channel.

In the intervals between the transmission of the address code of the called PS by the signal of block 4

5, the driver of the clock signal 7 generates the clock signals and transmits them "through the element OR 12 to the transmitter.

Thus, all the receivers 13 PS receive the clock signals and the address code of one of the PS. The sync signals are decrypted on the decoder 14 of the sync signal of each PS, which form the signals to adjust the timer 16. The address code is decrypted by the decoder 15 of the address code, the signal

5 from which the control unit 18 arrives, where the control signals are input to the inputs of the address code generator 19, the frequency switch 17, the first 22 and second 23 keys. In this case, the PS transmitter 21 is tuned to the frequency fa, the address code generator 19 begins to generate and transmit to the transmitter 21 the address code of this PS, the first 22 and second 23 keys are opened, allowing

5, a block for allocating and generating information. 20 to receive and transmit information

Receiver 1 of the central station receives the address code of the requested station

0 and sends it to the first input of the first key 10 and the selector 6 of the address code, which compares the received and transmitted addresses and, if they coincide, outputs them to the first input of the control unit 4 signal. On this signal, the control unit opens the second key 11 and the information from the block for extracting and generating information through the shaper 8 of the address code and the OR element 12 is fed to the transmitter 9. At the same time

0, the address code b selector transmits the address code PS to the second input of the first key 10, and the control unit 4 opens it, passing information to the allocation unit 5 and generating the information.

5 On the PS information CA from the receiver 13 through the open first key 22 enters the block 20 for extracting and generating information. If the peripheral station has information for transmission to the CA, its allocation unit 20 and generation of information

sends to the control unit 18 at its first input a signal by which the latter generates control signals at its third and fourth outputs, which arrive at the address code generator 15 and the frequency switch 17, which tunes the transmitter 21 to the frequency f2, and the code generator 15 the address transmits the code of the given MS to the transmitter 21, the Second receiver 2 CA receives the signal, which then goes to the block 3 of the memory of the station numbers, where it is stored, and the signal about the presence of a communication request is transmitted from this block to the block 4 of the control, which At their second, third, and fourth outputs, a free resource generates read control signals from station 3 of the station number memory of the address code, which goes to the address code selector and to the address code generator 8, where it is stored by the command of the control block 4. Then, at the command of the control unit 4, the address code is transmitted from the generator of the address code 8 through the element OR 12 to the transmitter 9.

On the PS, the address code from the receiver 13 enters the decoder 15 of the address code, where it generates a signal arriving at the control unit 18, which generates control signals opening the second key 23 and simultaneously tuning the transmitter 21 through the frequency switch 17 to the frequency fa.

The CA control unit 4 (Fig. 3) operates as follows.

When information is available in block 5, the formation and allocation of CA information to the fourth input of CA control unit 4 receives a signal on the availability of information for transmission. The signal converter 24, having received this signal at its first input, generates a signal at its fifth output, which triggers the write pulse shaper 27. The pulse 26 from the first output of the driver 27 of the write pulse opens switch 26, which passes the address of the called MS to the output of the control unit. The pulse from the second output of the writing pulse driver 27 is fed to the first delay line 28 and then through the OR 32 element to the sixth output of the control unit. Periodically, timer 25 sends time stamps to the eighth input of the signal converter 24, according to which the latter generates at the first output the trigger signals of the clock generator and the address code generator, which are fed to the eighth output of control unit 4.

When there is a signal at the first input, the signal converter 24 generates

control signals at its second output (fifth output of control unit 4), permitting the flow of information to the block for allocating and generating information.

If there is a signal at the fourth input of the signal converter 24 (communication requests from the PS), the signal converter generates signals from its fourth output to the second output of the control unit, allowing you to read the number of the next requested PS. In addition, the signal from the sixth output of the signal converter 24 is fed to the read pulse driver 29, the signal from the output of which goes to the third output of control unit 4, and also starts the channel pickup time generator 30, from which the signal goes to the fourth output of the control unit to the second delay line 31 and then through the OR element 32 to the sixth output of the control unit.

Unit 3 of the memory of station numbers (Fig. 4) operates as follows.

When the address (start) code arrives from the MS to the first input of the block 3, it enters the register 33, which does not remember this information and sends it to the memory block 45 and the first decoder 37, which, when the start is decrypted, generates a pulse at its corresponding output which arrives at the installation input of the corresponding trigger 38 and element 39. Simultaneously with the receipt of the request in the register 33, the write cycle generator 34 generates a pulse that arrives at the first output of the station number memory 3, the delay line 35 and f A 36 front edge, from the output of which the positive front goes to the inverse clock inputs of the flip-flops 38 and elements AND 39. At the inverse output of that trigger, which has a signal from the output of the decoder 37, turns 1, which will open the corresponding element And 39 and with the signal the output of the OR 40 element will be allowed to write the address code of the MS in the memory block 45 to the write address supplied to the memory block 45 from the write address generator 42 via the switch 44, the negative front from the output of the 36 front unit will flip the trigger 38, tvetstvuyuschy of the MS, which sent the request in protivoprlozhnoe state and forward at its output 1. This Vits signal through an OR gate 41 will go to a second output station number memory unit. When a second request is received from the same MS, it will not be recorded in memory block 45.

To read the number of the next MS requesting the channel, the control signals go to the second, third and fourth inputs of the station number memory block. Control signals arriving at the first and second inputs of the memory of station numbers control the read address and driver 44 and the switch 44 and, accordingly, read from the memory 45 to a specific address. The control signal from the second input of the block 3 of the memory of the station numbers is fed to the first input of the buffer block 46, preparing it for transmitting the request from the next MS to the second decoder 47, which is performed on the control signal received via the second input of the buffer block 46, The third input of block 3 is the memory of station numbers.

The MS request from the outputs of the buffer block 46 is fed to the third outputs of the memory block of the station numbers and to the inputs of the second decoder 47, from the corresponding output of which the signal goes to the input. Resetting the corresponding trigger 38, putting it into a state where Oh, thereby allowing the recording of the next request from the served PS.

Claims (3)

Claim 1. A radio communication system comprising central and peripheral stations, wherein the central station comprises a transmitter, a first and a second receivers, a control unit, and an information extraction and generation unit, each peripheral station contains a transmitter, receiver, control unit, and an allocation and formation of information, about tl and h-, and with the fact that, in order to increase the efficiency of using the capacity of the communication channel, a block of memory of numbers of stations is inserted at the central station; the clock signal, the address code generator, the code selector, the first and second keys, the OR element, the output of the first receiver connected to the first inputs of the address code selector and the first key, the first and second outputs of which are connected respectively to the first and second inputs of the allocation and information generation unit, the first output of which is connected to the information input of the second key; the control input of which is connected to the first output of the control unit; the output is connected to the first inputs of the sync signal generator and the sync signal generator the address, to the first second input of the OR element, the output of which is connected to the transmitter input, the first output of the address code selector is connected to the first input of the control unit, the output of the second receiver is connected to the first input of the station number memory, the first and second outputs of which are connected respectively, to the second and third inputs of the control unit, the second, third and fourth outputs of which are connected respectively to the second, third and fourth inputs of the memory block of the station numbers, the third outputs of which are combined with The output of the control unit and connected to the second inputs of the driver code 5, the address and the address code selector, the second output of which is connected to the second input of the first key, the sixth output of the control unit is connected to the control input of the first key, the cutout and the third output of the extraction and information generation unit are connected respectively to the fourth and fifth inputs of the control unit, and the quarter outputs of the allocation and shaping unit are connected to the sixth 5 inputs of the control unit, the seventh output of the control unit is connected to the third inputs of the formation of the address code and the address code selector, the eighth output of the control unit is connected to the second input of the sync signal generator and the fourth input of the address code generator, the sync signal decoder, the decoder of the address code are entered at the peripheral station, the address code decoder, timer, frequency switch, form of the address code, the first and second keys, with this receiver input connected to the clock decoder, address code decoder and address code information nnomu first key entry, the output of which is connected to 0 to the input of the allocation and generation unit, the first output of which is connected to the first input of the control unit, and the second you; One of the information extraction and generation unit is connected to the information input of the second key, the output of which is connected to the first input of the address code generator, the output of which is connected to the first input of the transmitter, the first output of the sync signal decoder 0 is connected to the first timer input, the output of which is connected to the second input of the control unit, and the second inputs are connected to the second outputs of the synchronizing signal decoder, the first and second outputs of the control unit are connected to the control inputs of the first and second keys, respectively, the third output of the control unit is connected to the second input of the address code generator, the fourth output of the control unit is connected to the input of the frequency switch, the output of which is connected to the second input of the transmitter, the output of the output) -; the address address switch is connected to the third to the input of the control unit. 2. System by l, 1, from l at that the control unit of the central station contains a switch, a signal converter, a write pulse shaper, a first and second delay line read shaper, a channel busy time generator, an OR element, a timer the sixth inputs of the control unit are the signal inputs of the switch, the outputs of the switch are the fifth outputs of the control unit, the pins, the second, the third, the fourth and the fifth inputs of the signal converter are the first, second, third The third, fourth, and fifth inputs of the control unit; the first, second, third, and fourth outputs of the signal converter are respectively the worm, second, sixth, and eighth outputs of the control unit; the fifth output of the signal converter is connected to the input of the write pulse driver, the first output of which is connected to the control input of the switch and the sixth input of the signal converter, and the second output of the write pulse shaper is connected to the input of the first delay line, the output of which is connected to the first input of the OR element, output which is the seventh output of the control unit, the sixth output of the signal converter is connected to the input of the read pulse generator, the output of which is connected to the seventh input of the signal converter, to the input of the channel occupancy time generator and the third output of the control unit, the output of the time occupier of the channel is connected to the input of the second delay line and is the fourth output of the control unit; the output of the second delay line is connected to the second input of the OR element, the timer output is connected to the eighth move the transducer signals. 3. Pop system, 1, characterized in that the block of memory of the station numbers at the central station contains a resistor, first and second decoders, a writer, a delay line, a front driver, N flip-flops, N AND elements, first and second OR elements, read address shaper, write address shaper, comm / tator, memory block, buffer block, IL AND NOT element, and the combined inputs of the register and shaper of the write cycle are the first input of the memory block station numbers, the output of the write loop generator is connected to the input of the delay line and is the first output of the memory block of the station numbers, the output of the delay line is connected to the input of the edge generator, the output of which is connected to the inverse clocked trigger inputs and the first inputs elements AND, N outputs of the first decoder are connected respectively to the installation S inputs N of the flip-flops, second inputs N of the AND elements whose outputs are connected respectively to the N inputs of the first OR element whose output is connected to the input of the write address generator and the control input of the memory block, the outputs which are connected to the information inputs of the buffer block, the outputs of which are the third outputs of the memory of station numbers and connected to the inputs of the second decoder, whose N outputs are connected respectively to the Reset inputs of N triggers, the inverse outputs of which are connected to the third inputs of the N elements A and I, and the direct outputs of the trigger 1 respectively to the N inputs of the second OR element, the output of which is the second output of the station number memory block, the register outputs are connected to the inputs of the first decoder and to the information inputs of the memory block whose address inputs are connected to the corresponding switch outputs, the output of the write address generator is connected to the first input of the switch, the second input of which is connected to the output of the address generator readout, the second input of the station number memory block is the first input of the read address generator, the first input of the OR-NOT element and the first input of the buffer block, the third input Lok station memory numbers is the second input of the buffer block, and the fourth input of the memory block of the station numbers is the second input of the OR-NOT element and the second input of the read address generator. / 81099I FIG. four