SU1649547A1 - Signatures analyzer - Google Patents

Description

1

The invention relates to computing and can be used to monitor and diagnose circulating devices containing elements with three states.

The purpose of the invention is to increase the speed and increase the reliability of the control by eliminating the dependence of the conversion of the signal of the third state to zero or one on the significant (zero and single) elements of the sequence under study in previous work cycles preceding the appearance of the analyzed third state.

FIG. 1 shows a signature diagram of the signature analyzer; in fig. 2 - encoder scheme.

The signature analyzer (Fig. 1) contains a clock input 1, information input 2, mode input 3, group 4 set inputs, reset input 5, pseudo-random sequence generator 6, delay element 7, signature generator 8, display unit 9, encoder 10, an ISKPNGOOAUCHE OR 11 element, an OR 12 element and a switch 13.

The encoder (Fig. 2) consists of two signal analyzers 14.1 and 14.2, each of which contains an NOT 15 element, a buffer element 16 with three states, a resistor 17, an EXCLUSIVE OR element 18, a trigger 19 and an input 20o. The input 20 of the analyzer 14.1 is connected to bus zero level, the input 20 of the analyzer 14 "2 - with a bus of a single level,

As a buffer element 16 with three states, an element can be used, the value of the logic level at the output of which is equal to the value of the logic level at its information input, provided that the control input of the device is given a logic zero signal, otherwise the output takes high-impedance state, e.g. buffer amplifier K155 LP8.

Before starting, the device is reset to the initial state: a logical unit is fed to the input 3 of the signature analyzer, then it sends some binary code to the installation inputs 4, which can be anything other than zero, then a positive pulse is sent to the input 5

0 5

five

0

0

parallel entry into the generator 6 of the code from the installation inputs 4 goes, the same pulse arrives at the input of the initial installation of the signature generator 8 and sets the shift register of the signature generator 8 signature to the initial state. Then a logical zero is applied to the input 3 of the signature analyzer. This is where the signature analyzer setup begins.

is running out.

i

The information input of the signature analyzer is connected to the monitored point of the digital device. When a clock pulse signature analyzer arrives at the clock input and clocks the information about the state of the point being monitored at the output 2 of the signature analyzer, logic levels are set at the outputs of the first and second analyzers 14.1 and 14.2 in accordance with the signal at the information input of the signature analyzer. If a logical zero or an active unit is present at the information input of the signature analyzer, then the first and second analyzers 14.1 and 14.2 are set to different logical levels, if the third state is Z, then the levels of the first and second analyzers 14.1 and 14.2 are set to logical unit levels. In case of installation of various logic levels at the outputs of the first and second analyzers 14.1 and 14.2. at the output of element 18 there is a level of logical units. The logic unit from the output of the access element 18 to the control input of the switch 13 allows the passage of a signal from the information input of the signature analyzer to the information input of the signature generator 8 signatures. If the levels at the outputs of the first and second analyzers 14.1 and 14.2 take the values of a logical unit, then the output of element 18 sets the logic zero level, which allows the signal from the generator 6 to pass to the information input of the signature generator 0 signatures through switch 13. Thus, signature analyzer present

If the levels are logical zero or active logical unit, they are fed through the switch 13 to the information input of the signature generator 8 and are written into it by a clock signal delayed by the delay element 7. If the third state Z is present at the information input of the signature analyzer, then the information input of the signature generator 8 receives a signal from the output of the generator 6, which is also recorded with a delayed clock signal. The need to use delay element 7 is determined by the response time of the analyzer 14, element 18 and switch 13,

The inclusion in the signature analyzer of the generator 6 allows one to increase the reliability of the control due to the independence of the method of recoding the third state Z from the value of the element of the studied ternary sequence received at the input to the previous clock cycle, which takes place in a known device. In the case of using a known device, two sequences, such as, for example, 1 OZ 0 and 1 01 0 0, will be non-peerable with a probability equal to one. When applying the proposed signature analyzer to recognize the indicated sequences, the probability of their distinguishing is P 0.5. The proposed signature analyzer allows for increasing the reliability in the case of a priori uncertainty about the type of possible malfunction that occurs in the overwhelming majority of cases in practice.

Claims (1)

Invention Formula A signature analyzer containing an encoder, switch, driver, signatures, display unit, and OR element. the input of the encoder is the information input of the analyzer, the output of the switch is connected to the information input of the signature generator, the output group of which is connected to the input group of the in5 block 0 five 0 five 0 Dictation, characterized in that, in order to increase speed and increase control reliability, it additionally contains an EXCLUSIVE OR element, a pseudo-random sequence generator and a delay element whose input is combined with the first input of the OR element and is an analyzer clock input, and the output connected to the clock input of the signature generator, the initial setup input of which is combined with the second input of the OR element, and is the analyzer reset input, the first and second information inputs of the switch for They are connected respectively to the information input of the analyzer and the pseudo-random sequence generator output, the clock input of which is connected to the output of the OR element, the mode setting input and the group of information inputs of the pseudorandom sequence generator constitute the mode setting input and the group of installation inputs of the analyzer respectively, the control input of the switch is connected to the element output EXCLUSIVE OR, the first and second inputs of which are connected to the outputs of the typhoid generator. ft.2 f /eight 15 W AND nineteen d sixteen FIG. 2