SU1644393A1 - Binary message coder - Google Patents

Description

one

(21) 4648793/24

(22) 2J.12.88

(46) 04/23/91. Vul. P 15

(71) Kiev Polytechnic Institute named after the 50th anniversary of the Great Oct. of the Br socialist revolution.

(72) K.A. Semenov (53) 621.325 (088.8)

(56) USSR Copyright Certificate nd 318939, class „H 03 M 13/22, 1971.

Reset Enter

(54) DEVICE FOR CODING BINARY MESSAGES

(57) The invention relates to the class of binary message coders and can be used in those areas of computer technology and data transmission techniques where increasing the noise immunity of information is performed using cyclic coding, in particular in large cases.

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mation and control systems. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that the device performs the coding of the g-bit word and issuing the control word for tn-1 clock by introducing a bidirectional parallel block for specifying the direction of transmission and the synchronization block. Thus, in this device the work cycle reduces the Inventory to the device class. coders of binary messages 20 and can find application in those areas of computer engineering and technology of data transmission, where increasing the noise immunity of information is produced using a cyclic com u Hovhan 25, in particular in large inormatsionnyh and steering systems "

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the device; figure 2 is a functional diagram of the operational register; in fig. 3 is a functional block diagram.

The device contains operational, 5 register 1, shift register 2, output Output 3, unit 4 sets the direction of transmission, information inputs, outputs 5, input Broad 6, Reset input 7, trigger 8, control unit 9, 0 pulse generator 10, unit 11 sync-, ronization, element I 12 and the counter 13 pulses,

Operational register 1 (Fig. 2) contains the element OR 14, the register 15 d5 and adders 16 modulo two.

The control unit (FIG. 3) contains a pulse counter 17, an element OR 18, a pulse shaper 19. Synchronization unit 11 is a Q programmable ROM KR556RT4,

The device works as follows

In the initial state, the device is set by applying a signal to the Reset 7 input; in this case, the counter 17 of the control unit 9, the operational register 1 and the shift register 2 are set in О. Counter 13 support55

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from to K + 1 clock with The device contains operational register 1, shift register 2, output Output 3, block 4 sets the direction of transmission, information inputs - outputs 5, input Input 6, input Reset 7, trigger 8, control block 9, generator 10 pulses, block 11 synchronization, 10 element And 12, the counter 13 pulses 3 Il.

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lives in the initial state by the signal from the second output of the counter 17 of the control block 9, which sets the direction of transmission to the block 4 from the inputs-outputs 5 to the output 3, as well as the mode of parallel recording of information in the shift register 2 and the operational register 1. The trigger 8 is reset clock frequency generator 10 in the absence of a signal at the input Input 6.

The operation of the device begins with the filing (mn) of the bits of the t-bit information message to the inputs / outputs of block 4. Then the device receives an input signal, which is written to the trigger 8 by the clock frequency of the generator 10. The output signal from the trigger 8 is fed to the input of the block 11 synchronization, which from its first output generates a signal to the enable input of block 4. Information from the inputs-outputs 5 through block 4 is fed to the inputs of parallel recording of the operational register 1 and shift register 2 "Simultaneously with the opening of block 4, block 11 sync tions from the third output produces synchronizing pulses for the shift register 2, on which there is a record of information in a parallel format. Then the signal is removed from the input of Input 6 and the trigger 8 returns to its initial state, removes the signal from the fifth input of the synchronization unit 11, closes the block 4 and simultaneously increases by one the state of the counter 17 of the control unit 9, which is a signal from the first output sets the required state of the first input of the synchronization unit 11.

Next, the remaining n bits of the t-bit message being encoded are fed to the inputs-outputs 5. The second output of the counter 17 of the control block 9 supports the direction of information transfer through the block 4 from the inputs-outputs 5 and the parallel recording mode in the operational register 1 and the shift register 2. Then, a second signal is fed to the device at input Input b, which is recorded in trigger 8 and opens block 4 through synchronization unit 11. Simultaneously with opening unit 4, synchronization unit 11 (in accordance with the signal level to the first input from the first output of counter 17) from its second output, it issues synchronization pulses to the operational register 1, according to which information is recorded into it in a parallel format. The signal is then removed from the Input input and the trigger 8 returns to the initial state and through the synchronization unit 11 closes the unit 4, simultaneously increasing by one a unit the state of the counter 17, which by a signal from the second output changes the transmission direction of the unit 4, translates the shift register 2 and the operational the register 1 from the parallel writing mode to the shift mode removes the initial setting signal from the counter 13 and sets the state of the second input of the synchronization unit 11, and the clock part appears on its second, third and fourth outputs that the generator 10, The incoming clock inputs simultaneously to the operating register 1, shift register 2, and the counter 13 starts a procedure for scores in operational control word register 1.

After counting the required number of pulses, the counter 13 outputs a signal to the fourth input of the synchronization unit 11, which opens block 4 on its first output, and the control word added in operational register 1 is output in parallel format from block 4 to the outputs-inputs 5 and to the second input of the AND element 12, which transmits the clock frequency of the generator 10 from its first input to the output 3. At the end of the last clock pulse of the generator 10, the series 1644393 is removed from the series necessary for calculating the control word

From the output of the counter 13, the element 12 is closed, through which a single pulse passed from the generator 10 to the output 3, and thus a signal was generated Output for reading the control word from the device

On the falling edge of the signal from the output of the counter 13, the driver 19 through

The 10th element OR 18 will reset the counter 17, which, with its outputs, brought the device to the initial state. This cycle of operation of the device ends and it is ready

5 in for the next cycle.

The control word in the operational register 1 is calculated as follows:

After the second signal at the input

20 Input 6 m-bit coded message is contained in shift register 2 (m-n bits) and register 15 (n bits). Code polynomial F (x) belonging to the cyclic code,

5 is located on the initial information polynomial U (x) and the chosen constituent polynomial K (x). To do this, multiply the initial polynomial U (x) by a monomial of the same degree as the constituent polynomial

(xn) "From the multiplication of a polynomial by a monomial of degree n, the degree of each member of the polynomial increases by n, which is equivalent to assigning n zeros from the low order of the polynomial. As a result, control word bits are written instead of these zeros. The values of the control bits are the result of the division of U (x). f x on K (x), i.e.

F (x), H «f :, oy + 1 $,

where 0 (x) is the quotient, and R (x) is the remainder of dividing U (x) by K (x), which 5 is the control word.

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Taking into account the rules of binary arithmetic, in terms of the addition function modulo two, we obtain the ratio

0 F (x) U (x) xh + R (x)

The division is carried out by successively adding modulo two dividers first with the senior 5 members of the dividend, and then with the senior members (starting with the first significant member) of the resulting balance until the degree of the remainder becomes less than the degree of the divider.

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In the operational register 1, the OR mode 14 controls the operation mode of the register 15 depending on the current value of its low-order bit. For logical O, a shift from bit to bit is performed on the internal links in register 15 and the next bit is recorded from a consecutive input to the higher T (n-1) bit, and for logical 1 a bit is written the modulo two summation result inputs. Thus, a binary division operation is performed by 1 modulo two summation and writing to the next bit (t, e сд shift).

D 1I charge control word requires the participation of each bit of the information word in the feedback link from the low bit of register 15 to the adders 16 modulo two. First, (ni) clock is processed in n bits, originally located in operational register 1, since one-two low-order processing will be performed automatically by filling register 15 in the second Entry cycle, during () cycles, bits are processed Shifting from shift register 2 “As information is advanced in shift register 2, zeros are formed, which, when processed in register 15, are successively replaced by bits of the control word,

As a result, (n-1) + (m-n) m-1 is necessary for the accrual and output to the control word output device.

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Claims (1)

Thus, the cycle of the prototype, the time of encoding and issuing a control word consists of (t + K) clock cycles of the generator, where it is the width of the encoded binary word of K is the number of control characters, J Invention formula A device for encoding binary messages containing a generator Q 5 Q 0 pulses, the output of which is connected to the first input of the element I, the control unit, the first output of which is connected to the reset input of the pulse counter and the control inputs of the modes of the operational register and the shift register, the output of which is connected to the serial information input of the operational register, is characterized by the fact that In order to improve the speed of the device, a block specifying the direction of transmission and a synchronization block are entered into it, the first and fourth outputs of which are connected respectively to the block enable input setting the transmission direction and the synchronization inputs of the operational register, shift register and pulse counter, the output of which is connected to the second input of the And element, the first input of the synchronization unit and the first reset input of the control unit, the second output of which is connected to the second input of the synchronization unit, the third and fourth inputs which are combined respectively with the trigger synchronization input and the input of the transmission direction of the block, the transmission direction assignments and are connected respectively to the output of the pulse generator and the output of the control unit, the output of the trigger is connected to the fifth input of the synchronization unit and the synchronization input of the control unit, the second reset input of which is combined with the reset inputs of the operational register and the shift register and is the device reset input, parallel information inputs-outputs of the operation register and parallel inputs the shift register is connected to the first inputs-outputs of the block specifying the direction of transfer, the second inputs-outputs of which are information inputs-outputs of the device, information the trigger input and output of the AND element are respectively the input of the input and the output of the output of the device. 1c t FIG. 2 77 Fig.Z