SU1642463A1 - Extreme numbers detector - Google Patents

Abstract

The invention relates to computing and can be used in information computer systems. The purpose of the invention is to expand the functionality of the device by determining the extreme numbers, taking into account their absolute size and sign. The device contains comparison unit 1, registers 2 and 3, switch 4, multiplexer 5, recording unit 6, trigger 7 and elements EXCLUSIVE OR 8, and 9 , NOT 10. The device simultaneously determines the maximum and minimum numbers of the consecutively entering numbers at the device input, taking into account their sign. In addition, the device provides the ability to determine extreme numbers by absolute value. 1 з „п„ ф-л, 3 Il. with SB

Description

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The invention relates to computing and can be used in information computer systems.

The purpose of the invention is to expand the functional capabilities of the device by making it possible to determine extreme numbers with regard to their absolute values and sign.

Fig. 1 shows a functional diagram of the device for determining extreme numbers; 2, a timing diagram of the formation of the signals for writing extreme numbers into the first and second registers; on fig.Z - functional diagram of the recording unit.

The device for determining extremal numbers contains a block 1 of comparison, the first 2 and second 3 registers, switch 4, multiplexer 5, block

6 records, T-flip-flop 7, elements of the IS-KEY or 8, AND 9 and NOT 10, information inputs 11.1-11.ti devices, clock input 12 devices and outputs of the maximum 13.1-13.p and minimum 14.1-140p numbers.

Record block 6 contains T-flip-flop 15, first 16, second M and third 18 elements AND, first 19 and second 20 elements OR, element 21, information, input 22, prohibition 23, address input 24 and first 25 and second 26 exits.

A device for determining extreme numbers works as follows.

Before starting to work, the setup input of trigger 15 of recording unit 6 receives a pulse, according to which trigger 15 is reset (setting circuit not shown) о State of registers 2 and 3 and trigger 7 at the moment the device starts working is indifferent. For definiteness, we assume that the trigger and registers 3 and 2 are in the initial state.

At the initial moment of time, the first clock pulse at the input 12 of the device, which coincides with the arrival of the first number at the information inputs of the device 11.1-11, p, arrives at the information input 22 of the recording unit 6. Since the trigger 15 is in the initial state, the zero signal with its output elements 16 and 18 are closed at the output of the output, as a result of which the unit does not respond to the control

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signals on input 23 of the ban and the address input 24 "

A single signal from the inverse output of the trigger 15 permits the passage of the signal from the information input 22 of the recording unit through the element 17 and the elements OR 19 and 20 to both outputs of the recording unit. The same signal from the output of the element 17 also goes to the output of the trigger 15 of this pulse is set to one, blocking the passage of subsequent pulses from information input 22 of the block through the element AND 17 and elements OR 19 and 20 to the first 25 and second 26 outputs of the block and allowing the passage of subsequent pulses from input 22 through the element 16 Do 18 under control of signals at the inputs 23 and 24 on one of the recording unit 25 outputs

Thus, the first clock pulse at the input 12 of the device causes the appearance of pulses at both outputs of the recording unit, which are fed to the C inputs of registers 2 and 3, respectively, and they simultaneously record the first number from the numeric sequence received at the inputs 11.1-11.11 of the device. The first clock pulse from the input 12 of the device enters, besides the recording block 6, the second input of the And 9 element. The passage of this pulse through the And 9 element to the C input of the trigger 7 is determined by a signal from the output of multiplexer 5 received through the HE 10 element to the first input element 9. If there is a zero signal at the output of multiplexer 5, the trigger on the leading edge of the signal arriving at its C input changes its state to the opposite, and if the signal at the output of multiplexer 5 5 is single, then the signal from the element is NOT 10 blocks element 9 and rigger

7 does not change its state. The value of the signal at the output of multiplexer 5 depends on the absolute value and the sign of the first number.

Let us assume that the number received in the work cycle is positive.

In this case, since registers 2 and 3 are in the initial state, trigger 7 does not change its state

on the first clock pulse. The trigger 7 is in the initial state, and the first channel of the switch 4 is opened with a zero signal from its output. From output 0

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Dov Switch 4 module number,

the move in register 2 is fed to the second group of inputs of unit 1 of the comparison. The same signal from the output of the trigger 7 is fed to the address input of the recording unit 6, preparing its first channel for opening, and to the address input A3 of the multiplexer 50

Further operation of the device depends on the sign and modulus of the number arriving at the information inputs 11.1-11 of the device. Opening the corresponding channel of the multiplexer 5 and the appearance of a single or zero signal at its output depends on

the sign of the number on the information input 11 „1 of the device arriving at its second address input;

the result of comparing the sign of the number at the input 11.1 of the device with the sign of the number in register 2 or 3 on the element EXCLUSIVE OR 8 (the first bits of registers 2 and 3 are significant, and a positive number corresponds to zero in the sign digit, negative - unit) arriving at the address input A 1 of multiplexer 5;

the state of trigger 7 defining the signal at address input A3 of multiplexer 5, i.e. which determines which number (maximum or minimum) to write;

the result of comparing the number module at the information inputs 11.2-ll.n of the device arriving at the first group of inputs of the comparison unit 1 with the module of the number arriving at the second group of inputs of this block from the output of the switch 40

The values of the signals at the output of multiplexer 5, depending on the listed conditions, are given in the L table.

As can be seen from the table, a single signal at the output of multiplexer 5, when determining the largest number (trigger 7 is in the zero state), appears in the following cases:

the number at the input of the device is greater than the number in register 2 modulo and both numbers are positive;

the number at the input of the device is positive, and the number in register 2 is negative;

the number at the input of the device is less than the number in register 2 modulo and both numbers are negative.

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15

20

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In determining the smallest number (trigger 7 is in the state of one), a single signal appears at the output of multiplexer 5, if

the number at the input of the device is less than the number in register 3 modulo and both numbers are positive;

the number at the device input is negative, and the number in register 3 is positive;

the number at the input of the device is greater than the number in register 3 by the module and both numbers are negative

Consequently, the number analysis scheme, which includes the comparison unit 1, the EXCLUSIVE OR 8 element and multiplexer 5, provides the detection of the largest and smallest of the numbers entered at the input by the devices in registers 2 and 3, respectively, for any signs of the analyzed numbers.

The presence of an extremal number corresponds to the appearance of a single signal at the output of the multiplexer 50

Let the number received at the information inputs 11.1-11. Then during the time from the moment of supplying the inputs 11.1-11. The number to the leading edge of the second clock pulse at the clock input 12 of the device at the output of the multiplexer 5, in accordance with item 8 of the table, the zero signal is set, which is fed to the inhibit input of block 6 records and blocks its operation, as well as through the element NOT 10 unlocks the element AND 9. The second clock pulse goes to the second input of the element 9, and from the output of this element to the clock input of the trigger 7. On the leading edge of this pulse, the trigger 7 switches to a single condition A single signal from the output of the trigger 7 at the switch 4 opens the second channel and the first number module of the comparison unit receives the first number module from register 3, the recording unit 6 is prepared for opening the second channel and a one is also installed at the address input A3 of the multiplexer 5. Since the number at the input of the device is negative, and the number in register 3 is positive, then according to cn 16 of the table at the output of multiplexer 5 with some delay 0

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A single signal is set at the response time of the elements until the end of the second clock pulse at the input 12 of the device.

A single signal from the output of multiplexer 5 through the element NOT 10 blocks the element AND 9 and stops the pulse to the clock input of the trigger 7t This same signal, entering the inhibit input of the recording unit 6, allows the clock pulse from the input 12 of the device to pass through the information input of the recording unit 6 to its output of the second channel and the clock input of the register 3. On the falling edge of the pulse at the clock input of the register 3, the second number is rewritten into it and fed through the open second channel of the switch 4 to the second group of inputs of the unit 1 cf Avneni Since the signs and modules of the numbers at the input 11.1-11.ri of the device and in register 3 become equal, at the output of multiplexer 5 in accordance with sp. Table 13 sets the zero signal

Let in the third cycle of operation at the inputs 11.1-11. And arrive a positive number, greater than the number received in the first cycle of operation. Since in the second cycle of operation the trigger 7 remained in the single state, then the second input of the EXCLUSIVE OR 8 element receives a unit from the first | Vogo bit of the register 3, and the first - zero from the input 11.1, t „e. the number at the input is certainly greater than the number in register 3, and in accordance with item 13 of the table, the output of multiplexer 5, as described above, sets the zero signal before the arrival of the third clock pulse and allows the passage of the third clock pulse to the clock input of the trigger 7 through the AND 9 element. On the leading edge of this pulse, the trigger 7 is set to the zero state and as a result, the second group of inputs of the comparison unit 1 receives the modulus of the number from the register 2, and the second input of the IC element is DRIVER OR zero — the sign of this number but. Since the number at the device's output is positive, a zero signal appears at the output of the EXCLUSIVE OR element, and the output of multiplexer 5 in accordance with n, 3 of the table is one. Due to the fact that the modulus of the number

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at the second input of comparison unit 1 is larger than at the first, a single signal is generated at the output of this comparison unit, which passes through the open first channel of multiplexer 5 to its output and removes blocking from the inhibit input of recording unit 6. The pulse from the clock input 12 of the device passes through the open first channel of the recording unit 6 and, with its falling edge, writes to the register 2 the number received in the third cycle of operation.

In the fourth cycle, let the device receive a positive number greater than the number received in the third cycle at the inputs 11.1-11 of the device. Then, as the trigger 7 remained in zero state in the previous operation cycle, after the appearance of the number at the inputs 11.1-11. In accordance with clause 3 of the table, a unit is set at the output of multiplexer 5 and blocks the receipt of a clock signal at the trigger input 7, which does not change its state in a given clock cycle. The clock pulse goes through the open first channel of the recording unit 6 to the clock input register 2, and at its trailing edge in the register 2 is recorded the new number.

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If the state of the trigger 7, which determines the mode of selecting an extremal number (the zero state selects the maximum number, the single number selects the minimum number), coincides with the input of the 11 "1-11.p device, the corresponding extremum number (as described in the example of device operation in the fourth clock cycle) switching of the trigger 7 into (the opposite state does not occur, since if the received number turned out to be, for example, the maximum, it is not necessary to analyze this number in order to detect the minimum number ”

The time diagram of the signals at the information inputs 11.I-11, p and the clock input 12 of the device, as well as at the outputs of multiplexers 5, recording block 6, trigger 7 and elements AND 9 and OR 10 when operating in the second, third and fourth cycles is shown in FIG 2,

Further operation of the device is similar to that described above.

Thus, the device for determining extreme numbers allows determining at the same time the maximum and minimum numbers of successively incoming numbers at the device input, taking into account their sign.

In addition, the device provides the ability to determine extreme numbers by absolute value. To do this, the input 11.1 of the device sign must be given during the work cycle a constant level zero, or one. In the first case, in register 2, the maximum will be allocated, and in register 3, the minimum absolute value, in the second case, vice versa.

Claims (1)

Invention Formula 1 A device for determining extreme numbers containing two registers, a switch, a comparison unit and a trigger whose output is connected to the control input of the switch, whose information outputs are connected to the inputs of the first group of the comparison unit, the inputs of the second group of which are connected to the information inputs of the first and second the registers whose bit outputs are connected respectively to the information inputs of the first and second switch groups and are respectively the maximum and minimum number of outputs Features, in order to extend the functionality by defining extreme numbers with regard to their absolute size and sign, a multiplexer, a recording unit, an EXCLUSIVE OR element, an AND element, an NOT element, and the first register information inputs are inputs the device number, the sign input of the device number is connected to the sign inputs of the first and second registers, the first control input of the multiplexer and the first input of the EXCLUSIVE OR element, the second input of which is connected to the sign the output of the switch, and the output with the second control input of the multiplexer, the third control input of which is connected to the trigger output and the address gap of the recording unit whose inhibit input is connected to the output of the multiplexer and NOT to the first input of the I element whose output is connected to the counting trigger input, and the second input is the clock input of the device and is connected to the information input of the recording unit, the first and second outputs of which are connected respectively to the clock inputs of the first and second registers, output More the comparison unit is connected to the first and second information inputs of the multiplexer, the third and fourth information inputs of which are connected to the output Less than the comparison block, the inputs of the logical zero and the logical unit of the device are connected respectively to the fifth, sixth, seventh and eighth information inputs of the multiplexer. 2 о The device according to 1, differing from the fact that the recording block contains a trigger, the first and third elements are AND, the first and second elements are OR, and the element is NOT, with the first inputs of the first, second and third elements AND are interconnected and connected to the information input of the block, the second input of the first element I is connected to the second input of the third element AND and connected to the input of the block inhibit, the third input of the third element II is connected to the address-1 input of the block and through the element is NOT connected to the third input of the first element AND , right, my trigger output with one with the fourth inputs of the first and third elements, and the inverse output of the trigger is connected to the second input of the second element, whose output is connected to the counting input of the trigger and with the first inputs of the first and second elements OR, the outputs of the first and third elements AND are connected respectively to the second inputs the first and second elements OR, whose outputs are respectively the first and second outputs of the recording unit