SU1515172A1 - Device for interfacing two processors common memory - Google Patents

Abstract

The invention relates to computing and can be used to create multiprocessor computing systems. The aim of the invention is to expand the field of application of the device by allowing the two-way exchange of information between the RAM and each of the processors associated with it. This is achieved by the fact that the second bus driver 3, the multiplexer 5 of the RAM control and the element NOT 7 are additionally introduced into the device. 1 sludge.

Description

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The invention relates to computing and can be used to create multiprocessor computing systems.

The aim of the invention is to expand the field of application by allowing the two-way exchange of information between the RAM and each of the associated with. her processors.

On what :, the structure of the proposed device is shown.

The device contains a main memory unit 1, the first and second bus drivers 2 and 3, the address multiplexer 4, the memory control multiplexer 5, the trigger 6, the HE element 7, the bus addresses 8 and 9 of the first and second processors, input 10 and 11 of the request Accessing the main memory unit of the first and second processors, outputs 12 and 13 providing access to the main memory unit to the first and second processors, buses 14 and 15 controlling the operation mode of the main memory unit of the first and second processors, bus 16 and. 17 accessing the RAM of the first and second processors, bus 18 and 19 data of the first and second processors, first and second processors 20 and 21.

The device works as follows.

The processor accessing the memory block 1. sets a signal at the input 10 of the access request to the memory block 1 by switching the trigger 6 to a state of one and thereby allowing the address from the address bus 8 to pass through the address multiplexer 4 the inputs of the block 1 RAM. At the same time, the operation of the first bus driver 2 and the activation of the memory control multiplexer 5 is ensured. The processor 20, receiving a signal from the video access control unit 12 to the RAM 1, generates signals on the buses 14 and 16 of controlling the operation mode of the RAM 1 and accessing the RAM 1, thereby selecting the switching direction of the first bus shaper 2 and providing control over the operation mode (recording or combining information) of the RAM unit 1. Upon completion of the cycle of work with block 1 opera

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The memory processor 20 removes the signal from the input 10 of the access request to the main memory unit 1 and the device enters the idle mode.

When accessing block 1, operating unit 1, mi of the second processor 21, the device operates in a similar way.

At the simultaneous appearance of signals at inputs 10 and 11 of the access request to memory 1, trigger 6 saves its state by servicing one of the processors in the same way as described process.

By (just removing the signal from input 10 or 11 of the access request to block 1 of RAM, processor 20 or 21, which gained access, trigger 6 switches due to the presence of a request signal from another processor 20 or 21 at its input and the device serves another processor, respectively .

Claims (1)

Invention Formula A device for interfacing two processors through a common memory containing an operative memory block, an address multiplexer, a first bus driver, a trigger, the first and second information inputs of the address multiplexer being connected to the address outputs of the first and BTOpoi processes, the information output the multiplexer of the address is connected to the address 1st, the memory unit enters, the information input / output of which is connected to the first information input / output of the first bus driver, the second information the input-output of which is connected to the input-output data of the first processor of the device; and each of the processors associated with it, a second bus driver, a memory control multiplexer and a NOT element are entered into it, the first information input Exit Forsch ovatel second bus connected to informatsionnm vhodom- 515 the output of the memory block, the second information input-output of the second bus driver is connected to the input-output data of the second processor of the device, the output of which is connected to the inverse reset input of the trigger, the inverse input of which is connected to the output of the request of the first processor of the device -the record from the first processor of which is connected to the control input of the first bus driver and the first information input of the first group of the control multiplexer the memory, the second information input of the first group of which is connected to the exchange control output from the first processor of the device, the output of the read / write control from the second processor of the device is connected to the control input of the second bus for10 5172b world leader and the first information input of the second group of the memory management multiplexer, the second information input of the second group of which is connected to the exchange control output from the second processor of the device, the first information output of the memory management multiplexer is connected to the memory control read / write input, input exchange control of which is connected to the second information output of the memory control multiplexer 15, the control input of which is connected to Exit trigger input acknowledgment request from the first processor unit and the input of NOT circuit whose output is connected to an input of the bus resolution Vuori shaper and the input confirmation request to the second processor unit. 0 Editor Y. Sereda Compiled by V. Gerashchenko Tehred L. Oliynyk Proof-reader V. Kabatsiy Order 6277/46 Circulation 668 VNIIPI State KONfMTera according to inventions and discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, 4/5 Raushsk nab. Production and Publishing Combine Patent, Uzhgorod, ul. Gagarin, 101 Subscription