SU1564066A1 - Information device - Google Patents

Abstract

The invention relates to the automation of production, in particular, to receiving information from equipment status sensors, and can be used in flexible production systems for machine building and instrumentation, namely, in racking warehouses, automated transport lines for interrogating sensors, and also in security devices. The purpose of the invention is to increase the reliability of work. The device contains sensors, blocks of elements of the register cells, including cells of a sequential shift register, located next to the corresponding sensors, smoothing rectifiers, and blocks for selecting the duration of pulses. The device also includes a block of test signals, a three-bus connection harness: common, synchronization and communication between the register cells, a control unit, including an amplifier, a synchronization pulse width shaping unit, a data polling shaping unit, a sync pulse shaping unit, D- trigger, "Sensor information" output bus, test signal test block, "Split Register Split", "Split Register Split" and "Spread Register OK", output bus, Read Enable switch, output bus pulse generator, input address sensor busses. 6 hp ff, 3 ill.

Description

The invention relates to the automation of production, in particular, to receiving information from state sensors - equipment, and can be used in flexible production systems (FMS): racking warehouses, automated transport lines controlled from computers, in particular, in roller tables for polling sensors, as well as in alarm systems.

The aim of the invention is to increase the reliability of operation.

FIG. 1 shows a functional diagram of the proposed device for receiving information from spaced sensors; in fig. 2 - time diagrams of signals (in the control points of Fig. 1): a - clock frequency synchronization at the output of the generator 21; b - the first clock pulse transmitted through the element OR-NOT 32; in - signal from the inverse output of the counter 31; g - synchronization signals from the output of the amplifier 9 power on the bus 40; (d) rectified voltage at the output of smoothing rectifiers 4; e - signal recording information in the cell register 3 with the output of block 5 of the selection; W - signal of the test unit at the output of block 6 test signals; h - sensor information 1.4 at the output of register 3.4; and - sensor information 1.3 at the output of the register 3.3 cell; k - sensor information 1.2 at the output of the 3.2 register cell; l - information of sensor 1.1 at the output of the register 3.1 cell; m - four sync pulses at the output of the element OR NOT 36; n is the signal at the output of the first low-order bit of counter 35; n is the signal at the output of the second least significant bit of the counter 36; p - signal at the inverse of the output of the higher razOS

C5 O

p yes counter 35; C - two clock pulses at the output of the element OR NOT 30; t is the signal at the output of the first low-order bit of counter 29; y is the signal at the output of the most significant bit of counter 29; ip is the unit signal at the output of the comparator 37 at the moment of coincidence of the number at the inputs 22 of the sensor address with the states at the outputs of the counter 35; x is the information of the interrogated sensor on the bus 14 recorded from the output of the register cell 3 to the trigger 13; q - information of test signals at the output 01 of the register 25; h - information of test signals at the output 02 of the register 25; w - signal on bus 16 "Short-circuit in the spaced register from the output ele10

There is a counter 31, an element OR-NOT 32, an inverter 33, an element AND-NOT 34.

The sensor sensing unit 11 comprises a counter 35, an OR-NOT 36 element and a digital comparator 37.

Communication harness 7 includes a common bus 38, a communication bus 39 between registers 4 and a synchronization bus 40 and is connected to control unit 8, the outputs of which are connected to computer 41.

The amplifier 9 power can be performed on transistors or cells of integrated circuits with a powerful output having a current limit, and is intended

ment or not 26; u - signal on bus 17 1 {- to form a pulse bus; sync pattern in a spaced register from the output of the element 27; e - signal on bus 18 “The spaced register is normal from the output of the EXCLUSIVE OR 28 elements; u is the signal on the bus 20 "Resolution of reading from the output of the element E 19; in fig. 3 is a diagram of the communication of the spaced sensors on the tires with the control unit.

The device receiving information contains sensors 1.1 ... 1.P, each of which is installed, for example, in the corresponding cell

the load capacity of which is sufficient for the operation of all the cells of the 3 registers. Pulse generator 21 clock synchronization frequency is designed to generate a clock frequency. The test signals generating unit 6 can be made similarly to the elements and links of the unit 2 register cell elements, to the information input of which the logical "1 is fed, and to the shift input - the logical" O, i.e.

rack warehouse,

n blocks 2.1 ... 2.P. Elele 25 block 6 is connected

they are connected to the input of the record, with the input being

cops of the register of information, including cells 3.1 ... 3.P, structurally mated with the corresponding sensors, smoothing rectifiers 4.1 ... 4.P, blocks 5.1 ... 5.P. of selecting the duration of synchronization pulses, block 6 forming test signals, a harness 7 of communication with a control unit 8 consisting of a power amplifier 9, a synchronization pulse shaping unit 10, a sensor polling generation unit 11, a burst shaping unit 12, trigger 13, output bus 14 "Sensor information, a block 15 checks t Stow signals output buses "closure in spaced register 16," Open in spaced register 17, "Diversity register serviceable 18, AND gate 19, the output bus 20" Resolution read pulse generator 21, input bus bars 22 'of the sensor address. Smoothing Straighteners 4

the cells are 3 registers, and the synchronization input is with the synchronization bus 40. For reliable operation of the register, the common bus 38 and the communication bus between the registers should preferably be made in the form of a twisted pair, and the bundle 7 should be placed in the screen or in the grooves of the metal structures connected to the common wire of the control unit 8. Sensors 1 are connected to the information inputs of register cells 3, the power inputs and recordings of which are connected

35 with the outputs of the smoothing rectifiers 4 and the selection blocks 5, and their inputs to the synchronization bus 40, which is connected to the control unit 8, namely, the output of the power amplifier 9, the input of which is connected to the main output of the synchronization pulse width generating unit 10. The auxiliary output of the unit 10 is connected to the permission input and the installation input to the initial state of the sensor acquisition unit 1 1, as well as

performed on the diode and the smoothing capacitor of the initial state of the blockiness sufficient for reliable operation of the register cell. Each block 5 for the selection of the duration of the synchronization pulses contains a time delay element 23 and a diode 24 connected by a cathode to the input of the synchronization pulse generation cell 12. The resolution input of the block 12 is connected to the auxiliary output of the sensor polling unit 11, and the auxiliary output is connected to the installation input to the initial one

ment 23 is the delay, and the anode - to its output. 50, the state of the unit 10 for generating the control unit 15 for checking the test signals contains two cells of the shift register 25, the elements OR NOT 26 and AND 27, the EXCLUSIVE OR 28.

The sync pulse shaping unit 12 contains a score OR NOT 30.

A unit 10 for generating controlled duration of synchronization pulses for the duration of synchronization pulses. The trigger input of the trigger 13 is connected to the main output of the sensor polling unit 11, and the output to the output bus 14 of the device "Sensor information. 29 and the element 55 of the synchronization input of the test signal testing unit 15 is connected to the main output of the sync pulse shaping unit 12, and its information input is

There is a counter 31, an element OR-NOT 32, an inverter 33, an element AND-NOT 34.

The sensor sensing unit 11 comprises a counter 35, an OR-NOT 36 element and a digital comparator 37.

Communication harness 7 includes a common bus 38, a communication bus 39 between registers 4 and a synchronization bus 40 and is connected to control unit 8, the outputs of which are connected to computer 41.

The amplifier 9 power can be performed on transistors or cells of integrated circuits with a powerful output having a current limit, and is intended

to form a pulse synchronization bus, the load capacity of which is sufficient for the operation of all the cells of the 3 registers. Pulse generator 21 clock synchronization frequency is designed to generate a clock frequency. The test signal generating unit 6 can be made similarly to the elements and links of the unit 2 register cell elements, to the information input of which the logical "1 is fed, and to the shift input - the logical" O, i.e.

stroke of block 6 is connected

they are connected to the recording input, and the output of block 6 is connected

with input shifting p-and

the cells are 3 registers, and the synchronization input is with the synchronization bus 40. For reliable operation of the register, the common bus 38 and the communication bus between the registers should preferably be made in the form of a twisted pair, and the bundle 7 should be placed in the screen or in the grooves of metal structures connected to the common wire of the control unit 8. Sensors 1 are connected to the information inputs of register cells 3, the power inputs and recordings of which are connected

5 with the outputs of the smoothing rectifiers 4 and the selection units 5, and their inputs to the synchronization bus 40, which is connected to the control unit 8, namely, the output of the power amplifier 9, the input of which is connected to the main output of the synchronization pulse shaping unit 10. The auxiliary output of the unit 10 is connected to the permission input and the installation input to the initial state of the sensor acquisition unit 1 1, as well as

VC ° D ° M of the installation of the initial state of the block 12 of the formation of a package of sync pulses. The resolution input of the block 12 is connected to the auxiliary output of the sensor polling unit 11, and the auxiliary output is connected to the installation input to the initial one

with the information input of the trigger 13 and the output of the first cell 3 register. The first, second and third outputs of block 15 are connected respectively to the output buses of the device "Short circuit in spaced register 16," Open circuit in spaced register 17, "The spaced register is valid 18. The first input of the And element 19 is connected to the third output of the signal testing unit 15, the second input - to the auxiliary output of the blotter input - with its synchronization input. The output of the element OR NOT 36 is connected to the synchronization input of the counter 35, the installation input in the About of which is connected to the installation input to the initial state of the block. The outputs of the lower bits of the counter 35 are connected to the first group of inputs of the comparator 37, the second group of inputs of which is connected to the information inputs of the block, and the main output of the block is connected to the output of the figure 10 to form a controlled long duration comparator 37

synchronization pulses, and the output is a device for receiving information from different terminals of the output bus 20 "Read permission of the device. Impulse generator 21

connected to the synchronization inputs of block 12

Senna sensors works as follows.

In the initial state, the clock pulses

generating a packet of sync pulses, blocking the output of the generator 21 (FIG. 2, a) at the same time 10 forming the controlled duration of the synchronization pulses, unit 1 generating the sensor polling. The information outputs of the sensor sensing unit 11 are connected to input inputs to the synchronization inputs of the sensor forming unit of sensors 11, a packet of sync pulses 2, the controlled duration of synchronization pulses 10, to the inputs of the OR-NOT element 32 and the inverter bus 22 "Device 20 sensor address 33 The duration of the impulse is required. In block 15, the test signal test (Fig. 2, d) of the extended pulse

synchronization of the separated register of information collected on blocks 21 ... 2.P of the cell elements is determined by the number of different inputs the synchronization input of the shift register 25 is connected to the synchronization input of the block, the shift input to the information input of the block, and the outputs of the register 25 cells under- 25 p DOV in the counter 31 and the way they are decrypted to the corresponding inputs of the elements OR NOT 26, AND 27, EXCLUSIVE OR 28, the outputs of which are connected respectively to the first, second and third outputs of the block. In block 12 formation

walkie-talkies. In the proposed device, one bit of counter 31 is used. Counter 31 passes through an OR-NOT element 32 pulses produced by generator 21 (in this case, one pulse, Fig. 2.6),

the sync-pulse packet input of the unit to 30 is then connected with the potential at the direct output of the old “0 counter 29 connected to the installation input to the initial state of the block, the direct output of the high bit of the counter to the auxiliary output of the block and the first input of the OR-NOT element 30, the second input whom

This counter's counter locks the output of the OR-NOT 32 element and gives permission for the passage of pulses through the IS-NE 34 element (the signal in Fig. 2 should be regarded as inverse). Since the element

connected to the synchronization input of the block, 35 AND-NOT 34 from the output of the generator 21 enters the third input - to the input of the resolution of the block, an inverse signal, then the total duration

and the output - with the counting input of the counter 29 and the main output of the block. In block 10, the generation of the controlled duration of synchronization pulses is auxiliary you-. the block stroke is connected to the inverted output of the higher bit of the counter 31, the counting input of which is connected to the output of the OR-NOT 32 element, the synchronization input of the block is connected to the first input of the OR-NOT 32 element

pulse recording increases by 1/2 period (Fig. 2, d). The clock pulses from the main output of the unit 10 pass through the power amplifier 9 and through the synchronization bus 40 are fed to the test signal generating unit 6 and 2.1 .2 blocks of register cell elements, i.e., the inputs of the smoothing rectifiers 4.1 ... 4. P and blocks 5.1 ... 5.P. Selection of the duration of clock pulses.

and the input of the inverter 33, the output of which is under-45 blocks 5.1 ... 5. The selection of the selection eliminates the input to the first input of the element AND-NOT 34. The second input of the element AND-NO 34 is connected to the second input of the element OR-NOT 32 and to to my output of the higher bit of the counter 31, the input of the setting in “About which is the connection to the input circuit of the cell 3.1 Z.p. register of the sync pulse, the duration of which is less than the delay of the element 23 (Fig. 2, e), and with a duration exceeding the duration of the delay

It is not connected with the installation input to the initial state of 50 elements 23 of the formed expanded-block 10, and the main output of the block 10 of the connecting impulse, blocks 5.1 ... 5.P simultaneously with

is not with the output of the element AND-HE 34. In the sensor polling unit 1, the auxiliary output of the block is connected to the inverse

by synchronization, the write signals to the cells 3.1 ... Z.p and the block 6 for the formation of test signals are generated. As a result in them

the output of the most significant bit of the counter 35, pr - "records the information of sensors 1.1 ... 1. My output is connected to the first input and test signals. In block 6, where the input

the element OR NOT 36, the second input of which is connected to the input of the block resolution, and

the recording is combined with the shift and information inputs, the signal is recorded in the first cycle

The third input is with its sync input. The output of the element OR NOT 36 is connected to the synchronization input of the counter 35, the installation input in the About of which is connected to the installation input to the initial state of the block. The outputs of the lower bits of the counter 35 are connected to the first group of inputs of the comparator 37, the second group of inputs of which is connected to the information inputs of the block, and the main output of the block is connected to the output of the digital comparator 37

The device receiving information from spaced sensors works as follows.

In the initial state, the clock pulses

c Output of the generator 21 (FIG. 2, a) simultaneously in the counter 31 and the method of their decoding. In the proposed device, one bit of counter 31 is used. Counter 31 passes through an OR-NOT element 32 pulses produced by generator 21 (in this case, one pulse, Fig. 2.6),

This counter's counter locks the output of the OR-NOT 32 element and gives permission for the passage of pulses through the IS-NE 34 element (the signal in Fig. 2 should be regarded as inverse). Since the element

pulse recording increases by 1/2 period (Fig. 2, d). The clock pulses from the main output of the unit 10 pass through the power amplifier 9 and through the synchronization bus 40 are fed to the test signal generating unit 6 and 2.1 .2 blocks of register cell elements, i.e., the inputs of the smoothing rectifiers 4.1 ... 4. P and blocks 5.1 ... 5.P. Selection of the duration of clock pulses.

effect on the input circuit of writing cells 3.1 З.п the register of the sync pulse, the duration of which is less than the delay time of the element 23 (Fig. 2, e), and for the duration exceeding the delay time

the recording is combined with the shift and information inputs, the signal is recorded in the first cycle

"1, and the subsequent cycles - the signal" O (Fig. 2, g. W, C, and, K, l). The signal "1 for the entire polling period of the diversity information register passes through all its cells 3.1 ... Z.p in control block 8, which allows to find out at the end of the cycle whether the diversity information register is working correctly. When polling information from the output of cell 1.1, upon completion of the formation of a predetermined recording pulse duration by unit 10, an inverse output potential for the operation of unit 11 of generation of sensor polling is set at the inverse output of counter 31. The clock pulses arrive at the input of the counter 35 through the IL-NE 36 element (Fig. 2, m). The number of bits in the counter 35 is determined from the expression

b logtn + A.l + l, (I)

where n is the number of sensors;

It is the rounding value to the whole mantissa of the logarithm.

At the moment of filling (b -) of the lower bits of the counter 35 (Fig. 2, n, n), the most significant bit is triggered, which by the potential "I from the direct output locks the OR-NOT 36 element. At the same time, the count stops (signal 2, n should be considered as inverse). During the counting time on the digital comparator 37, the current combinations of the lower bits of the counter 35 are compared with the installed combination on the input tires 22 "Device sensor address. When the combinations are equal, a pulse is generated at the output of the comparator 37 and at the main output of the sensor polling unit 11 (Fig. 2,), which is fed to the trigger trigger input 13. Information to the trigger input 13 receives information from the output of the information register cell 3.1 (Fig. 2, l), which is fixed on the output bus 14 "Sensor information until the next arrival of the comparison pulse 37 of the comparator 37 (Fig. 2, x). This information is perceived by an external device, such as a computer or a digital display device (not shown), only in the case of a read signal on the output bus 20 "Read resolution (Fig. 2, 10) if, from the test signal testing unit 15, permission is given to the element 19 (Fig. 2, e) from the output bus 18 "The spaced register is healthy.

When testing test signals, the resolution input of the sync pulse shaping block 12 and the input of the element ORI 30 from the inverse output of the high bit of the counter 35 receive a resolution signal (Fig. 2, p). Since earlier, the counter 31 was set to allow a potential O on the input of counter 29, it begins to fill by an amount equal to the number of test information bits to be checked, in this case two (Fig. 2, c). According to expression (1), the number of bits of the counter 29 is also equal to two. The high bit (Fig / 2, t) and the potential "1 locks the OR-NOT 30 element, then the counter 31 (Fig. 2, y) at the inverse output of which the potential appears" 1 (Fig. 2, c), which sets in initial state the units for forming the interrogation of sensors 11 and the formation of a packet of clock pulses 12, thus completing the cycle of interrogating the diversity register 2 of information. During operation of the counter 29 from the output of the element OR-NOT 30 and the main output of the block 12 of forming a packet of clock pulses (Fig. 2, c), the clock pulses go to the synchronization input of the test signal check block 15 and to the synchronization input of the shift register 25, to the information input of which this time, the pulses of the test signals arrive (Fig. 2, l). Since the number of test information bits to be checked is two, then the number of the shift register 25 cells is also two. When reliable information arrives, an EXCLUSIVE OR 28 element (Fig. 2, l, two first cycles) outputs a resolving potential "1 to AND 19, through which the signal passes from the inverse output of the counter 31 (Fig. 2, c) to the" Resolution readout 20 of the device (Fig. 2, y, c, h, e).

The combinations "0,0," 1,1 are a symptom of a failure in a spaced register. The combination "0.0 means that the potential signals do not pass through the spaced register, and this is possible if any communication bus 39 is closed between the cells of the spaced register or synchronization bus 40 on the common bus 38. The combination" 1.1 means that One or all of the control bus of the separated register was broken (in Fig. 2, and, k, l, c, h, w, y, e, y), in the third cycle, an example is shown: the connection bus was broken between the test signal testing unit 6 and block 2 p.

Thus, for the polling cycle of the spaced sensors 1 connected to the information inputs of the register cells 3, the control unit 8 generates a certain number of clock pulses equal to the number of sensors 1 and an additional number of clock pulses for testing the connections of the blocks 2 of the register cell elements with the control block 8. The sensor data is recorded simultaneously at the beginning of the cycle by an extended sync pulse (Fig. 2, d) by individually selecting it over all the write inputs of the register 3 cells through the selection blocks 5. The sensor information 1 recorded in the cells 3 of the register 1 is sequentially shifted by the sync pulses to the trigger 13, and each information bias or sync pulse is counted by the counter 35, the states of which are then compared by the comparator 37 with the states on the current

cycle in the computer or in the programmer of the device for displaying the warehouse cells. The coincidence of the number at the inputs 22 with the number at the outputs of the counter 35 corresponds to the number of shifts of the block of elements of the cells 2 of the register and, accordingly, the number of the polled sensor. The counting of the number occurs from the output block 2.1 of the register cell elements to the beginning of the blocks 2 elements of the register cells. At the moment of equality of numbers with the help of a comparator 37 (Fig. 2, f), the information "1 10 or" O sensor from the output of the blocks of 2 elements of the register cells (Fig. 2, l) is recorded in the register and stored until the next moment of determining the equality of numbers in another

“Units at the outputs of blocks 6 and cells 3 3 and 3.1 (Fig. 2, g, l, l), which received the employment information from the senders 1.1 and 1.3. In the second synchronization cycle, the units are shifted in cells 3.4 and 3.2 (Fig. 2, h, k), in the third - in cells 3.3, 3.1 (Fig. 2, l), in the fourth - in cell 3.2 (Fig. 2 , k), on the fifth - in the cell 3.1 (Fig. 2, l). In the sixth, also at the output of the cell 3.1, “a unit should always be absent when operating correctly. The sixth clock cycle is simultaneously the clock for preparing the recording of sensor information into blocks of 2 register cell elements. Thus, at the output of the cell 3.1, at the input D of the trigger 13 and the input Do of the register 25

cycle (Fig. 2, x). In block 2, the elements of cells 15 in the first cycle appear sequentially in the information sequence of read pulses, the information of the last sensor shifts the test unit pulse followed by zeros (Fig. 2, g, g, l, l, l). Single and

the number of units and zeros "101010, in the first synchronization cycle the information on the occupancy of the first warehouse cell appears, in the third - the third warehouse cell and in the fifth cycle there is a unit of the health test of blocks 2

the next zero pulses in the register elements of the register (Fig. 2, l), during the cycle of the cycle are recorded in the register 25, and using a decoder on the elements OR 26, AND 27, EXCLUSIVE OR 28, the signals for indicating the operability of blocks 2, register cell elements, and for enabling the reading of information stored in trigger 13 by means of a computer or a storage cell occupancy indication device.

The cycle of the proposed device (Fig. 2).

thirty

the second in the sixth also follows zero. In the second and fourth bars in this sequence, zeros appear, since the second and fourth cells of the warehouse are free.

In block 8 of the control unit 10, the generation of the controlled duration of the synchronization pulses generates an extended synchronization pulse in the sixth cycle of the previous cycle according to the setting signal in "O" coming from the sync burst generation unit 12 from the output of the counter 29 to the inputs R of the counters 31 and 35.

Let the number of spaced sensors 1, issuing single signals with occupied warehouse cells, be four. In the first survey cycle, cells 1 and 3 are occupied, in the second - 1, in the third - 1 and 3, in the fourth - 1 and 2 (Fig. 2, l). The external device at the inputs 22 polls the third sensor in the first, second and third cycles, and the second sensor in the fourth (Fig. 2,), i.e., at the inputs 22, respectively, there are three-digit combinations of binary numbers 011 or 010, specified by the corresponding a program from a computer or installed in the programmer of the display device of the storage cells (not shown in Fig. 1). The combination of .000 is not used in this device. In the first cycle of operation of the device at the time of the formation of the extended sync pulse by the formation unit 10 of the controlled duration of the synchronization pulses, its duration is wider than the duration of the preceding synchronization pulses (Fig. 2, d) for each cell 3 register, there is a signal recording information sensors 1 in cell 3 register (Fig. 2, e). With this signal at the end of its action by the falling edge of the extended sync pulse, the synchronization input information is recorded in the cells of the 3 registers. In this case, in the first bar,

“Units at the outputs of blocks 6 and cells 3 3 and 3.1 (Fig. 2, g, l, l), which received the employment information from the senders 1.1 and 1.3. In the second synchronization cycle, the units are shifted in cells 3.4 and 3.2 (Fig. 2, h, k), in the third - in cells 3.3, 3.1 (Fig. 2, l), in the fourth - in cell 3.2 (Fig. 2 , k), on the fifth - in the cell 3.1 (Fig. 2, l). In the sixth, also at the output of the cell 3.1, “a unit should always be absent when operating correctly. The sixth clock cycle is simultaneously the clock for preparing the recording of sensor information into blocks of 2 register cell elements. Thus, at the output of the cell 3.1, at the input D of the trigger 13 and the input Do of the register 25

 In the first cycle, the sequence of ones and zeros of 101010 appears after the first cycle, in the first synchronization cycle, the occupancy information of the first warehouse cell appears, in the third cycle - the third warehouse cell, and in the fifth clock cycle, the health test unit of blocks 2 appears

elements of the register cells (Fig. 2, l), for braid

0

g

the second in the sixth also follows zero. In the second and fourth bars in this sequence, zeros appear, since the second and fourth cells of the warehouse are free.

In block 8 of the control unit 10, the generation of the controlled duration of the synchronization pulses generates an extended synchronization pulse in the sixth cycle of the previous cycle according to the setting signal in "O" coming from the sync burst generation unit 12 from the output of the counter 29 to the inputs R of the counters 31 and 35.

The duration of the setup signal in "O" is determined by the delay time of switching the counters 31 and 29 to the initial state (Fig. 2, y) via the communication bus from the inverse output of the counter 31 to the input R of the counter 29. In the initial state of the counters at the beginning of the formation of the extended the sync pulse by the zero potential of the direct output of the counter 31 by the clock signal of the generator 21 is forbidden to pass through the AND-NE element 34, and by the unit potentials from the inverse output of the counter 31 through the OR-NOT 36 element and from the inverse output of the counter 35 through the OR-NOT 30 element it was decided to pass the zero potential of the forward output of the counter 31 through the element OR NOT 32. At the same time, the inverse output of the counter 31 through the AND 19 cell also generated the read enable signal from the external device stored in the trigger 13 of the sensor information polled in the previous cycle (Fig. 2, c, o), on the bus 14 "Sensor information (Fig. 2, k). A clock pulse (Fig. 2, b) of the generator 21 passes through an OR-NOT 32 element and a back 5 front, after an expiration of the clock frequency period, converts the counter 31 into a single output state, which prohibits further passage of clock pulses

the element OR-NOT 32 is cut and resolves through the AND-NOT element 34. Since the clock signal is inverted at its input, the duration of the extended sync pulse is increased by half a cycle of the generator 21 (Fig. 2, a, db, c, d). Similarly, the zero potential of the inverse output of the counter 31 removes the prohibition on the passage of clock pulses, the inverted elements OR-NO 36, to the counting input of the counter 35 (Fig. 2, m). The switching of the states of the counter 35 occurs in the middle of the clock intervals of information shifts in blocks of 2 elements of the register cells (Fig. 2, d, l, m, n, n) for which the operation of the described device is considered (Fig. 2, d). The number of passable 15 elements OR-NOT 36 pulses to the counting input of the counter 35 is equal to the number of sensors in the separated cells of the 3 registers, in this case the fourth

32, 36 are replaced with OR elements without inversion.

In block 15 for testing test signals, two synchronization pulses by shifting the test information at the DO input in register 25 clear it of the old information and fill it with new (Fig. 2, n, h).

ten

The elements OR NOT 26, AND 27, EXCLUSIVE OR 28 are decoders of the recorded test information in the register 35. The correct passing of the test information through the blocks 2 elements of the register cells corresponds to the combination "10 in the register 25. As a result, the output of the EXCLUSIVE OR 28 on the bus 18 "The spaced register is normal (Fig. 2, e) a single potential appears, which is in the sixth cycle of the information shifts cycle of blocks of 2 cell elements (Fig. 2, m). According to the condition, in the first cycle, a 2 nd gistR during the formation of an extended sync pulse permits the passage of a pulse from the inverse counting output at the output of the 35 meter with code ™ 31 (Fig. 2, c) through the And 19 element to the bus 0 011 at the inputs of the comparator 37 at the output 0 "Resolution of the comparator readout is formed by a pulse (Fig. 2, (Fig.2) stored at this time in trigf), the duration of which is equal to either 25 the period of the clock signals or the duration of the test, if the last encoder is polled. A positive pulse front of the comparator 37 records the information of the polled sensor (in this case, the third one) into the trigger 13, i.e. in the middle of the third information shift cycle, in cell 3 of the register from input D, the "unit" is signaled that one third of the storage cell is occupied (Fig. 2, f, l, x)

Input 22 "Sensor address is set to code" 011 of the third sensor. In case of coincidence

HERE 13 on the sensor information bus 14 (Fig. 2, x), which is perceived by the external device as valid. The combinations "00 and" 11 at the output of register 25 are erroneous and are decrypted, respectively, by the elements OR-HE 26 and AND 27 (Fig. 2, w, y). The appearance of the combination “01 in case of any malfunction in the block 2 elements of the register cells is unlikely, therefore, it is excluded from decoding.

35

Suppose that in the third polling cycle (Fig. 2, e, g, i, k, k) the bus 39 of the connection between the output and input of the 3.4, 3.3 register cells was broken. Then, in the first clock cycle, the units of information 3.1 3.3 register the information units. At the end of the interrogation of the information of the sensors, the last fourth pulse (Fig. 2, m) in the counter 35 switches the highest bit,

Suppose that in the third polling cycle (Fig. 2, e, g, i, k, k) the bus 39 of the connection between the output and input of the 3.4, 3.3 register cells was broken. Then, in the first cycle, the units 3.1 3.3 of the register will write down “units of information which, with its potential, covers the occupancy of the first and second cells of the warehouse,„ -., „„, „,,.,„ ,, „,„ l „, , - "40 a c cell 3.5 of the register will write the test

The setting of clock pulses through the element OR-NO 36 to the counting input (Fig. 2, m), and the potential of the inverse output allows the passage of clock pulses through the element OR-NOT 30 to the counting input of the counting unit. In the second slip of the shift information, "units from cells 3.5 and 3.3 move to cells 3.4, 3.2 and" unit in cell 3.3 is added, since the communication bus is broken

ka 29 (fig. 2, c) and the synchronization input 45 of the information input of the register 3.3 cell

Register 25 of block 15 for testing test signals. The number of pulses is two, since the passage of test pulses through the spaced blocks of 2 elements of the register cells is carried out by the combination "10,

perceived as a "unit arriving at 3.4". Subsequently, for the rest of the cycles, this unit is generated over all remaining shifts of the information sequence, i.e., at the output of a two-pulse at the end of the 50th 3-1 register and at the inputs of the trigger 13 and

formation sequence from the cell exit 3.1. Therefore, the number of bits in the counter 29 is also equal to two (Fig. 2, c, t, y). Counter 29 ends the polling cycle exploded register 2 (Fig. 3, y).

Self-locking of the counters 29, 31, 35 is carried out according to the same type of scheme. If counters have a counting input on the positive front, then the elements OR NOT 30

the register 25 in the third cycle forms the sequence "101111, while the sequence" 101010 must follow, and register 25 instead of the combination 10 when the communication bus 39 between iy., dam and inputs of the register 2 cells is working, the record "11. This combination is decrypted by the element AND 27, and on the bus 17

32, 36 are replaced with OR elements without inversion.

In block 15 for testing test signals, two synchronization pulses by shifting the test information at the DO input in register 25 clear it of the old information and fill it with new (Fig. 2, n, h).

™ 31 (Fig. 2, c) through the AND element 19 onto the bus 0 "Resolution of information reading (Fig. 2) stored at this time in the trigger 13 on the bus 14" Sensor information (Fig. 2, x), which is perceived external device as authentic. The combinations "00 and" 11 at the output of register 25 are erroneous and are decrypted, respectively, by the elements OR-HE 26 and AND 27 (Fig. 2, w, y). The appearance of the combination “01 in case of any malfunction in the block 2 elements of the register cells is unlikely, therefore, it is excluded from decoding.

Suppose that in the third polling cycle (Fig. 2, e, g, i, k, k) the bus 39 of the connection between the output and input of the 3.4, 3.3 register cells was broken. Then, in the first cycle, the units of the information unit will be recorded in the cells of 3.1 3.3 registers. In the second slip of the shift information, "units from cells 3.5 and 3.3 move to cells 3.4, 3.2 and" unit in cell 3.3 is added, since the communication bus is broken

 3.3 register information input

perceived as a "unit arriving at 3.4". Subsequently, for the remaining cycles, this unit is generated over all remaining shifts of the information sequence, i.e., at the output of the 3-1 register cell and at the inputs of the trigger 13 and

the register 25 in the third cycle forms the sequence "101111, while the sequence" 101010 must follow, and register 25 instead of the combination 10 when the communication bus 39 between iy., d and the inputs of the register 2 cells is working, is written the combination "11. This combination is decrypted by the element AND 27, and on the bus 17

13

the potential signaling to the external device about this malfunction (fig. 2, sh). At this time, on the bus 18, the spaced register is faulty from the output of the EXCLUSIVE OR 28 element, the potential zero (Fig. 2, e) prohibits the passage of the read enable signal (Fig. 2, o) by the external device with information of the polled sensor stored in the trigger. 13 (Fig. 2, x).

If in this place, instead of the break of the pro-10, the bus 39 of the connection between the output and the input of the cells 3.4, 3.3 has elapsed onto the common bus 38 of the blocks of 2 elements of the register cells (not shown in Fig. 2), then in the location of the closure in the spaced register 2 zeros are generated. As a result, instead of a sequence

"101010 appears the sequence" 101000, and in register 25 the combination "00 is recorded. This combination is decrypted by the element OR-NOT 26 (FIG. 2, b). An external device from the bus 16 "Closure 20 in the spaced register is given a fault signal and the zero of the EXCLUSIVE OR 28 element prohibits the passage of the signal" Read permission through AND 19 to bus 20 (Fig. 2, o, w). Other types of damage to the communication buses of the spaced register 2 are recognized by the test signal testing unit 15 as a communication interruption, i.e. in the register 25 the combination “11. For example, if the communication bus 39 between the output and the input of a pair of register 2 cells is closed with the synchronization bus and the register 2 power, then the public key current, for example, at the output 0 of the 3.4 register cell, is not enough to shunt the potential of the bus 40, since the power of the amplifier 9 is selected sufficient to power all the 2 blocks of the register cells, therefore, the output DO of cell 3.3 will constantly present the pulse potentials of the sync bus 40 (Fig. 2, d). The negative edge of synchronization at input C is preceded by a single potential at the input DO, therefore, from this moment on, the units in the 2 elements of the register cells will begin to generate units in the output sequence from the output of cell 3.1, and in register 25

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14

signals signals the nature of the malfunction (interruption of any tire, bus-39 closure of the information communication of cells 3 of the register to the common bus 38) and prohibits the passage of false information to an external device, realizing the control of the passage of signals on the communication buses of the separated register.

Communication of the device for receiving information from spaced sensors with a computer can be carried out through a standard interface of parallel input / output of information in which a buffer register is provided. At the same time, signals from input buses 14 are stored. , 16 "A split register closure must be made asynchronously with the interrogation of the buffer register computer data by a bus signal 20" Read permission. Further processing of the information read from the buffer register and the setting of the addresses at the inputs 22 "The address of the sensor is carried out in a computer programmatically.

Claims (7)

1. An information device, preferably for storage racks, containing sensors installed at monitoring positions, an information register having 30 recording cells connected to each information input with a corresponding sensor, and associated with a control unit including a trigger and having an output for connecting with the indicator, characterized in that, in order to increase the reliability of operation, the information register additionally contains, according to the number of cells, the records placed together with the latter in the monitoring positions smoothing rectifiers and power selection pulse widths and recording cell formed of series-parallel connected inputs and effects synchronization to the synchronization bus, common inputs the common bus, each successive cell outputs except the first recording - with posledovatel35 40 The combination of "1. In the case of the 45 information input of the previous The bus 40 to the bus 38 all the current that the amplifier 9 is capable of giving (and in this case it is necessary to limit it) will begin to emit at a low resistance of the short-circuit conductors. The voltage at the output of amplifier 9 will fall, the supply of blocks 2 elements of the register cells will stop, and cell 3.1 will be de-energized, i.e. its output stage will be open, which is equivalent to supplying a logical unit to the DO input of register 25, in which it will also be written at the end of the cycle the combination "11. As a result, for any combinations of faults of three communication buses of the blocks of 2 elements of the register cells, test test block 15 cells, the output of the first cell is connected to the information input of the control unit connected by the output to the sync bus, while the control unit additionally includes the power amplifier of the synchronization pulses 50, the generation units of the controlled duration of the synchronization pulses and the sensor polling and a pulse frequency generator synchronization, the first output of the first of the shaping units through the power amplifier is connected to the synchronization input of the information register, and the second is connected to the enable and setup inputs in and a similar state of the second formation unit and is associated with ten 20 yf, 4066 14 signals signals the nature of the malfunction (interruption of any tire, bus-39 closure of the information communication of cells 3 of the register to the common bus 38) and prohibits the passage of false information to an external device, realizing the control of the passage of signals on the communication buses of the separated register. A device for receiving information from spaced sensors with a computer can be connected via a standard interface of parallel input / output of information in which a buffer register is provided. At the same time, signals from input buses 14 "Sensor information 18," The spaced register is valid 17, "Open space break, 16" The short space register has to be asynchronously polled by the buffer data of the buffer register by the bus signal 20 "Read resolution. Further processing of the information read from the buffer register and the setting of the addresses at the inputs 22 "The address of the sensor is carried out in a computer programmatically. Invention Formula f, 1. An information device, mainly for rack storage, containing sensors installed at monitoring positions, an information register having 0 recording cells, each connected to an information input with a corresponding sensor, and associated with a control unit including a trigger and having an output for connecting with the indicator, characterized in that, in order to increase the reliability of operation, the information register additionally contains, according to the number of cells, the records placed together with the latter in the monitoring positions smoothing The rectifiers and pulse duration selection units and its recording cells are made in series-parallel action and are connected by synchronization inputs to the synchronization bus, common inputs to the common bus, and outputs each subsequent recording cell except the first to the follower 5 0 information input of the previous cells, the output of the first cell is connected to the information input of the control unit connected by the output to the sync bus, while the control unit additionally includes the power amplifier of the synchronization pulses, the generation units of the controlled duration of the synchronization pulses and the sensor polling , the first output of the first of the formation units through the power amplifier is connected to the synchronization input of the information register, and the second one is connected to the resolution inputs and is set to odnoe state of the second forming unit and is bonded to you 1564066 15 The “read resolution” of which is connected to the input by informational information and the output is with The first output of the trigger timing, the course of which is connected to the course of the control unit. in l che k u n in l and and and in a m in d n p and n ta x st d p in in a and in c p so A bus connection with the indicator, the pulse clock frequency generator is connected to the synchronization inputs of the first and second formation units, the informational inputs of the last of which are connected to the input buses. Sensor address, the power input of each information register cell is connected via the corresponding smoothing rectifier to the synchronization input cells and, through the corresponding pulse duration selection unit, to the recording control inputs. 2. The device according to claim., Characterized by that the block for selecting the duration of the synchronization pulses contains a time delay element and a diode connected by the cathode to the input of the delay element, and the anode to its output. 3. The device for and. 1, characterized in that the shaping unit of the controlled synchronization pulse duration contains the OR and NAND elements, an inverter and a counter, the inverse output of the higher bit of which is formed by the second output of the block and whose count input is connected to the output of the OR element; with the first input of the OR element and the input of the inverter, the output of which is connected to the first input of the NAND element, whose second input together with the second input of the first OR element is connected to the forward output of the high-order counter, the input It is connected to the input of the setup unit in the initial state, and the first output of the block is connected to the output of the NAND element. 4. The device according to claim 1, characterized by the hem, that the sensor survey generation unit contains an OR element, a counter and a digital comparator, while the second output of the block is connected to the inverted output of the high digit of the counter, the direct output of which is connected to the first input of the OR element, the second input is connected to the block enable input, the third to its synchronization input, and the output to the synchronization input of the counter, the installation input to which is connected to the installation input to the initial state of the block, and the low-order outputs to the first group log in Dov digital comparator, the second group of inputs of which is connected to the information inputs of the block, and the output - with the first output of the block. 5. The device according to claim 1, characterized in that the information register additionally sixteen five five 0 0 five 0 five 0 A test signal generation unit was introduced, the synchronization input of which is connected to the synchronization bus, a common input to the general information register bus, recording control inputs, serial information and information are combined, and the output is connected to the information input of the last cell, and to the control block - a packet generation unit sync pulses, a test signal test block and an AND element, with the second output of the synchronization pulses shaping control unit being connected to the installation input to the source co This unit of sync pulse shaping unit and with the first input of the element I connected to the output bus "read resolution", the second output of the sensor poll generation unit is connected to the resolution input of the sync package forming unit whose sync input is connected to the output of the pulse clock frequency generator, the second the output to the setup input to the initial state of the generation unit of the controlled duration of the synchronization pulses, and the first to the synchronization input of the test unit and test signals, the information input of which is connected to the information input of the control unit, and the first, second and third outputs are respectively connected to the output bus "Short circuit and" Open in the information register and "The information register is healthy, and the third output of the test signal test block is additionally connected to the second input of the element I. 6. The device according to claim 4, characterized in that the packet forming unit of sync pulses contains an OR element and a counter, the installation input in "About which is connected to the installation input of the initial state of the block, the direct high-order output - with the second output of the block and one of the inputs of the OR element, the second input of which is connected to the synchronization input of the block, the third to the input of the resolution of the block, and the output to the counting input of the counter and to the first output of the block. 7. The device according to claim 4, characterized in that the test signal test block contains AND, OR and EXCLUSIVE OR elements and shift register cells, the outputs of the latter of which are connected to the corresponding inputs of the OR element, the AND element and the EXCLUSIVE OR element, the outputs of which are connected respectively with the first, second and third outputs of the block, and the corresponding inputs of these cells are connected to the information synchronization input of the block. one ; uuuuuuL JLJUu jm jmrarnztumnro  tt 7 Hd1SPTGU  iJirmjiiTruTrt uuuuuubuu ittshnl and and and and and and 77 jmrarnztumnro t} It SPTGU ubuu ittshnl and and and and and / Fig.Z