SU1480096A1 - Signal dynamic range stabilizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve the accuracy of stabilization with single-channel and multi-channel input sources. The stabilization device contains multiplexer 1, el-2 with adjustable transmission coefficient, adders 3, 9 and 15, ADC 4, a selection block 5 for minimum and maximum signal levels, subtractors 6, 7, 16, 18 and 20, weight amplifier 8, multipliers 10 and 17, e-memory of permanent memory 11 and 19, digital comparator 12, memory of memory 13 and 21, decoder 14, D / A converter 22, and control pulse shaping unit 23. The device has two modes of operation: calibration mode and operating mode. With a multichannel input source, all sources are polled and the calibration cycle is repeated. In the operating mode, signals are not generated, but only the information is read from memory elements 13 and 21. The goal is achieved by using digital elements and introducing an amendment when determining the amount of displacement, due to the fact that adder 3 is turned on after electronic 2, as well as due to the simplicity of the stepwise approximation of the hyperbolic adjustment characteristic of unit 2. 1 Cp. F-crystals, 7 ill.

Description

00

1 f t

CD o

The invention relates to radio engineering, in particular, to automatic gain control systems, and can be used in calibrating channel gains.

The purpose of the invention is to improve the accuracy as well as increase the accuracy with a multichannel input source.

FIG. Figure 1 shows a structural electrical circuit of a device for stabilizing the dynamic range of a signal; in fig. 2 - structural electrical circuit of the control pulse shaping unit; in fig. 3- diagrams explaining its operation, where "is the signal at the input of clock pulses, b is the signal at the mode selection input, b is the signal at the start input, t, 3 and e are signals at the first, unit 23 of forming the control pulses contains counters 24 and a clock generator 26, the first three generators 27, the first and second pulse generators 28 and 29, the decoder 30, the second, third and fourth circuits 31, 32 and 33, the first, second and third elements 34, 35 and 36 , the inputs of the counter 24 and the second pulse generator 29 form the input of the clock pulses of the devices the first inputs of the first, second and t etego AND elements 34, 35 and 36 and the input of the counter 25 - entrance selection

press, counter reset input 25 - in

the second and the second outputs are the setup signal, h, and are the first and second minimum and maximum 25 start synchronization signals, the third element output is the maximum signal level (BVMMS), the third trigger 32, and the fourth one is the device synchronization signal; FIG. 4 shows a structural electrical circuit BVMMS; in fig. 5 - the diagramger 33 and the counter 24 are the first, second, third and fourth outputs of the control pulse shaping unit.

we who take his job where a

the signal at the control input, b is the signal at the installation input, c is the signal at the first synchronization input, t is the signal at the second synchronization input, 3, e are the signals at the outputs of the fourth and fifth And elements; in fig. 6 is a structural electrical circuit of a digital comparator; in fig. 7 are diagrams explaining its operation, where q is the signal at the installation input, 5 is the signal at the control input, C is the signal at the synchronization input, g is the signal at the input of the second inverter, d is the signal at the input of the fifth adder.

The device for stabilizing the dynamic range of the signal contains multiplexer 1, element 2 with adjustable transmission coefficient, first adder 3, analog-to-digital converter (ADC) 4, unit 5 for selecting the minimum and maximum signal levels of BBMMS, first subtractor 6, second subtractor 7, weight amplifier 8 , second adder 9, first multiplier 10, first permanent memory element 11, digital comparator 12, first memory element 13, decoder 14, third sum

torus 15, third subtractor 16, second multiplier 17, fourth subtractor 18, second constant memory element 19, fifth subtractor 20, second memory element 21, digital-analog converter (CDL) 22, control pulse generation unit 23.

The control pulse shaping unit 23 comprises counters 24 and 25, a clock generator 26, a first trigger 27, first and second pulse drivers 28 and 29, a decoder 30, a second, third and fourth triggers 31, 32 and 33, first, second and third elements And 34, 35 and 36, while the inputs of the counter 24 and the second pulse shaper 29 form the input clock of the device, the first inputs of the first, second and third elements 34, 35 and 36, and the input of the counter 25 is the input of the selector switch, the output of the third element And third trigger 32, fourth

bench press counter reset input 25 - input

start, the output of the third element And the third trigger 32, the fourth

5 start, the output of the third element And the third trigger 32, the fourth

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the trigger 33 and the counter 24 are the first, second, third and fourth outputs of the control pulse shaping unit.

In addition, the clock generator output is the output of the device synchronization signal, the outputs of the first and second elements 34 and 35 of the outputs of the first and second synchronization signals for BVMMS, respectively, the output of the second pulse generator 29 is the output of the device setting signal.

The selection block of the minimum and maximum signal levels BVMMS contains the first, second and third registers 37, 38 and 39, the first and second switches 40 and 41, the fourth adder 42, the fourth and fifth elements And 43 and 44 and the first inverter 45, the input of the first register 37 is the input BVMMS, the second inputs of the fourth and fifth elements And 43 and 44, the control input BVMMS, the control inputs of the second and third registers 38 and 29 - the installation input, the control input of the first register 37 - the first synchronization input, control inputs of switches - the second input is synchronous and the outputs of the second and third registers 38 and 39 are outputs of the signals of the maximum and minimum levels, respectively.

3-14

Digital comparator 12 comprises a sixth element AND 46, a third counter 47, a fixed memory block 48, a fifth adder 49 and a second inverter 50, while the subtracting input of the fifth adder 49 is the input of a digital comparator, the first input of the sixth element And 46 The control input, the reset input of the third counter 47 is the installation input, the second input of the sixth element 46 is the synchronization input of the digital comparator, and the output of the third counter 47 is the output of the digital comparator.

The device for stabilizing the dynamic range of the signal works as follows.

The control element 2 is in accordance with the following expression

V.

} 1 / V,

1 + / 3 (dZj - OJ

(one)

(2)

J

R; - control voltage of element 2 at j cycle; control voltage on j-1 clock;

the transmission coefficient of element 2 on the j cycle;

V.

K, D Z

J

Z

j "OCI ZJMHH / - 7

NOK.C (MMN j

the maximum and minimum values of the output signal at the jth cycle; coefficient taking into account random disturbances of the signal determining the inertia and noise immunity of the device 0 / & one .

The required displacement of the primeator is determined by the following

s. i / 2 {i-d An) zj-2s / f:},

where s

Zj & n

offset signal tick;

7 +7

Ј m about ks jt

n., - n.

PIM J

f

F

P (, -0

codes defining the transmission coefficients of element 55

Before the device starts operation, the following coefficients in binary code are added to the first constant memory element 11:

- f-N

V i W

de

W

N

 X

1, ..., N;

-a valid range of variation of the normalized output signal;

-Required level of the output normalized signal;

-the number of discrete coefficients determined by the expression N 1 + + ent (ln D / ln W);

VXMWH dynamic range of the signal;

MNN and H / mshks - the minimum and maximum possible levels of the input signal,

t0e. the first memory element 11 stores the number V, the inverse of the set gain factor Kj.

The following values are added to the second constant memory element 19:

thirty

d. W

(four)

where i is N, N.

In the block 48 of the fixed memory of the digital comparator 12, the threshold values of the output control signal U are entered, XWUH where I 0, N.

W

; -N

(five)

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five

The device has two modes of operation: calibration mode and operating mode

In the calibration mode, a single-level signal is input to the device mode selection input. With the appearance of the signal at the device start-up input, the counters 24 and 25 of the forming unit 22 are set to the zero state, and the BVMMS 5 register is set to one. At the input of the element with an adjustable transmission coefficient, one of the input signals is received

The input signal at the j-th cycle through the element 2, the first adder 3 and the ADC 4 is fed to the input BVMMS 5. In this block as a result of the comparison operation performed on the fourth adder 42, the values of ZMU4 and Z Maiic are fixed at registers 39 and 38 respectively

At the outputs of the first subtractor 6 and the third adder 14, the results A Z j and 2 Z appear. Accordingly,

The difference signal & Z is fed to the second subtractor 7, at the input of which a signal is generated, sweep errors. This signal is fed through the weight amplifier 8 with a gain factor to the first adder 9 and then to the first multiplier 10, where it is converted to the value of R at V-., 1 + p (AZ / -. 1,).

The index j indicates the number of the calibration step of the device and indicates that the channel state at this jth calibration stage in general is different from the state (offset value, transmission coefficient) at the previous (j - 1) step „Calculation result Rj v H tl + p (iZ - 1) J enters the digital comparator 12, where a new control code is formed determining the transfer coefficient at this jth calibration stage. The process of determining the new code p. comes down to finding one that satisfies the condition

 R

i U

(6)

where i 1, N.

The number of items found determines the new channel state after calibration. The timing diagram in FIG. 6 explains the operation of the digital comparator 12

At the same time, the sum signal Zj from the output of the third adder 15. goes to the third subtractor 16, to the input of the subtracted which receives the signal S h, where S, is the mixture calculated at the previous j-1 clock from the output of the second memory element 21. The third subtractor 16 forms the difference (Z max + Z MUH) - - 2S (j-uL

Code difference dp

 n, - luchenna in the fifth subtracter

P

J-, PO20, goes to the second memory element 19, where the value of the correction factor dCfln) is formed, which takes into account the changed transmission coefficient of element 2, and the product Y d (An) Z KC + Z MWH- 28.3 is formed in the second multiplier 17 - readable in the fourth subtractor 19, where the final required signal offset is determined at this stage.

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Since the code of the required transmission coefficient and the required offset are formed, a signal is generated at the first output of the control pulse shaping unit and the gain code value is stored in the first memory element 11, and the offset is stored in the second memory element 19 the decoder 14, where the magnitude of the gain factor in the binary code is generated, And the offset value is converted to the digital signaling module 22 into an analog value, and since the VAP 22 reference voltage is reduced by two ie, the minimum output CHI- Nala value is close to zero

With a multichannel input source, with the arrival of the next pulse at the input of the device’s clock pulses, the state of the first counter 24 5 of the shaping unit 22 is changed by one, which leads to the input of the element 2 with the control gain of another input source, as well as the signal change at the address inputs of memory blocks 13 and 21. The cycle of the calibration process is repeated. After interrogating all sources of signal, the calibration process ends

In the operating mode, a zero-level signal is input to the mode selection input, no signals are generated at the first, second and third outputs of the formation unit 23, but information is read from the first and second memory blocks 13 and 21.

Thus, due to the use of digital elements, the introduction of a correction when determining the amount of bias, due to the fact that the first adder is connected after the element with an adjustable coefficient, the simplicity of the stepwise approximation of the hyperbolic adjustment characteristic of the element with a controlled transmission coefficient in the device achieves high accuracy.

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Claims (1)

1. A device for stabilizing the dynamic range of a signal, containing a series-connected element with an adjustable coefficient the transfer and the first adder, the output of which is the output of the device, the block separating the minimum and maximum signal levels, the first subtractor connected in series, the inputs of which are decremented and subtracted are connected respectively to the outputs of the maximum and minimum signals of the block of the minimum and maximum signal levels, the second subtractor The input of which is subtracted is the input of a signal of a single level, the weight amplifier, the second adder, the other input of which is connected to the input of a signal of units the first multiplier and the first memory element, the output of which is connected to the control input of the element with an adjustable transmission coefficient, are connected in series to a third adder, the inputs of which are connected to the outputs of the minimum and maximum levels of the signal, and a third subtractor connected in series to the fourth subtractor the input of which is decremented is connected to the input of a signal of a single level, and the second memory element, the output of which is connected to the input of a third subtracted subtractor and also a shaping unit, the first input of which is the input of the device clock, the first output is connected to the recording resolution inputs of the first and second memory elements, characterized in that, in order to improve the accuracy, an analog-to-digital converter is inserted into it connected between the output of the first adder and the input of the block separating the minimum and maximum signal levels, the second multiplier connected between the output of the third and the input of the subtracted fourth subtractors, pre 10 15 480096-8 a generator connected between the output of the second memory element and another input of the first adder, the first constant memory element connected between the output of the first memory element and the second input of the first multiplier, the fifth subtractor and the second constant memory element connected in series, the output of which is connected to another input of the second multiplier, as well as the decoder and digital comparator, while the first multiplier is connected to the first memory element through a digital comparator, which controls the input of which The second output of the control signal shaping unit, the output of the first memory element is connected to the control input of the element with adjustable transmission coefficient through the decoder, the third output of the control pulse formation unit is connected to the control input 25 of the minimum and maximum signal level selection unit, the inputs the subtracted and decremented fifth subtractor are connected respectively to the outputs of the first memory element and the digital comparator, and the second and third inputs of the control impulse forming unit The pulses are the start and select mode inputs respectively. 20 thirty 2 o The device according to claim 2, in order to increase accuracy with a multichannel input source, a multiplexer is inserted into it, the inputs of which are device inputs, the output is connected to the input of an element with a controlled gain, the fourth output of the control signal generating unit connected to the control input of the multiplexer and the address inputs of the first and second memory elements. To an / south digital converter one l Hoj v w  f - p p p p p p P P P. ll # 7 Zy NJ / Y7 % K-J LjOrn - I 41 V3 Record W Record Fia.U pn P. t t t t t Phage.5 Phase.6 7