SU1478147A1 - Multiport network parameter meter - Google Patents

Abstract

The invention serves to speed up the process of measuring parameters of multipoles by automating it. The device comprises a generator, a voltage divider, two drivers, a key, a control unit, a unit of switching switches. Introduction of input and output switches, a clock pulse generator, two counters, two registers, four decoders, four indicators, two OR elements, a phase meter, a key and an inverter provide automatic switching and indication of numbers of input and output channels of a multipole. The description provides an example of the implementation of the control unit. 1 hp f-ly, 4 ill.

Description

one

The invention relates to a measurement technique and is intended to measure phase shifts and voltages of signals passing through a multi-terminal.

The aim of the invention is to accelerate the measurement process by automating it,

Figure 1 shows a block diagram of a device for measuring parameters of multipoles; figure 2-3 - timing diagrams of input-output information when working with computer DZ-28; figure 4 is a variant of the combinational circuit.

The device contains a signal generator 1, which is connected via a voltage divider 2 to the input switch 3, the outputs connected to the input terminals of the quadripole under study, the input channel of the phase meter 4 is connected to the output of the divider. 2

voltage, and the second input of the phase meter 4 and the input of the voltmeter 5 are connected to the output of the output switch 6, the inputs of which are connected to the output terminals of the quadrupole, a generator of 7 clock pulses through a block of 8 switching switches connected to counters 9 and 10 channel numbers, to the outputs of which through decoders 11 and 12 are connected indicators of channel numbers 13 and 14, simultaneously the outputs of the decoders 11 and 12, respectively, are connected to the control inputs of input 3 and output 6 of the switch, information outputs of phase I 4 and volt Tra 5, respectively, are connected to the buffer registers 15 and 16, the recording entries of which are respectively connected to the outputs of the logical elements OR 17 and 18, the first inputs of which are through the sequence J

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Keys 1 9 and 20 connected with them are connected to control outputs of phase meter 4 and voltmeter 5, outputs of buffer registers 15 and 16 are connected via decoders 21 and 22 to indicators 23 and 24, while outputs of buffer registers 15 and 16 are connected to information inputs of a multiplexer 25, the control inputs of which through the decoder 26, the information output counter 27 to the output. three-input element And 28, connected in turn by the first input to the output of the decoder 29, the second to the output of the Transfer trigger 30, the third to the output of the computer VV, the inputs of the trigger 30 are connected to the outputs of the decoder 31, the inputs of which are connected to the outputs of the SIM and EV computer, and j with the output of the decoder 29, the input of which is connected to the computer bus Ex. the input of the imaging unit 32 is connected to the computer output Ib, and the output through the imaging unit 33 is connected to the computer output CIP, the computer output bus is connected to the decoder 34 and simultaneously with the information inputs of counters 9 and 10, the output of the decoder 34 through a two-input element 35, the second input which is connected to the output of the decoder 29, the trigger 36, the combinational 1 circuit 37, the buffer register 38, the recording input of which is connected to the output of the decoder 29, and the control input of the neutral state is connected to the output of the trigger 30 and the second input of the trigger 36, information the output of register 38 is connected to the bus of the computer Input, at the same time the data bus through the imaging unit 39 is connected to the output of the multiplexer 25, the control input of the imaging unit 39 is connected to the output Transfer trigger 30, the inputs of counters 9 and 10 through the corresponding outputs of the decoder 40 with the output of input counter 11 connected by the input to the output of the three-input element I 42, the inputs of which are connected to the output of the decoder 29, the output receiving trigger 30 and the output of the EB computer, the outputs of counters 9 and 10 are connected to the block 8 of switching switches, the signal output to Afterwards, the shaper 43 and 44 are costly connected to the second inputs of the two-input elements OR 17 and 18, the first inputs of which are connected respectively to the outputs of the keys 19 and 20, the first inputs of the latter respectively are connected to the control outputs of the phase meter 4 and a voltmeter 5, and the second They are connected to the output of the inverter 45 connected to the output of the transducer 4-3 of the transient process.

Items 25-45 constitute a control unit.

The operation of the device in conjunction with a computer (block 8 in position 4) is divided into two stages. The first stage is receiving information from the computer about the channel numbers of the studied multipole. The second stage is the transfer of information about the parameters of the studied channel of a multipole. In this case, the exchange of information between the computer and the measuring device is carried out by portions of bytes,

Consider the first stage of the device - reception. On the tire of the computer Ex. In accordance with the program entered into the computer (Fig. 2a, b), a code is established corresponding to the mode of interaction of the DZ-28 computer with the peripheral device. This code is decrypted by the control decoder 29 and fed to one of the inputs of the decoder 31. At the output of the SIM computer, a sync pulse of SIM is simultaneously generated & at the output Bb the signal is set to O, The presence of the indicated combination at the inputs of the decoder 31 sets the trigger 30 for determining the mode to the Receive state. Such a state of the trigger 30 sets the bus driver 39 to the neutral state and removes the neutral state of the register 38. Then, on the bus, Ex. a command is generated that corresponds to the selection of a peripheral device group, and on the output bus, the peripheral device group address code is set, which corresponds to the reception of the first byte of information from the computer. The address code of the peripheral device is decrypted by the decoder 34 and when a signal is sent on the Busbar, through element 35 switches the trigger 36, which enables the selection of the group of the peripheral device and in turn triggers the combinator circuit 37, the output code of which is written to the register 38 and goes to the computer bus Enter. In the second byte of information from the computer on the bus Vyv comes the code

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addresses of the input channel, and in the third - the code of the address of the output channel of the studied multipole. The bytes of the received information are counted by the D input counter by signals from the output of the And 42 element, the decoder 40 alternately switches the counters 9 and 10 of the input and output channels to the mode of setting the codes received from the computer via the bus Vyv. Then the computer goes into the standby mode of supply from the measuring device of the sync pulse CIP, which is a confirmation signal of the measuring device about receiving and processing information from the computer. A CIP pulse is generated by shaper 33 according to a signal at pin BB after its delay at a time of about 10.0 µs by shaper 32. A CIP pulse generated in this way is fed to a CIP computer pin.

The second stage of the device operation is the transmission of information about the measured parameters of a single channel of a multipole to a computer for subsequent processing. Receipt of the signal by the CIP of the computer transfers the signal BB to the level corresponding to 1 according to the arising input combination of signals of the decoder. 31 sets the mode trigger 30 to the Information transfer state from the measuring device and the computer. In the Transfer mode, the information on the value of the phase shift of the signal and the voltage in the channel of the multi-channel being recorded in the buffer registers 15 and 16 is read byte-by-multiplexer 25. The number of bytes is determined by the information output counter 27 and the decoder 26, controlled by the output signal of the element And 28. The output signal of multiplexer 25 is processed by bus driver 39 to provide the level and polarity of signals necessary for a computer. The control of the neutral state of the tire driver 39 is performed by the mode determination trigger 30.

Data output from the device DZ-28

accompanied by a SCM signal. The formation of the SIM is based on the D-flip-flop, which is set to zero state by the micro-order of data output. At the end of the cycle of interaction of the DZ-28 with the HQ signal Bb, the trigger returns to its original position.

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The SIM signal enters the I / O interface line. The formation of the SIM is blocked by the blocking signal (), which corresponds to the zero state of the Secret Control (work with the built-in keyboard).

Synchronization of the interaction of the DZ-28 in the exchange of information with the peripheral node (PU) keyboard with the help of the signal of the control bus BB

If DZ-28 is in a state of waiting for a response (SIP signal) from the PU or keyboard.

After the CIP signal arrives (this means that the DZ-28 received the information and started processing it or proceeded to prepare the transmission of new information), the BB signal is set to one state. The BB signal can be set to any state using micro orders.

The order of operation of the I / O interface in the output of information on the bus The output is as follows:

a) on the bus the control is set by the output command;

b) on the Vyv bus, a byte of information is set;

c) DZ-28 sets the SIM signal to the zero state;

d) DZ-28 sets the VV signal to the zero state;

e) DZ-28 goes into standby mode for the CIP, with which the PU signals that the received information and the PU indicates that the received information and the PU is ready to receive the next byte of information on the bus

e) upon the arrival of a CIP signal or at the end of its cooling time, for some commands it sets the BB and SIM signals to one state;

g) in response to the installation of the signal, the IP should remove the CIP signal.

Timing diagrams of information output via the Vyv bus are shown in FIG.

The order of operation of the I / O interface when entering information into the DZ-28 via the bus. Input is as follows:

a) a combination is set on the bus of the GPR, set by the input command;

b) DZ-28 sets the VV signal to the zero state;

c) D3g: 28 goes into standby mode CIP;

d) PU is placed on the bus Entering data bytes and sets the CIP signal

to zero state;

d) on arrival of the CIP signal or

at the end of the waiting time for some commands, DZ-28 receives the data of the bus Input and sets the signal Ib.

in response to the installation of the signal, the PU should remove the CIP signal.

Timing diagrams for information input from the bus. Input is shown in FIG.

On a DZ-28 type computer, the fact that a single command is completed and the computer's resolution to go to the next program command is recorded with code combination 0514, which in binary-decimal code will be 1010, 0111, respectively. The combination scheme that implements this combination is shown in 4.

The technical and economic advantages of the proposed technical solution in comparison with the known one are automatic switching and indication of the numbers of input and output channels of a multipole.

As a control computer, a DZ-28 type machine is used, which provides a significant gain in measurement time, providing a better and more comprehensive estimate of the parameters of the studied multipole.

Claims (2)

Invention Formula 1, A device for measuring parameters of multipoles, comprising a generator with a voltage divider, two series-connected shapers, a first switch, a control unit, a switching switch unit, a voltmeter, which in order to speed up the measurement process by automating it, input and output switches, a clock pulse generator, two counters, two registers, four decoders, outputs connected to four indicators, two OR elements, a phase meter, the second cell h and an inverter, wherein the output of the voltage divider is connected to the reference input of the phase meter and the information input of the input switch, the control inputs of which are connected to the outputs of the first decoder, the outputs of the second decoder connect the output switch, the information output of which is connected to the second input of the phase meter and the input of the voltmeter, the information outputs of the phase meter and the voltmeter, respectively, are connected via the first and second registers to the inputs of the third and fourth decoders and respectively About the first and second inputs of the control unit, pulse outputs of the phase meter and voltmeter, respectively, through the first and second keys and through the first and second elements OR are connected to the control inputs of the first and second registers, the output of the first driver through the inverter is connected to the second inputs of the first and second keys , and the output of the second shaper is connected to the second inputs of the first and second elements OR, the clock pulse generator is connected to the first input of the block of switching switches, the first and second outputs of the cat respectively, are connected to the counting inputs of the first and second counters, the overflow outputs of which are connected respectively to the second and third inputs of the switching switches block, the third output of which is connected to the input of the first driver, the inputs of the input switch are connected to the input terminals of the studied multipole, the inputs of the output switch are connected to the output terminals of the studied multipole, the first and second decoders, respectively, are connected to the outputs of the first and second meters The first and second outputs of the control unit are connected to the second inputs. The first and second counters are recorded respectively. The third output of the control unit is the sync output of the device CIP, the inputs of IB SIM and Control of the device are respectively the fourth, fifth and sixth inputs of the control unit, the fourth output which is the Input input, and the fifth output is connected to the information inputs of the first and second counters. 2. The device according to claim 1, about tl and - the fact that the control unit It contains the first element I, the output counter, the first decoder, the multiplexer, and the bus driver, the output of which is connected to the fourth output of the control unit. Input, the output of the second element And, through the input counter, is connected to the second decoder, the outputs of which are the first and the second output of the control unit, the fifth input of which is connected to the first input of the third decoder, the fourth input is connected to the second input of the third decoder, and also through the first and second driver to the third output ohm SIP control unit, the sixth input of which Upr is connected to the input of the fourth decoder, the first output of which is connected to the third input of the third decoder and the first inputs of the first and second elements And, the three outputs of the third decoder are connected to the corresponding inputs of the first trigger, the first output of the coder Q 5 five 0 Secondly, the reception is connected to the first input of the second trigger, the first input of the register and the second input of the second element AND, the third inputs of the elements AND are connected to the fourth input VB of the control unit, the second output of the first trigger transfer is connected to the second input of the first element AND and the control input of the bus driver, the third input of the control unit Out through the sequentially connected fifth decoder, the third element I, the second trigger, the combinator circuit and the register is connected to the fourth output of the control unit The input and the second output of the fourth decoder are connected to the second input of the third element AND and the second input of the register, the first and second inputs of the control unit are connected to the corresponding inputs of the multiplexer, and the third input of the control unit is connected to the fifth output of the control unit. SII FIG. Phage. 2 } - } - OS fu "