SU1322229A1 - Device for controlling velocity of electric drive - Google Patents

Abstract

The invention relates to automation and can be used in precision devices for adjusting the speed of the electric drive. The purpose of the invention is to increase the speed and accuracy of the device for adjusting the speed of the electric drive with varying external disturbances. The goal is achieved by introducing into the device an additional control loop, consisting of a time interval converter - code 15, adder code 16, speed reference block 17, which allows to increase the quality factor of the device. The additional circuit allows forming the control pulse width signal both by changing the frequency and phase of the signal fj, and by changing the frequency and phase of the reference signal fj simultaneously. The device contains a pulse generator 1, controlled frequency dividers 2, 3 and 4, a logical block of comparison 5, a power converter 6, an executive motor 7, a speed sensor 8, a pulse driver 9, 14, an element OR 10, a delay element 11, a trigger 12, pulse expansion unit 13. 3 sludge. i (L SLE to to y with fe./

Description

t

The invention relates to controlled systems of automatic control of the speed of an electric drive, built on the basis of closing the system according to the phase difference of the compared frequency signals, and can be used in precision devices to which high accuracy requirements are imposed on controlling and stabilizing the frequency and phase of rotation of the output shaft.

20

25

thirty

The purpose of the invention is to increase the speed and accuracy of a device for controlling the speed of an electric drive with varying external disturbing influences in a wide range.

FIG. 1 is a block diagram of the device for controlling the speed of the electric drive} in FIG. 2 — graph-operations and timing diagrams explaining the operation of the logical unit of comparison; in fig. 3 is a block diagram of a device for controlling the speed of an electric drive (a is a diagram of a known speed controller 6 — a diagram reflecting the logical nature of the operation of the device, 6 reflecting the dynamics of the system).

The device for controlling the speed of the electric drive contains a pulse generator 1, frequency dividers, a logical comparison unit 5, a power converter 6, an executive motor 7, a speed sensor 8, the first pulse shaper 9 pulses, an ILR1 10 element, a delay element 11, a trigger 12, a pulse expansion block 13 , the second shaper 14 pulses, the converter 15 time interval - the code, the adder 16 codes and block 17 task speed.

The operation of the speed control device is based on the principles of pulsed

Discrete controlled actuators whose main circuit is closed by the phase difference of the compared frequency signals of the reference frequency f and the frequency fp from the speed sensor.

The device works as follows.

The speed reference block 17 is manual or automatic.

tota dividing ratio

N:

setting the output code q, my adder 16 codes.

Controllable dividers 2–4 frequencies can be implemented in the traditional way, in which a CT2 reversible counter is feedback-fed from output O to input C.

Reference frequency f

If- fp frequency of the quartz oscillator

one

pulses fed to the first input of the logical unit 5 comparison.

The signal from the frequency sensor 8 speed with the number of pulses Z per revolution of the shaft of the engine 7 using the first driver 9 pulses and the second divider 3 frequencies with a division factor tota

NP converted to 40 hours.

R

j is proportional to the speed of rotation of the front shaft of the actuator motor 7, which is fed to the inputs of the delay element 11 and the correction device (Fig. 1, dashed frame). A correction device containing the third divider 4 frequencies, the element OR 10, the trigger 12, the pulse expansion unit 13 and the second driver 14 of the pulses, converts the frequency-static systems to the electron 45 into a new sequence

pulses fp, out of phase with respect to fp, which is fed to the second input of the logic unit 5 of the comparison. Frequency sensor 8 speed 8 50 is designed to generate a frequency signal strictly proportional to the speed of rotation of the motor shaft 7. Shaper 9 pulses amplifies the periodic signal from the sensor

A device issuing a n-bit dual speed converts it into a frequency code in the form of a plectrical signal and usually consists of an operating signal.

high and low levels.

In the simplest case, it is a pushbutton set, with automatic 2

The com- mand code is a program-master device or a computer.

The speed setting unit 17 outputs a code q corresponding to the required speed value to the control inputs of the controlled dividers 3 and A of the frequency and to the input of the adder 16 codes. In accordance with the given code, in the second 3 and third 4 frequency dividers, the required values of the division factors Np and N are set, respectively. In the first divider 2 hours

tota dividing ratio

N:

setting the output code q, my adder 16 codes.

Controllable dividers 2–4 frequencies can be implemented in the traditional way, in which a CT2 reversible counter is feedback-fed from output O to input C.

five

0

Reference frequency f

If- fp frequency of the quartz oscillator

one

pulses fed to the first input of the logical unit 5 comparison.

The signal from the frequency sensor 8 speed with the number of pulses Z per revolution of the shaft of the engine 7 using the first driver 9 pulses and the second divider 3 frequencies with a division factor tota

NP is converted to an hour amplifier and comparator.

The corrective device, as in the continuous systems, is intended

to ensure stable operation of the device to control the speed and give it the desired dynamic properties.

Receiving a signal is reduced to two operations: finding the deviation of the period of frequency fp from the reference period of frequency f and expanding the received deviation (pulse) to the required number of ratios, determined from the condition of system stability.

The pulse expansion carried out by the pulse expansion unit 13 can be carried out in a known manner. Obtaining a stable time interval T is produced by drawing from periods of frequency fp periods of frequency f produced by the third frequency divider 4, the division factor of which Nj relative to the division factor N of the first frequency divider 2 is determined by the ratio

N 2kp - 1

N,

2k

where kp is the expansion coefficient of the pulse expansion unit 13.

The regulation of the time interval T in the whole range of operating speeds of the device occurs synchronously with the change of the reference frequency fj in accordance with the signals from the speed setting unit 17 by changing the division factor N of the divider 4 frequency. The comparator and the pulse separation unit are combined into a logical comparison unit 5, which makes a comparison of the phase of the frequency pulses f and fp arriving at its inputs, and the results of this comparison form a pulse-width signal (Fig. 26), which is fed to the input of the power converter 6 .

FIG. 2a presents a rational algorithm for the operation of a proportional type block 5 in the form of a directional graph, which ensures the normal operation of the device at all possible combinations of frequencies at its inputs during acceleration, deceleration and in steady-state synchronous speeds, when

fi g f fp - fj - f ,.

For example, when starting the engine there is fj and there is no fp. Block 5 goes to bj, accelerates, f p rarely appears, i.e. fp; f, there is a short transition from b - b, - «b. The engine accelerates, coming under O

50

five

oh with q

50

five

the frame of the fp pulse, with the goat block 5 goes from b to b,. Established under fi, when f j, fj transitions take place b - bj - b, etc., i.e. acceleration, braking. When the phase mismatch is larger than the period f, block 5 occupies two extreme states bj or b, in which the signal from stalling is blocked.

The power Converter 6 produces amplification of the pulse-width signal coming from the output of block 5, and supplies it to the main winding of the engine 7. The power Converter 6 operates in key mode.

From the time diagrams illustrating the operation of the device (Fig. 2b), it follows that the relative duration of the pulse-width signal v increases with an increase in the load moment MC on the shaft of the executive engine. Moreover, the change occurs only due to a change in the frequency and phase of the signal fp or the same due to the errors in stabilizing the speed and phase of rotation of the shaft of the executive engine. The magnitude of these errors is mainly determined by the gain factor D or the good quality of the system. A similar picture of the formation of 2f occurs in the case of a change in the control action, i.e. changing the speed setting is detectable f.

An additional control loop consisting of a speed setting block 17, an adder 16 codes and a time interval converter 15 — the code allows generating a control pulse width f signal both by changing the frequency and phase of the signal fр and by changing the frequency and phase reference signal fj simultaneously. Such control of the regulator increases the drive speed and significantly reduces the errors in stabilizing the speed and phase of rotation of the engine.

The time diagrams illustrating the formation of a latitudinal and pulsed signal y in the device are shown in FIG. 2c for the consistency of gtri coefficient of error K 2 1.

the physical nature and implementation of the additional circuit is as follows.

Pulse width signal arriving at the input of the transducer 1) atovatel 1

time interval - the code from the pulse extension unit T, iT Tr - TC - time interval formed at the output of the trigger 12,

TK periods of frequency fp and often- 5

you

to

derived from the output of the third divider 4 frequency. In the steady state mode of the device, when the frequencies

f; f.

fp

temporal

the interval Tn and LTDdCr is selected from the condition of obtaining a symmetric characteristic of the regulator by an equal half the frequency period

Since in this mode LT T, - TC.

those.

-Ytr then

That t

In the case when f p f and ip zj, then there is a deviation in speed, the magnitude of which is proportional to - p

T., can be written

AND

on the time interval (W

Then the flux for the pulse-width signal in the form of T J, Tc / 2 K

From the obtained expression it follows that the pulse-pulsed signal T arriving at the input of the converter 15 time interval — the code from the pulse expansion unit 13, contains information about the speed deviation and can change its value in the linear zone of the controller within O,.

The time interval converter 15 — the code is executed according to the traditional scheme and in the simplest case contains a frequency generator f, the AND element, a pulse counter, and a register.

In this converter, the duration of the pulse-width signal T ,, is converted into an n-bit binary code whose numerical value, q

 . ,

where K, p is the coefficient of preE

educator is chosen such that in steady state at T-T the value of the q code is exactly equal to the q code provided by the speed setting unit 17. In particular, when using for filling the frequency of the generator 1 pulses f f gdr 2- Obtained in the converter 15

„And q receives 16 codes, which is the difference df q e

on the inputs of the sum of them computed

Q gatel, speed sensor, the first pulse shaper connected to the input of the second frequency divider, the output of which is connected to the reset input of the third frequency divider, with the first

the algebraic sum q 4, 51 where k 1,2, ..., p is the coefficient of the sum of the input of the OR element and through the element of the error world. Delay with the reset input of the trigger,

The code of the output connected in this way is connected through the serially connected pulse expansion unit and the second driver is fed to the information inputs.

the first divider 2 frequency, changing

,

1322229

13

Where

its division factor is N and therefore the reference

P

f af

i, - e

Obviously, in the steady state mode of the device, when the error is

speed is Che - PE

zero have a place

and N,

h;

N ,, f, f, - fp. The reference frequency f, changes its value in proportion to the detected speed deviation, and

15

frequency fJ in the direction of frequency f about, i.e. if fp f

R

always happens the reverse of the change of ft then

f f5, and vice versa.

The adder codes can be straight

35

Nene according to the traditional scheme using any type of chip SM.

The introduction of additional elements and connections (Fig. 36, c) increases the goodness of the system of the device by (1 + + CrrCu) times, without increasing the order of its astatism.

In this case, the stability of the system is ensured by

25 by selecting the magnitude of the expansion factor Kp of the correction device.

Improving the accuracy of the electric drive of the device is 30 not only due to an increase in the system Q-factor by (1 Kj), but mainly due to the phase shift of the reference frequency and in transient modes, which is involved in the formation of the control signal j the more effective the higher the K value. .

Claims (1)

Invention Formula 40 Device for controlling the speed of an electric drive, comprising a pulse generator, first, second and third frequency dividers, an OR element, a delay element, a trigger, a pulse width unit, the first and second pulse formers, a comparison logic unit, the output of which through a serially connected power converter, an executive gatel, speed sensor, first pulse shaper connected to the input of the second frequency divider, the output of which is connected to the reset input of the third frequency divider, with the first  the input of the OR element and, through the delay element, to the trigger reset input, 71 pulses to the second input of the comparison logic unit, the first input of which is connected to the output of the first frequency divider connected by the input to the output of the pulse generator and to the input of the third frequency divider whose output is connected to the second input of the OR element connected by the output to the trigger input, characterized in that , in order to improve the speed and accuracy of the device for speed control / OZH-SHE  fy- 222298 the drive, a speed reference block, a code adder and a time interval transducer are entered — the code whose input is connected to output 5 of the pulse expansion unit, and the output to the first input of the code adder, the second input of which is connected to the output of the speed reference block and to the control the inputs of the second and third frequency dividers, and the control input of the first frequency divider is connected to the output of the code adder. fo .I Si Me FIG. 2 but L Editor 0. Head Compiled by E.Vlasov Tehred L. Oliynyk Proofreader G. Reshetnik Order 2863/43 Circulation 863 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5  . "..." ... to "...." .. D Production and printing company, Uzhgorod, Projecto st., 4 Fig 3