SU1399869A1 - Device for controlling solid-state frequency converter - Google Patents

Abstract

This invention relates to a converter technique and can be used in frequency converters. The purpose of the invention is to improve the reliability of frequency converters when operating at variable load. By introducing a mean value filter, a D-flip-flop with setup inputs, a sample-hold device, and a second comparator, the frequency of the inverter is controlled as a function of the duty cycle of the inverter output current pulses. 1 hp f-ly, 1 ill. i (L

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The invention relates to electrical engineering, namely to converter technology, and may find application in high-frequency electrical technology installations.

The purpose of the invention is to increase reliability when the converter operates on a load with variable parameters.

FIG. 1 is a functional diagram of the device in FIG. 2 shows the inverter conductive sensor circuit; in fig. 3 - time diagrams of voltages, which are used for the operation of the device.

A device for controlling a semiconductor frequency converter, made on a single cell resonant inverter 1 with counter-paralysis of a tyrstone 2 and diode 3, contains an inverter conductive sensor 4 included in the power circuit of the inverter 1, which sets the generator 5, whose output is connected with the control electrode of the thyristor 2, the source 6 of the reference voltage, the output of which is connected to the first input of the comparator 7, the source 8 of the control voltage, the output of which is connected to the input of the integrator 9.

The device is additionally equipped with a low-frequency filter 10, a D-flip-flop 11, a sampling-storage device 12 and a second comparator 13, and the output of the sensor of the conducting state of the inverter 1 through the low-pass filter 10 is connected to the second input of the first comparator 7, the output of which is connected to clock input D-trigger 11, the output of the integrator 9 is connected to the information input of the device 12 sampling-storage and to the second input of the second comparator 13, the output of the device 12 sampling-storage connected to the input of the master oscillator 5 and to the first input at the second comparator 13, the output of which is connected to the setup input of the D-flip-flop 11, the D-input of which is connected to the common bus, and the inverse output is connected to the control input of the sample-storage device.

The inverter conductive state sensor contains two current transformers 14 and 15, connected respectively to the thyristor circuit 2 and reverse diode 3 of the resonant inverter 1, and kc is the secondary circuit of the transistor

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current format 14 is connected to the beginning of the current transformer 15 winding to a common point, the second winding leads of current transformers 14 and 15 through diodes 16 and 17 are connected to the first output of resistor 18, the second output of which is connected to the cathode of the zener diode 19 and the first voltage of the capacitor 20, the zener diode anode 19 and the second terminal of the capacitor 20 are connected to the common connection point of the secondary windings, in parallel with which the resistors 21 and 22 are connected.

The device works as follows.

The control pulses U, (FIG. 3) from the output of the master oscillator 5 are fed to the control electrode of the thyristor 2. Sensor 4 produces pulses Uj, the duration of which is equal to the total duration of the currents of the thyristor and diode of inverter 1. The low frequency filter 10 produces voltage Uj, proportional to the duty cycle Uj, which is compared on the first comparator 7 with the reference voltage UQP produced by the source 6 of the reference voltage. As long as Uj with U, j, the voltage at the output of the comparator 7 is zero. The voltage at the inverting output of the D-flip-flop 11, previously set to one, is also zero. Therefore, the sample-storage device 12, to the control input of which the inverting output of the trigger 11 is connected, operates in the mode of transmitting the signal from the information input to the output. Consequently, when the pause duration is within acceptable limits, the source 8 of the control voltage through the integrator 9 and the sample-storage device 12 affects the frequency of the driving oscillator 5, and it is possible to further increase the frequency of the inverter 1 or increase its equivalent resistance.

As soon as the voltage at the output of the low-frequency filter 10 exceeds the reference Uen (which contributes to the mode when the pause time between pulses Uj decreases to a critical value, due to an increase in frequency or due to a change in load parameters), the output level of the comparator 7 is set to

tension A difference of 0-1 at the input of the CHHxpoHnaaiUTO D-flip-flop 11 causes the latter to switch to the zero state, since the D-input is grounded. The voltage at the control input of the sampling-storage device 12 becomes equal to 1, which causes the voltage value that was present at its information input at the moment of switching to the storage mode to be saved at its output. Consequently, the input voltage of the master oscillator 5 remains constant, corresponding to the critical pause value, and the inverter continues to operate at a fixed frequency, at which the pause duration does not decrease below the critical value, despite a further increase in the control voltage Ug of the source 8 voltage management wives. In the time diagrams of FIG. 3, this mode is shown to the right of the moment of switching the PR of which 1) 4 1, and Ug YY const, since the sampling-storage device operates in the storage mode.

Now suppose that the voltage Ug decreases and at the time trtgpj (Fig. 3) reaches the value Uj. This causes the comparator 13, the output of which is connected to the setup input of the trigger 11, to be switched to state 1, and the trigger 11 is reset. The voltage at its inverting output becomes zero, and the sampling-storage device 12 goes into sampling mode, i.e. The control voltage source 8 again begins to influence the frequency of the master oscillator 5 through the integrator 9.

The purpose of the integrator 9 is to smooth out too 6 STRENGTH voltage variations of source 8, which may lead to an abrupt increase in frequency that the low-frequency filter 10 cannot track. To do this, it is sufficient to exceed the order of the time of the integrator 9 over the time of the low-frequency filter 10. In this case, the voltage of the filter 10 with sufficient accuracy at any time will correspond to the duty cycle of the sensor A.

Thus, the invention allows to increase the reliability of

frequency generator, since the output frequency is controlled under the condition of monitoring the pause time, which limits the amplitude of the direct voltage applied to the thyristor in its non-conducting state.

Claims (1)

1. A device for controlling a semiconductor frequency converter made on a single cell resonant inverter with a counter-parallel switching of the thyristor and a diode, containing a master oscillator, the output of which is connected to the control electrode of the thyristor, the inverter conductive sensor included in its power a circuit, a voltage source, the output of which is connected to the first input of the comparator, a voltage source of control, the output of which is connected to the input of the integrator, characterized in that increase the reliability when the converter operates on a load with variable parameters; it is equipped with a low-frequency filter, an O-trigger with a setup input, a sample-storage device and a second comparator, the output of the inverter conductive sensor being connected through the low-pass filter to the second input the output of which is connected to the clock input of the D-flip-flop, the output of the integrator is connected to the information input of the sampling-storage device and to the second input of the second comparator, the output of the device The rci-storage is connected to the input of the master oscillator and to the first input of the second comparator, the output of which is connected to the installation input of the D-flip-flop, the D input of which is connected to the common bus, and the inverse output is connected to the control input of the sample-hold device. 0 five 0 five 50 55 2, The device according to claim 1, about tl and the fact that the sensor of the inverter END state contains two current transformers connected respectively to the circuit of the thyristor and the reverse diode of the resonant inverter, and the end of the current transformer winding circuit of the thyristor connected to the beginning of the winding the current transformer in the diode circuit to a common point; the second terminals of the current transformer windings through the diodes are connected to the first terminal of the first resistor, the second terminal of which is connected to the cathode of the zener diode and the first capacitor lead, the zener diode anode and the second capacitor lead are connected to the common connection point of the secondary windings, in parallel with which the second and third resistors are connected. ten  € phi.1 15 and. pn ppppppppppppppppp t I inepi Us . u. fig.Z Editor E. Kopcha Compiled by S.Stankevich Tehred M. KhodanychKorrektor N. Ko role Order 2675/55 Circulation 665 VNII1Sh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 - 6 t  -i tnffp2 Subscription