SU1368983A1 - Synchronous frequency divider by 14 - Google Patents

Description

21) 409 096 / 24-21 1:22) 07/18/86 46) 01/23/88. Bul № 3 (72) Yu.A. Bazalev and V.I.M. dreams (53) 621.374 (088.8) (56) USSR author's certificate 1225010, cl. H OZK23 / 40, 02.10.84. USSR Author's Certificate 1243130, cl. H 03 K 23/40, I7.01.85. i4) SYNCHRONOUS FREQUENCY DIVIDER

14

7) The invention relates to a pulse-ei technique and can be used) and the construction of chronizers, digital

frequency synthesizers and electromusical instruments. The purpose of the invention, the speed increase, is achieved by the removable execution of the synchronous frequency sharing and the introduction of new functional connections between the removable elements. The proposed frequency divider contains IK-triggers 1-4. item 5, clock bus 6 and reset bus 7. The operation of the frequency divider by 14 is determined by the logical equations for the I and K inputs of all 1K triggers and is illustrated by the timing diagrams given in support of the invention. 2 Il.

U

with od

00

with

OS

00

The invention relates to a pulse technique and can be used, for example, to build chronizators, digital frequency synthesizers and electromusical instruments.

The purpose of the invention — speed increase — is achieved by the fact that in a known synchronous frequency divider at 14, containing four 1K-flip-flops and one AND element, the counting inputs of all 1K-flip-flops are connected to the clock bus, and the R-inputs to the reset bus, the inverse output of the second 1K-flip-flop is connected to the 1-input of the third 1K-flip-flop and the first input, and the direct output is connected to the K-input of the third 1K-flip-flop and the first input of the And element, the second input of which is connected to the inverse of the third 1K-flip-flop, in which the inverse output of the third 1K-flip-flop is connected n with the I and K inputs of the first 1K flip-flop, the direct output of which is connected to the I and K inputs of the second 1K flip-flop, the inverse output of which is connected to the I and K inputs of the fourth 1K flip-flop, the inverse output of which is connected to the third input of the element I, whose course forms the output bus of the device.

FIG. 1 shows an electrical functional diagram of a synchronous frequency divider by 14; in fig. 2 - time diagrams that show his work.

Synchronous frequency divider by 14 contains the first 1, second 2, third 3 and fourth 4 1K-triggers. the element And 5, the clock bus 6, the bus 7 reset. The counting inputs of all 1K-flip-flops 1-4 are connected to the clock bus 6, and the R-Bodes with the reset bus 7. The direct output of the second 1K flip-flop 2 is connected to the first input of the And 5 element and to the K-input of the third 1K-flip-flop 3, the inverse output of which is connected to the second input of the And 5 element and to the 1- and K-inputs of the first 1K-flip-flop 1, The direct output of which is connected to the I and K inputs of the second 1K flip-flop 2, the inverse input of which is connected to the 1 input of the third XK flip-flop 3 and to the I and K inputs of the fourth 1K flip-flop 4, the inverse output of which is connected to the third input element And 5, the output of which forms the output bus 8 transfer.

In this scheme of connecting the elements, the logical equations for the I and K inputs of the GC flip-flops 1-4 and the transfer signal are

i, Q ,; ,; ; i, Qi;

K, Q3; K, Q ,; K, Q ,; K, Qj;

P Q2Q3Q4.

The operation of the synchronous frequency divider at 14 on 1K triggers, defined by the logical equations for the I and K inputs of all 1K triggers 1–4, is carried out in the following order.

On the Reset signal, arriving as a pulse on the reset bus 7, all 1K-TriggerB1-4 are set to the initial zero state, after which the output states are equal (diagrams Q, Q, Q, Q, Q with i 0):

0,0; 0 0; Q, 0; P 0.

Based on the logical equations for the I and K inputs of all 1K triggers 1-4 of the proposed state device and the 1 and K inputs will be as follows:

I,, O; I, Q, 1; K, Q, 1; K, Q, 0; K,

Since the IK flip-flop on the last input clock pulse at and does not change its state, when and switches to the opposite state, when and switches to the state of a logical one, and at the state of a logical zero, then on the first clock pulse, received on bus 6 after the end of the signal Reset on bus 7, the first 1, third 3 and fourth 4 1K-three heres are switched to the state of logical one, and the second 1K-flip-flop does not change its state (diagram at). In this state of exit

Q, 1; QZ 0; Q, 1; Q 1; . Input states change; 1.0; 1.1;

K, 0; K, 0; .

as a result, on the second tactical pulse the device goes into its

The second state, which is characterized by the following values of the outputs

the inputs of all 1K-flip-flops 1-4 transfer signals P at the element output

5 (charts with):

Q, i;

I, 0; I, 0; I, 0;

K, 0; At the third cycle (diagrams with 3) of the output state

Q, i; by.

Considering the operation of the device in the same way and further, all get 100 inputs and outputs for all i. 25, the match of the signals 0, Qj, is satisfied. Therefore, the transfer signal at the high of the element U 5 in these cycles P 1,

its duration is € 2Т, where T is the 30th duration of the period of follow-up of tires on the tire 6.

According to the fifteenth clock pulse, the 1K-triggers 1-4 return to the zero state:,.

oh

13689834

Q, 0; Q, 0; , Q, Q, 0.

ten

15

0

five

0

,

B

This ends the cycle of operation of the synchronous frequency divider by 14, then its operation repeats every 14 clock pulses.

Claims (1)

Invention Formula Synchronous frequency divider by 14, containing the first, second, third and fourth 1K-flip-flops, C- and R-inputs which are connected respectively to the clock bus and the reset bus, and the element I, the first input of which is connected to the K-input of the third 1K-trigger, the inverse output of which is connected to the second input of the element I, and with the direct output of the second 1K-trigger, the inverse output of which is connected to the 1-input of the third 1K-flip-flop, while the 1-inputs of the first, second and fourth 1K-flip-flops are connected to the K-inputs of the corresponding 1K-flip-flops, characterized in that the third IK trigger is connected to the K input of the first A 1K flip-flop, the direct output of which is connected to the K input of a second 1K flip-flop, the inverse output of which is connected to the K input of a fourth 1K flip-flop, the inverse output of which is connected to the third input of element I.