SU1218469A1 - Device for demodulating delta modulated signals - Google Patents

Abstract

The invention is intended for use in automation and communication technology. Invention-pervo-. It is necessary to reduce the output signal distortion due to the U of the dependence of the quantization step on the compression voltage. The device contains four current stabilization cascade 1-4, three switches J5-7, three capacitors 8-10, subtraction element 11, trigger 14, key 13 and comparison unit 12, consisting of two comparators 22, 23, two inverters 20, 21, two elements AND 24, 25 and element OR 26. The use of comparison unit 12, in which the difference signal from the output of subtraction element 11 is compared with the compression voltage, and trigger 14 with switches 6, 7, is implemented alternately with clock the frequency of the capacitors 9, 10; to the output of the device, allowing It is impossible to obtain a linear dependence of the quantization step on the compression voltage. 1 z.p, f-ly. 2 Il. (O ke S 4 a; o

Description

The invention relates to automation and communication technology and can be used as a decoder in systems with delta modulation.

The aim of the invention is to reduce output distortion.

FIG. 1 is a functional block diagram of a device for demodulating delta-modulated signals; Fig. 2 is a functional block diagram comparison.

The device contains first, second, third, and fourth current stabilizing stages 1–4, first, second, and third switches, first, second, and third capacitors 8–10, subtraction element 11, comparison unit 12, key 13, and trigger 14. Element output 11, the subtraction is connected to the first input of the comparison unit 12. The output of the first current stabilizing stage 1 is connected to the input of the first switch 5, the control input of which is combined with the second input of the comparator unit 12 and connected to the information input 15 of the device. The third input of the comparison unit 12 is connected to the compression input 16 of the device, and the output is connected to the first input of the key 13, the output of which is connected to the input of the fourth current stabilizing stage 4, the first and the second outputs of which are connected respectively to the input of the first and the second and third current stabilizing cascades 1,2,3. The second key input is combined with the counting input of the trigger 14 and is connected to the clock input 17 of the device. The first and second outputs of the first switch 5 are combined with the outputs of the second 2 and third 3 current-stabilizing stages, respectively, and connected, respectively, to the direct 18 and inverse 19 outputs of the device. The capacitors 8, 9, 10 are connected by their first outputs to a common bus, and the second outputs are respectively to the second output of the first switch 5, the first input of the second 6 and the first input of the third 7 switches, and the second inputs of the switches 6, 7 are connected to the first inputs of the switches 7, 6. The outputs of the switches 6,7 are connected to the inputs of the subtracting element 11, the output of the second switch 6 is also combined with the first output of the first switch 5. The output of the trigger 14 is connected to the control inputs of the switch Leu 6, 7. Comparison unit 12 consists of two inverters 20, 21, two comparators: 22, 23, two elements AND 24, 25 and element OR 26, the output of which. is the output of comparison unit 12. The first inputs of the comparators 22, 23

10 are combined and connected to the first input of the block 12, the outputs of the comparators 22, 23 are connected to the first inputs of the corresponding elements AND 24, 25, the outputs of which are connected to the inputs of the element OR 26. The second input

The first element And 24 is connected to the second input of the comparator unit 12 and through the first inverter 20 is connected to the second input of the second element And 25.

20 Similarly, the second input of the first comparator 22 is connected to the third input of the comparator unit 12 and through the second inverter 21 is connected to the second input of the second comparator 23.

25 A device for demodulating a delta-modulated signal operates as follows.

The first current stabilization stage 1 generates a current equal to Ij,

30 which is two times more than

the current Ig generated by the second, and the current If generated by the third current-stabilizing cascades 2, 3, respectively, while the condition

35 ..

Fourth current stabilizing. cascade 4 controls the operation of the first three current stabilizing stages 1–40 3, with all current stabilizing stages 1–4 operating in the key mode.

Let the input of the input 15 to the control input 45 of the switch 5 receive a logic 1 signal, which indicates the need to increase the output signal values by the quantization step Di. At the same time, let the 5Q switches 6 and 7 be in such. the state that the second capacitor 9 is connected to the connection point; - the first output of the first switch 5 is not connected with the output of the second current stabilizing stage by the second input of the subtraction element 11. The capacitor 10 is therefore not connected to the first input of the subtracting unit 11.

3

at the output of which a difference is formed

4U () K,

where K is the gain of subtraction unit 11.

The magnitude of the difference obtained is L (J is compared in comparison block 12 with the value of the compression voltage from input 16, which determines the quantization step size and is equal to

ikompR Ai-K, where Ai is the magnitude of the quantization step

Comparison unit 12 operates in such a way that a logical 1 signal appears at its output if, when a logical 1 signal arrives at input 15, and the result of an open element H 24 is compared, the result of the comparison and U and the copy from the output of the comparator 22 arrive through the element OR 26 to the output of the unit 12 comparison. When a pulse of logical O is received at input 15, the signal of logical 1 at the output of comparison unit 12 is determined by the output signal of comparator 23, if AND 25 and OR 26 are open through the open element.

Since at the initial moment of time the voltage across all capacitors 8-10 is zero, the signal at the input of the comparison unit 12 is equal to logical 1, the potential of which from the output of the comparison unit 12 is applied to the first input of the key 13, the second input of which is connected to the clock input 17

At the moment when the clock signal arrives, the key 13 opens and enables the fourth current stabilizing stage 4, which turns on the current stabilizing stages 1, 2 and 3, because the input signal 15 has arrived at the input 15, the first switch 5 is in this state When the current 1d passes through it to the connection point of the output of the current-stabilizing stage 2 and the first input of the subtracting element 11, as well as through the second switch .6 to the second capacitor 9 Taking into account that 1d is positive, we find that the capacitor 9 is charged itelnym current equal 1e -IB- Simultaneously first capacitor 8 is discharged in precisely the same magnitude but opposite in direction to the current.

1HA69

At the point in time when the output voltage of the subtracting element 1 1 becomes equal to the compression voltage, the output of the comparison unit 12 is a logical O signal and all the current stabilizing stages 1-4 turn off. The voltage change on the capacitors 8 and 9 stops, on this cycle of operation

10 of the device ends.

With the arrival of the next clock pulse, the trigger 14 changes its state and, respectively, switches 6 and 7 change their state.

15 Now the capacitor 9 appears. connected to the second input of the subtracting element 11, and the third capacitor 10 to the connection point of the first output of the first switch 5

20 with the output of the second current stabilizing stage 2 and the first input of the subtracting element 11. Let the input signal 15 still present a logical signal 1. The output voltage of the 25 subtracting element of the subtraction element 11 becomes (i), and since. + UU,.

At the output of comparator unit 12, a signal 1 appears, which you-.

3Q turns on the current stabilizing stages 1-4, while the capacitor 10 through the switch 6 is charged with current BEFORE the voltage at the output of the subtraction element 11 becomes D U K-jlU. At the moment of equality of the voltages UU and U, |, p at the output of the comparator unit 12, a logic signal O appears and the further change of the capacitor 10 stops.

If at the input 15 there is a logical O signal, then at the output of the comparison unit 12 there is a logical 1 signal in the event that L becomes equal to O at & CI-D. In this case, the capacitor that is currently connected to the outputs of the current-stabilizing stages 1, 2 is discharged by the current Ig, and the first condenser 8 is charged by the current by exactly the same amount as the capacitor connected to the output of the current-stabilizing cascades 1,2.

55

Claims (2)

1. Device for demodulating delta-modulated signals. 35 40 containing four current-stabilizing stages, the first and second capacitors, and the first switch, the control input of which is the information input of the device, the input is connected to the output of the first current-stabilizing stage, and the first one. and the second outputs are combined with the outputs of the second and third current stabilizing stages, respectively, and are respectively the forward and inverse outputs of the device, the first and second outputs of the fourth current stabilization stage are connected respectively to the input of the first and the inputs of the second and third current stabilizing stages, the first terminals of the capacitors are connected to the common bus, the second output of the first capacitor is connected to the second output of the first switch, which, in order to reduce the distortion of the output signal, the second and third switches are entered into it, TptT-my capacitor, trigger, key, comparison unit and subtraction element, the first input of which is connected to the output of the second and the first output of the first switch, with the input connected to the output of the third switch, the output of the subtraction element is connected to the first input of the comparator unit, the second and third inputs of which are connected respectively , with an information input and a platoon compression device, and the output is connected five 0 five 0 To the first input of the key, the output of which is connected to the input of the fourth current-stabilizing stage, the second, the KEY input is combined with the counting trigger input and is connected to the clock input of the device, the first output of the third capacitor is connected to the common bus, the output of the trigger is connected to the control inputs of the second and the third switch, the first input of each of which is combined with the second input of the other and connected to the second output of the corresponding capacitor. 2. The device according to claim 1, characterized in that the comparison unit contains the first and second inverters, the first and second elements AND, the OR element and the first and second comparators, the first inputs of which are combined and connected to the first input of the comparison unit, and the outputs are connected to the first inputs of the corresponding AND elements, the outputs of which are connected to the inputs of the OR element, the output of which is the output of the comparison unit, the second input of the first AND element is connected to the second input of the comparison unit and. through the first inverter is connected to the second input of the second element I, the second input of the first comparator is connected to the third input of the comparison unit and through the second inverter is connected to the second input of the second comparator.