SU1160564A2 - Phase-lock loop - Google Patents

Abstract

DEVICE OF PHASE AUTO PRESENTATION OF FREQUENCY according to author. St. No. 1012444 about the fact that, in order to increase speed, between the output of the reference generator and the input of the zero setting of the frequency divider are connected in series the pulse shaper and the AND element, and between the outputs of the difference frequency selector and the other input of the element And the third element is included. OR.

Description

(Ls

O5

about ate

about

4 The invention relates to radio engineering and can be used in high-speed wide-range synchronization systems, frequency synthesizers of radio measuring devices, where steady-state error is required, close to zero. According to the main author. St. No. 1012444 known device phase-locked loop (PLL), containing a ring connected tunable oscillator divider circuit, phase detector, the first low pass filter, the output of which is connected to the first control input of the tunable generator, the first input of the phase detector connected to the divider output frequencies, and the second with the output of the reference oscillator, a coarse frequency control channel of the tunable oscillator, including a differential frequency selector connected in series, the inputs of which о are connected to the outputs of the reference generator and frequency divider, reversible counter, digit converter - analogue, the second low-pass filter, the output of which is connected to the second control input of the tunable generator, as well as the phase comparator and two OR elements, and the inputs of the phase comparator connected to the outputs of the reference generator and frequency divider, and the outputs of the phase comparator are connected to the first inputs of two 1-SHI elements whose second inputs are connected to the outputs of the difference frequency selector, while you ode OR elements are connected to inputs of a reversible counter On However, the known device possesses the significant time transient in the restructuring of the generator over a range. This is due to the fact that for large frequency detuning of the signals of the reference and tunable generators, the change in the state of the reversible counter occurs mainly due to the impulse coming from the differential frequency allocator (once per period of the difference frequency). When decreasing the detuning (differential frequency), the main reason for the change in the state of the reversible counter is the occurrence of pulses from the phase comparator (with the frequency of the reference signal). Considering that the phase difference of the signals arriving at the phase comparator in the adjustment process does not take into account both positive and negative values, the code of the reversible counter changes both upwards and downwards. Therefore, during part of the period, the signal arriving at the tunable generator via a coarse trim channel produces a not a tuning but a frustrating action. As the inertia increases (the retention band decreases) of the exact adjustment channel, this effect significantly increases the duration of the transient process. The purpose of the invention is to increase the speed. . To do this, in the PLL device containing a tunable oscillator, a frequency divider, a phase detector, a first low-pass filter, the output of which is connected to the first controllable input of the tunable oscillator, and the first. The second input of the phase detector is connected to the output of a frequency divider, and the second to the output of a reference oscillator, as well as a coarse frequency control channel for a tunable oscillator, including series-connected,. difference frequency extractor, whose inputs are connected to the outputs of the reference oscillator and frequency divider, reversible counter, digitizer converter -. analogue, the second low-pass filter, the output of which is connected to the second control input of the tunable generator, as well as the phase comparator and two OR elements, the inputs of the phase comparator connected to the outputs of the reference generator and frequency divider, and the outputs of the phase comparator are connected to the first inputs. Two OR elements, the second inputs of which are connected to two differential frequency separator outputs, while the outputs of the OR elements are connected to the reverse inputs of the smart counter, between the output of the reference Generator and the installation input of the zero frequency divider are connected in series the driver of impulses and element I, and between the outputs of the difference frequency selector and the other input of the AND element included the third element OR. Fig, 1 shows a diagram of the proposed device PA; in fig. 2 time diagrams of the operation of the PLL. The device contains a tunable oscillator 1, a divider 2 frequencies, a phase detector 3, a reference generator 4, the first one. The lower filter 5 is often a difference frequency selector 6, a recallable counter 7 "converter 8 digit - analog second filter 9 lower frequencies, phase comparator 10, the first 11 and second 12 elements OR, the shaper 13 pulses, the third element 1 Sh 14 and the element And 15. The device works as follows. When detuning is greater than the capture band of the PLL, at the output of the phase detector 3 there is a variable voltage whose frequency is equal to the beat frequency periodically changing through the first filter 5 lower clock frequency of the tunable oscillator 1 within the band of the PLL. The frequency adjustment of the tunable oscillator 1 to the frequency of the reference oscillator 4 is carried out mainly through the coarse channel. Since the nodes of the difference frequency selector 6 and phase comparator 1 are usually performed in digital form, we believe that the formation of pulses of the required duration occurs in blocks 6 and 10. For large frequency detuning, the coarse channel tuning is performed mainly by the effect of the difference 6 frequencies, and at smaller detuning, the signal coming from the phase comparator 10 is dominant. To eliminate the detuned effect of a coarse trim channel. in the proposed device, with a forced cyclic setting, the phase difference of the compared signal () occurs once the image point goes to the movement section corresponding to the inverse code change in the reversible counter (sections T) of FIG. .2). As a result, these signals arriving at phase detector 3 and phase comparator 10 always have this phase difference. matching, in which the state of reversing Roro of counter 7 is changed only in the direction decreasing the initial frequency detuning (Fig. 2 & 2). To determine the moment of the forced installation of the difference of the phases, signals from the outputs of the difference frequency selector 6 are used. They appear exactly at those moments of time when the phase difference of the compared signals exceeds the multiples of t2f, after that, in the known device, the point falls on the motion segment with increasing frequency detuning. In the proposed device, these movements are eliminated by forcibly influencing the phase of the signal from the tunable generator 1 by resetting the divider 2 in the frequency. The moment of reset in O splitter 2 is determined by the element 15, provided that a pulse appears at one of the outputs of the difference frequency selector 6 (depending on the sign of the initial frequency detuning) and the pulse from the output of the pulse former 13 pulses. Moreover, in order to realize the condition CHk T, it is necessary to have a waveform of the reference generator 4, close to the meander wave, and to generate pulses arriving at the AND 15 element from the corresponding front of the signal of the reference oscillator 4. For the normal operation of the device it is necessary that 6 difference frequency, was not less than half the period of the reference signal. FIG. 2 "shows the diagrams of operation of the known device and the following notation is accepted: FCMCt)) normalized beat voltage at the output of the phase detector 3 with a sawtooth characteristic of the phase center; - Immersions. . . . eg formed from the signal of the reference generator 4, the frequency of which is equal to the frequency of the reference generator; and -) - - pulses coming from the phase comparator 10 to the input of the addition of the reversible counter 7; and - - # 1 pulses arriving at the input of the subtraction of the reversible counter 7; Ugpn - pulses at the output of the difference frequency extractors 6; the time intervals during which the reversal counter 7 is counted down (the digital integrator increases the frequency spreading / construction). FIG. 2f illustrates the operation of the proposed PLL device. FIG. 2b shows the change in frequency control in a known device. (curve 1) and. The proposed designation (crisis 2) and the following notation is accepted: A - frequency detuning between the compared signals; about - initial frequency detuning; d - change of frequency detuning when changing the code of the reverse counter from one;

/and

kn 11 FA11CH ring capture band along the exact control channel. The advantage of the proposed device PLL compared with the known is to increase the speed. As can be seen from FIG. 2b transient time in the proposed device with the same initial. The conditions in this case are 3 times less than in the known device, and the gain from the use of the proposal increases with an increase in the initial frequency detuning and inertia of the exact control channel.

Claims (1)

DEVICE OF PHASE AVT0P0DSTROYKI FREQUENCY according to ed. St. No. 1012444; This is due to the fact that, with a view to. improve performance, between the output of the reference generator and the input of the zero setting of the frequency divider are connected in series pulse shaper and the element And, and between the outputs of the difference frequency separator and the other input of the element And the third element is included. OR.