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SG86356A1 - Error correction system, error correction method, and data memory with correction function - Google Patents

Error correction system, error correction method, and data memory with correction function

Info

Publication number
SG86356A1
SG86356A1 SG9904524A SG1999004524A SG86356A1 SG 86356 A1 SG86356 A1 SG 86356A1 SG 9904524 A SG9904524 A SG 9904524A SG 1999004524 A SG1999004524 A SG 1999004524A SG 86356 A1 SG86356 A1 SG 86356A1
Authority
SG
Singapore
Prior art keywords
error correction
data memory
function
correction
error
Prior art date
Application number
SG9904524A
Inventor
Ushio Teruhiko
Yamada Kohji
Kanai Toshio
Kunieda Eiji
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG86356A1 publication Critical patent/SG86356A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
SG9904524A 1998-09-25 1999-09-15 Error correction system, error correction method, and data memory with correction function SG86356A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27191298A JP3272308B2 (en) 1998-09-25 1998-09-25 Error correction system, error correction method, and data storage system having error correction function

Publications (1)

Publication Number Publication Date
SG86356A1 true SG86356A1 (en) 2002-02-19

Family

ID=17506620

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9904524A SG86356A1 (en) 1998-09-25 1999-09-15 Error correction system, error correction method, and data memory with correction function

Country Status (4)

Country Link
JP (1) JP3272308B2 (en)
KR (1) KR100339452B1 (en)
SG (1) SG86356A1 (en)
TW (1) TW436767B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6872053B2 (en) 1997-05-05 2005-03-29 King Of Fans Quick install blade arms for ceiling fans
KR20010081335A (en) * 2000-02-12 2001-08-29 구자홍 Coding method for correcting error of digital data in high density disc
CN100530980C (en) * 2003-07-09 2009-08-19 汤姆森特许公司 Error correction method for reed-solomon product code
US7607071B2 (en) * 2005-01-28 2009-10-20 Intel Corporation Error correction using iterating generation of data syndrome
KR100724211B1 (en) * 2006-05-09 2007-05-31 엘지전자 주식회사 Error correction coding method of digital data for next generation high density recording media
JP2008077458A (en) 2006-09-22 2008-04-03 Fujitsu Ltd Storage data processing device, storage device, storage data processing program
KR102281751B1 (en) * 2015-10-01 2021-07-27 에스케이하이닉스 주식회사 Operating method of flash memory system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761220A (en) * 1994-09-19 1998-06-02 Cirrus Logic, Inc. Minimum latency asynchronous data path controller in a digital recording system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761220A (en) * 1994-09-19 1998-06-02 Cirrus Logic, Inc. Minimum latency asynchronous data path controller in a digital recording system

Also Published As

Publication number Publication date
KR100339452B1 (en) 2002-06-05
KR20000022714A (en) 2000-04-25
TW436767B (en) 2001-05-28
JP2000112776A (en) 2000-04-21
JP3272308B2 (en) 2002-04-08

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