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SG73403A1 - Memory controller which executes read and write commands out of order - Google Patents

Memory controller which executes read and write commands out of order

Info

Publication number
SG73403A1
SG73403A1 SG1996006440A SG1996006440A SG73403A1 SG 73403 A1 SG73403 A1 SG 73403A1 SG 1996006440 A SG1996006440 A SG 1996006440A SG 1996006440 A SG1996006440 A SG 1996006440A SG 73403 A1 SG73403 A1 SG 73403A1
Authority
SG
Singapore
Prior art keywords
order
memory controller
write commands
executes read
commands out
Prior art date
Application number
SG1996006440A
Other languages
English (en)
Inventor
L Randall Mote Jr
Original Assignee
Ast Res Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/415,038 external-priority patent/US5638534A/en
Priority claimed from US08/414,948 external-priority patent/US5666494A/en
Application filed by Ast Res Inc filed Critical Ast Res Inc
Publication of SG73403A1 publication Critical patent/SG73403A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
SG1996006440A 1995-03-31 1996-03-30 Memory controller which executes read and write commands out of order SG73403A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/415,038 US5638534A (en) 1995-03-31 1995-03-31 Memory controller which executes read and write commands out of order
US08/414,948 US5666494A (en) 1995-03-31 1995-03-31 Queue management mechanism which allows entries to be processed in any order

Publications (1)

Publication Number Publication Date
SG73403A1 true SG73403A1 (en) 2000-06-20

Family

ID=27022792

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996006440A SG73403A1 (en) 1995-03-31 1996-03-30 Memory controller which executes read and write commands out of order

Country Status (10)

Country Link
EP (1) EP0838057B1 (zh)
JP (1) JPH0955081A (zh)
KR (1) KR100295187B1 (zh)
CN (1) CN1088215C (zh)
AU (1) AU693668B2 (zh)
DE (1) DE69625486T2 (zh)
RU (1) RU2157562C2 (zh)
SG (1) SG73403A1 (zh)
TW (1) TW388982B (zh)
WO (1) WO1996030838A1 (zh)

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US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6343352B1 (en) 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6038646A (en) * 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
JP4817477B2 (ja) * 1998-10-30 2011-11-16 富士通セミコンダクター株式会社 半導体記憶装置
GB2348717B (en) 1999-01-11 2003-08-06 Sgs Thomson Microelectronics Data flow control circuitry
DE69939152D1 (de) * 1999-01-11 2008-09-04 Sgs Thomson Microelectronics Speicherschnittstellenvorrichtung und Verfahren zum Speicherzugriff
KR100287188B1 (ko) * 1999-04-06 2001-04-16 윤종용 데이터 처리속도 및 데이터 입출력핀의 효율을 향상시킬 수 있는 반도체 메모리장치 및 이의 독출기입 제어방법
EA001895B1 (ru) * 2001-02-15 2001-10-22 Лев Лазаревич Матвеев Способ получения, обработки и хранения ссылок на информационные источники, списков ссылок и полных копий информационных источников
US20040054877A1 (en) 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7469316B2 (en) 2003-02-10 2008-12-23 Intel Corporation Buffered writes and memory page control
AU2003900733A0 (en) * 2003-02-19 2003-03-06 Canon Kabushiki Kaisha Dynamic Reordering of Memory Requests
US7237074B2 (en) * 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US7076611B2 (en) * 2003-08-01 2006-07-11 Microsoft Corporation System and method for managing objects stored in a cache
US7484045B2 (en) 2004-03-30 2009-01-27 Intel Corporation Store performance in strongly-ordered microprocessor architecture
US20060112240A1 (en) * 2004-11-24 2006-05-25 Walker Robert M Priority scheme for executing commands in memories
US20070005868A1 (en) * 2005-06-30 2007-01-04 Osborne Randy B Method, apparatus and system for posted write buffer for memory with unidirectional full duplex interface
US20070239996A1 (en) * 2006-03-20 2007-10-11 Cromer Daryl C Method and apparatus for binding computer memory to motherboard
US9262326B2 (en) * 2006-08-14 2016-02-16 Qualcomm Incorporated Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
CN101299326B (zh) * 2007-05-14 2010-05-26 深圳艾科创新微电子有限公司 一种图形显示系统中变长显存预读系统及方法
US7890668B2 (en) * 2008-02-14 2011-02-15 International Business Machines Corporation Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous
US7848144B2 (en) * 2008-06-16 2010-12-07 Sandisk Corporation Reverse order page writing in flash memories
US20140219021A1 (en) * 2013-02-07 2014-08-07 Seagate Technology Llc Data protection for unexpected power loss
CN102945213B (zh) * 2012-09-24 2016-08-10 无锡众志和达数据计算股份有限公司 一种基于fpga的乱序内存控制器及其实现方法
US9021228B2 (en) 2013-02-01 2015-04-28 International Business Machines Corporation Managing out-of-order memory command execution from multiple queues while maintaining data coherency
CN113672529B (zh) * 2020-05-15 2025-06-20 恩智浦美国有限公司 用于直接存储器访问的系统和方法
CN115729475B (zh) * 2022-12-09 2025-07-18 重庆航天工业有限公司 一种实现存储器连续写入的方法
CN119621603B (zh) * 2025-02-17 2025-07-11 中科亿海微电子科技（苏州）有限公司 一种缓存一致性维护方法、装置和多核系统

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Also Published As

Publication number Publication date
CN1180430A (zh) 1998-04-29
AU5039896A (en) 1996-10-10
AU693668B2 (en) 1998-07-02
KR960035270A (ko) 1996-10-24
RU2157562C2 (ru) 2000-10-10
EP0838057A1 (en) 1998-04-29
EP0838057A4 (en) 2000-05-10
DE69625486T2 (de) 2009-09-17
EP0838057B1 (en) 2002-12-18
CN1088215C (zh) 2002-07-24
WO1996030838A1 (en) 1996-10-03
DE69625486D1 (de) 2003-01-30
TW388982B (en) 2000-05-01
JPH0955081A (ja) 1997-02-25
KR100295187B1 (ko) 2001-09-17

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