SG55185A1 - Circuit arrangement for forming the sum of products - Google Patents
Circuit arrangement for forming the sum of productsInfo
- Publication number
- SG55185A1 SG55185A1 SG1996009097A SG1996009097A SG55185A1 SG 55185 A1 SG55185 A1 SG 55185A1 SG 1996009097 A SG1996009097 A SG 1996009097A SG 1996009097 A SG1996009097 A SG 1996009097A SG 55185 A1 SG55185 A1 SG 55185A1
- Authority
- SG
- Singapore
- Prior art keywords
- sum
- products
- forming
- circuit arrangement
- arrangement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/462—Saving or restoring of program or task context with multiple register sets
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
- G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4242929A DE4242929A1 (en) | 1992-12-18 | 1992-12-18 | Circuit arrangement for forming the sum of products |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG55185A1 true SG55185A1 (en) | 1998-12-21 |
Family
ID=6475741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG1996009097A SG55185A1 (en) | 1992-12-18 | 1993-12-17 | Circuit arrangement for forming the sum of products |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0627099A1 (en) |
| JP (1) | JPH08500690A (en) |
| KR (1) | KR100337716B1 (en) |
| DE (1) | DE4242929A1 (en) |
| SG (1) | SG55185A1 (en) |
| WO (1) | WO1994015278A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19717970B4 (en) * | 1997-04-28 | 2006-11-09 | Systemonic Ag | Circuit arrangement of a digital module for multiplication and addition of binary numbers |
| US7711765B2 (en) * | 2006-02-17 | 2010-05-04 | Telefonaktiebolaget L M Ericsson (Publ) | Method and apparatus to perform multiply-and-accumulate operations |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7712367A (en) * | 1977-11-10 | 1979-05-14 | Philips Nv | DIGITAL ADDITIONAL COMPUTER. |
| EP0042452B1 (en) * | 1980-06-24 | 1984-03-14 | International Business Machines Corporation | Signal processor computing arrangement and method of operating said arrangement |
| US5128890A (en) * | 1991-05-06 | 1992-07-07 | Motorola, Inc. | Apparatus for performing multiplications with reduced power and a method therefor |
-
1992
- 1992-12-18 DE DE4242929A patent/DE4242929A1/en not_active Withdrawn
-
1993
- 1993-12-17 KR KR1019940702887A patent/KR100337716B1/en not_active Expired - Fee Related
- 1993-12-17 WO PCT/NL1993/000267 patent/WO1994015278A1/en not_active Ceased
- 1993-12-17 EP EP94903145A patent/EP0627099A1/en not_active Withdrawn
- 1993-12-17 SG SG1996009097A patent/SG55185A1/en unknown
- 1993-12-17 JP JP6515035A patent/JPH08500690A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR100337716B1 (en) | 2002-11-22 |
| WO1994015278A1 (en) | 1994-07-07 |
| EP0627099A1 (en) | 1994-12-07 |
| JPH08500690A (en) | 1996-01-23 |
| KR950700571A (en) | 1995-01-16 |
| DE4242929A1 (en) | 1994-06-23 |
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