SG142201A1 - Method for fabricating a dual damascene structure - Google Patents
Method for fabricating a dual damascene structureInfo
- Publication number
- SG142201A1 SG142201A1 SG200607730-9A SG2006077309A SG142201A1 SG 142201 A1 SG142201 A1 SG 142201A1 SG 2006077309 A SG2006077309 A SG 2006077309A SG 142201 A1 SG142201 A1 SG 142201A1
- Authority
- SG
- Singapore
- Prior art keywords
- layer
- fabricating
- dielectric layer
- dual damascene
- damascene structure
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 5
- 230000009977 dual effect Effects 0.000 title abstract 3
- 238000005530 etching Methods 0.000 abstract 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
METHOD FOR FABRICATING A DUAL DAMASCENE STRUCTURE A method for fabricating a dual damascene structure contains providing a substrate having a conductive layer, an etching stop layer, a dielectric layer, and a photoresist layer thereon, performing an etching process to remove a portion of the dielectric layer through a via pattern of the photoresist layer for forming a via structure in the dielectric layer, providing CO-containing gas to perform an ash process, filling GFP materials into the via structure, forming a photoresist layer with a trench pattern on the substrate, etching the dielectric layer through the trench pattern to form a trench structure in the dielectric layer, above the via structure, and removing the etching stop layer exposed in the via structure. Figure 15
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG200607730-9A SG142201A1 (en) | 2006-11-07 | 2006-11-07 | Method for fabricating a dual damascene structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG200607730-9A SG142201A1 (en) | 2006-11-07 | 2006-11-07 | Method for fabricating a dual damascene structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG142201A1 true SG142201A1 (en) | 2008-05-28 |
Family
ID=39426740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200607730-9A SG142201A1 (en) | 2006-11-07 | 2006-11-07 | Method for fabricating a dual damascene structure |
Country Status (1)
| Country | Link |
|---|---|
| SG (1) | SG142201A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6042996A (en) * | 1998-02-13 | 2000-03-28 | United Microelectronics Corp. | Method of fabricating a dual damascene structure |
| US6093508A (en) * | 1997-03-28 | 2000-07-25 | International Business Machines Corporation | Dual damascene structure formed in a single photoresist film |
| US6150269A (en) * | 1998-09-11 | 2000-11-21 | Chartered Semiconductor Manufacturing Company, Ltd. | Copper interconnect patterning |
| US6649531B2 (en) * | 2001-11-26 | 2003-11-18 | International Business Machines Corporation | Process for forming a damascene structure |
| US6872666B2 (en) * | 2002-11-06 | 2005-03-29 | Intel Corporation | Method for making a dual damascene interconnect using a dual hard mask |
| US20060024971A1 (en) * | 2004-07-30 | 2006-02-02 | Samsung Electronics Co., Ltd. | Dry etching method using polymer mask selectively formed by CO gas |
-
2006
- 2006-11-07 SG SG200607730-9A patent/SG142201A1/en unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6093508A (en) * | 1997-03-28 | 2000-07-25 | International Business Machines Corporation | Dual damascene structure formed in a single photoresist film |
| US6042996A (en) * | 1998-02-13 | 2000-03-28 | United Microelectronics Corp. | Method of fabricating a dual damascene structure |
| US6150269A (en) * | 1998-09-11 | 2000-11-21 | Chartered Semiconductor Manufacturing Company, Ltd. | Copper interconnect patterning |
| US6649531B2 (en) * | 2001-11-26 | 2003-11-18 | International Business Machines Corporation | Process for forming a damascene structure |
| US6872666B2 (en) * | 2002-11-06 | 2005-03-29 | Intel Corporation | Method for making a dual damascene interconnect using a dual hard mask |
| US20060024971A1 (en) * | 2004-07-30 | 2006-02-02 | Samsung Electronics Co., Ltd. | Dry etching method using polymer mask selectively formed by CO gas |
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