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SG10201402893YA - Data packet processing system on a chip - Google Patents

Data packet processing system on a chip

Info

Publication number
SG10201402893YA
SG10201402893YA SG10201402893YA SG10201402893YA SG10201402893YA SG 10201402893Y A SG10201402893Y A SG 10201402893YA SG 10201402893Y A SG10201402893Y A SG 10201402893YA SG 10201402893Y A SG10201402893Y A SG 10201402893YA SG 10201402893Y A SG10201402893Y A SG 10201402893YA
Authority
SG
Singapore
Prior art keywords
chip
processing system
data packet
packet processing
data
Prior art date
Application number
SG10201402893YA
Inventor
Ingo Volkening
Hak Keong Sim
Ritesh Banerjee
Original Assignee
Lantiq Deutschland Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lantiq Deutschland Gmbh filed Critical Lantiq Deutschland Gmbh
Priority to SG10201402893YA priority Critical patent/SG10201402893YA/en
Priority to EP15728453.0A priority patent/EP3152877B1/en
Priority to PCT/EP2015/062025 priority patent/WO2015185461A1/en
Priority to US15/312,753 priority patent/US10326706B2/en
Priority to CN201580029626.8A priority patent/CN106576084B/en
Publication of SG10201402893YA publication Critical patent/SG10201402893YA/en
Priority to US16/410,112 priority patent/US11153222B2/en
Priority to US17/451,487 priority patent/US20220038385A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3063—Pipelined operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/6215—Individual queue per QOS, rate or priority
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/26—Route discovery packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5691—Access to open networks; Ingress point selection, e.g. ISP selection
    • H04L12/5692—Selection among different networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/325—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the network layer [OSI layer 3], e.g. X.25

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
SG10201402893YA 2014-06-04 2014-06-04 Data packet processing system on a chip SG10201402893YA (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SG10201402893YA SG10201402893YA (en) 2014-06-04 2014-06-04 Data packet processing system on a chip
EP15728453.0A EP3152877B1 (en) 2014-06-04 2015-05-29 Data packet processing system on a chip
PCT/EP2015/062025 WO2015185461A1 (en) 2014-06-04 2015-05-29 Data packet processing system on a chip
US15/312,753 US10326706B2 (en) 2014-06-04 2015-05-29 Data packet processing system on a chip
CN201580029626.8A CN106576084B (en) 2014-06-04 2015-05-29 On-chip data packet processing system
US16/410,112 US11153222B2 (en) 2014-06-04 2019-05-13 Data packet processing system on a chip
US17/451,487 US20220038385A1 (en) 2014-06-04 2021-10-19 Data packet processing system on a chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG10201402893YA SG10201402893YA (en) 2014-06-04 2014-06-04 Data packet processing system on a chip

Publications (1)

Publication Number Publication Date
SG10201402893YA true SG10201402893YA (en) 2016-01-28

Family

ID=54766191

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201402893YA SG10201402893YA (en) 2014-06-04 2014-06-04 Data packet processing system on a chip

Country Status (5)

Country Link
US (3) US10326706B2 (en)
EP (1) EP3152877B1 (en)
CN (1) CN106576084B (en)
SG (1) SG10201402893YA (en)
WO (1) WO2015185461A1 (en)

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US10015048B2 (en) 2014-12-27 2018-07-03 Intel Corporation Programmable protocol parser for NIC classification and queue assignments
US9825862B2 (en) 2015-08-26 2017-11-21 Barefoot Networks, Inc. Packet header field extraction
US9912774B2 (en) 2015-12-22 2018-03-06 Intel Corporation Accelerated network packet processing
US10063407B1 (en) 2016-02-08 2018-08-28 Barefoot Networks, Inc. Identifying and marking failed egress links in data plane
US10841206B2 (en) * 2016-05-31 2020-11-17 128 Technology, Inc. Flow modification including shared context
US10225161B2 (en) * 2016-10-31 2019-03-05 Accedian Networks Inc. Precise statistics computation for communication networks
GB2556636A (en) * 2016-11-21 2018-06-06 The Sec Dep For Foreign And Commonwealth Affairs Method and device for filtering packets
US11245572B1 (en) 2017-01-31 2022-02-08 Barefoot Networks, Inc. Messaging between remote controller and forwarding element
US10686735B1 (en) 2017-04-23 2020-06-16 Barefoot Networks, Inc. Packet reconstruction at deparser
US10505861B1 (en) 2017-07-23 2019-12-10 Barefoot Networks, Inc. Bus for providing traffic management statistics to processing pipeline
US10594630B1 (en) 2017-09-28 2020-03-17 Barefoot Networks, Inc. Expansion of packet data within processing pipeline
US11394666B2 (en) * 2017-12-18 2022-07-19 Intel Corporation Scalable communication with a packet processing unit
US11025678B2 (en) * 2018-01-25 2021-06-01 Seagate Technology Llc AXI interconnect module communication network platform
US12363035B2 (en) 2021-09-29 2025-07-15 Juniper Networks, Inc. Opportunistic mesh for software-defined wide area network (SD-WAN)

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CA2326070C (en) 1999-12-30 2007-10-02 At&T Corp. Handheld integrated ip device
WO2002019634A1 (en) * 2000-08-31 2002-03-07 Netrake Corporation Method for enforcing service level agreements
US20030043800A1 (en) 2001-08-30 2003-03-06 Sonksen Bradley Stephen Dynamic data item processing
US7296067B2 (en) * 2002-12-19 2007-11-13 Research In Motion Limited Wireless/LAN router queuing method and system
US7698457B2 (en) * 2003-11-12 2010-04-13 Andrei Ghetie Scalable and dynamic quality of service control
US8385202B2 (en) * 2008-08-27 2013-02-26 Cisco Technology, Inc. Virtual switch quality of service for virtual machines
US8274908B2 (en) * 2009-07-24 2012-09-25 Intel Corporation Quality of service packet processing without explicit control negotiations
US8571031B2 (en) 2009-10-07 2013-10-29 Intel Corporation Configurable frame processing pipeline in a packet switch
US9344377B2 (en) * 2010-04-30 2016-05-17 Broadcom Corporation Packet processing architecture
US8693470B1 (en) * 2010-05-03 2014-04-08 Cisco Technology, Inc. Distributed routing with centralized quality of service
US9755947B2 (en) * 2010-05-18 2017-09-05 Intel Corporation Hierarchical self-organizing classification processing in a network switch
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WO2014166884A1 (en) * 2013-04-08 2014-10-16 Telefonaktiebolaget L M Ericsson (Publ) Congestion aware throughput targets
US9588923B2 (en) * 2014-01-24 2017-03-07 Applied Micro Circuits Corporation Flow pinning in a server on a chip
US20150324305A1 (en) 2014-05-09 2015-11-12 Vanderbilt University Change management system, change management method, and change management program
SG10201402893YA (en) * 2014-06-04 2016-01-28 Lantiq Deutschland Gmbh Data packet processing system on a chip

Also Published As

Publication number Publication date
US10326706B2 (en) 2019-06-18
EP3152877A1 (en) 2017-04-12
EP3152877B1 (en) 2019-07-03
US20190372905A1 (en) 2019-12-05
US20220038385A1 (en) 2022-02-03
US20170208015A1 (en) 2017-07-20
CN106576084A (en) 2017-04-19
CN106576084B (en) 2020-09-11
WO2015185461A1 (en) 2015-12-10
US11153222B2 (en) 2021-10-19

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