[go: up one dir, main page]

SE8105535L - AS A SINGLE INTEGRATED CLUTCH DESIGNED MICRODATOR - Google Patents

AS A SINGLE INTEGRATED CLUTCH DESIGNED MICRODATOR

Info

Publication number
SE8105535L
SE8105535L SE8105535A SE8105535A SE8105535L SE 8105535 L SE8105535 L SE 8105535L SE 8105535 A SE8105535 A SE 8105535A SE 8105535 A SE8105535 A SE 8105535A SE 8105535 L SE8105535 L SE 8105535L
Authority
SE
Sweden
Prior art keywords
data processor
control unit
single integrated
exchange
buffer storage
Prior art date
Application number
SE8105535A
Other languages
Swedish (sv)
Other versions
SE428162B (en
Inventor
Valery Leonidovich Dshkhunian
Eduard Evgenievich Ivanov
Jury Egorovich Chicherin
Pavel Romanovich Mashevich
Sergei Savvich Kovalenko
Original Assignee
Dshkhunian Valery
Eduard Evgenievich Ivanov
Chicherin Yurij E
Mashevich Pavel R
Kovalenko Sergei S
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dshkhunian Valery, Eduard Evgenievich Ivanov, Chicherin Yurij E, Mashevich Pavel R, Kovalenko Sergei S filed Critical Dshkhunian Valery
Priority to SE8105535A priority Critical patent/SE428162B/en
Publication of SE8105535L publication Critical patent/SE8105535L/en
Publication of SE428162B publication Critical patent/SE428162B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Microcomputer which is configured as a single integrated circuit and comprises a data processor 2, a memory 5, an adapter stage 6, buffer storage cells 7 and a control unit 8 for controlling the exchange of information being transmitted via a system line. All these units are interconnected by a two-way master bus 1. The data processor 2 comprises a calculation control unit 3 and an operation executing unit 4. Furthermore, the data processor 2 includes a buffer storage cell 13, a control unit 14 for the information exchange of the data processor, and an address comparator 15, all of which are interconnected. The microcomputer also comprises a master bus distributor 22 and a system bus distributor 23, which are connected to the control unit 8 for controlling the exchange of information being transmitted via the system bus, as well as a system bus address comparator 39, which is connected to the data processor 2 and the first- mentioned buffer storage cell 7. <IMAGE>
SE8105535A 1981-09-18 1981-09-18 Microcomputer SE428162B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SE8105535A SE428162B (en) 1981-09-18 1981-09-18 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8105535A SE428162B (en) 1981-09-18 1981-09-18 Microcomputer

Publications (2)

Publication Number Publication Date
SE8105535L true SE8105535L (en) 1983-03-19
SE428162B SE428162B (en) 1983-06-06

Family

ID=20344580

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8105535A SE428162B (en) 1981-09-18 1981-09-18 Microcomputer

Country Status (1)

Country Link
SE (1) SE428162B (en)

Also Published As

Publication number Publication date
SE428162B (en) 1983-06-06

Similar Documents

Publication Publication Date Title
JPS57105879A (en) Control system for storage device
DE3786080D1 (en) MEMORY ACCESS CONTROL DEVICE IN A MIXED DATA FORMAT SYSTEM.
KR910001555A (en) Data processor
KR900007680B1 (en) Input/output control system
SE8001183L (en) DATABEHANDLINGSANLEGGNING
EP0382358A3 (en) Full address and odd boundary direct memory access controller
JPS56123051A (en) Data transfer system in master slave system
JPS57117059A (en) Multiprocessor system
SE8105535L (en) AS A SINGLE INTEGRATED CLUTCH DESIGNED MICRODATOR
JPS5476034A (en) Bus data transfer system
JPS5549750A (en) Control and memory unit for data processing system
EP0067519B1 (en) Telecommunications system
JPS5650451A (en) Multiaccess system of multimicrocomputer
JPS54122059A (en) Inter-processor information transfer system
GB2001462A (en) Data communication system
JPS55108027A (en) Processor system
JPS6478362A (en) One connection preparation of several data processors for central clock control multi-line system
JPS57111733A (en) Bus conversion system
JPS6478361A (en) Data processing system
GB2099619A (en) Data processing arrangements
GB1482659A (en) Device for selective exchange of information
JPS57130278A (en) Storage device
JPS5552130A (en) Information processing unit
JPS54100628A (en) Memory-contention control system
JPS5582328A (en) Common bus control system

Legal Events

Date Code Title Description
NUG Patent has lapsed

Ref document number: 8105535-2

Effective date: 19900703

Format of ref document f/p: F