SE529174C2 - Silicon carbide semiconductor device, e.g. power MOSFET, comprises gate insulation film disposed on surface of surface channel layer and including high dielectric constant film - Google Patents

Abstract

Silicon carbide semiconductor device comprises a gate insulating film on a surface of a surface channel layer and including a high dielectric constant film. Silicon carbide semiconductor device comprises a semiconductor substrate (1) made of single crystal silicon carbide and having a principal surface (1a) and a backside surface (1b) opposite the principal surface; a drift layer made of a first conductive type silicon carbide, on the principal surface of the semiconductor substrate and having a dopant concentration lower than a dopant concentration of the semiconductor substrate; a base region (3a,3b) having a second conductive type, disposed on a predetermined area of the drift layer and having a predetermined thickness; a source region (4a,4b) having the first conductive type, disposed on a predetermined surface portion of the base region and being shallower than a depth of the base region; a surface channel layer (5) made of the first conductive type silicon carbide, on surface portions of both of the drift layer and the base region, and having a predetermined concentration and a predetermined thickness for connecting between the source region and the drift layer; a gate insulating film (7) on a surface of the surface channel layer and including a high dielectric constant film; a gate electrode (8) disposed on the gate insulation film; a source electrode on the source region; and a backside electrode on the backside surface of the semiconductor substrate. Independent claims are also included for: (a) manufacturing a silicon carbide semiconductor device comprising preparing a semiconductor substrate made of single crystal silicon carbide having a principal surface and a backside surface opposite the principal surface; forming a drift layer on the principal surface of the semiconductor substrate; forming a base region on a predetermined area on the drift layer; forming a source region on a predetermined surface portion on the base region; forming a surface channel layer on surface portions of both the drift layer and the base region; forming a gate insulation film including a high dielectric constant film on a surface of the surface channel layer; forming a gate electrode on the gate insulation film; forming a source electrode on the source region; and forming a backside electrode on the backside surface of the semiconductor substrate; (b) a silicon carbide semiconductor substrate comprising a principal surface of the substrate including two surfaces, a (0001)- silicon surface and a surface tilted from a (0001)-Si surface by 10[deg]; and (c) manufacturing a silicon carbide semiconductor substrate comprising preparing a silicon carbide semiconductor substrate having a principal surface tilted from a (0001)-Si surface by 10[deg] by a cutting method; mirror-polishing the principal surface of the silicon carbide semiconductor substrate; and depositing an epitaxial layer (2) epitaxially on the principal surface. .

Description

30 35 ~ 529 174 L a defect caused by polishing in a MOS transistor. The MOS transistor includes an emitter region, a collector region, a gate oxide film, and a gate electrode formed on a surface portion of the substrate. Specifically, when the defect caused by polishing occurs on the surface of the substrate, slight current leakage occurs at the gate oxide film.

Furthermore, when a device is formed on the SiO2 substrate after epitaxial growth, for example, a crystal defect caused by a defect caused by polishing on the surface of the substrate may occur in the epitaxial layer of the device (i.e., the diode), so that current leakage (i.e., PN junction leakage) easily occurs.

The device has the epitaxial layer on the substrate, where a P-type conductive region is formed, and has an anode electrode and a cathode electrode. . In view of the above-mentioned problems, it is an object of the invention to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, wherein the device has low resistance in the on-state.

It is another object of the invention to provide a silicon carbide semiconductor substrate and a method for manufacturing a silicon carbide semiconductor substrate, wherein the substrate has an excellent surface condition and smoothness with suppression of defects.

To achieve the said object, a silicon carbide semiconductor device has a gate insulating film including a high dielectric constant film. The device has a stacked type channel layer contacting the gate insulating film. Accordingly, the high dielectric constant film is formed on the surface of the channel layer so that the interface state is not concentrated at a high density near the conduction band. Thereby, the problem of reducing the channel mobility caused by the interface state affecting the current flow can be solved. Accordingly, the channel mobility is improved. Accordingly, the device has a low on-state resistance. Preferably, a stacked structure of a high dielectric constant film and the oxide film formed on the surface of the high dielectric constant film provides the gate insulating film.

Accordingly, the interface state is not concentrated with high density near the conduction band at a portion of the gate insulating film abutting the channel layer. Furthermore, the oxide film is formed on the film with higher dielectric constant, so that a difference ΔEc measured from an edge of an energy level Ec of the silicon carbide can become larger. Accordingly, the energy threshold for generation of a gate leakage current is raised, so that the generation of the ground leakage current is prevented.

Preferably, the semiconductor substrate is a single crystal substrate of silicon carbide with the main surface inclined by between 10° and 20° from a (0001)-Si surface. Here, semiconductor substrates with various offset angles are manufactured, and a correlation between the offset angle and a density of defects caused by polishing is studied. It is confirmed that the polishing defects are significantly reduced when the offset angle is equal to or greater than 10°. Furthermore, it is confirmed that the surface roughness is reduced, so that the semiconductor substrate with small crystal defects is formed. 10 15 20 25 30 35 529 174 r 3 Accordingly, when the surface inclined by between 10° and 20° from the (0001)-Si surface is used, the interface state is reduced, compared with other surfaces. (OOÛÜ-SH/ïa" can Üfloat a" small amount of crystal defects. Consequently, the influence " of interface defects" on the current flow is reduced. Consequently, the channel mobility of the power MOSFET has been further improved.

Preferably, the semiconductor substrate is a single crystal substrate of silicon carbide with the main surface provided with at least two surfaces, one of which is inclined by between 10° and 20° from a (0001)-Si surface, and the other is the (0001)-Si surface. The single crystal substrate of silicon carbide with one surface inclined by between 10° and 20° from the (0001)-Si surface and the (0001)-Si surface as the main surface achieves a reduction of the interface state, compared with the single crystal substrate of silicon carbide with the other surface as the main surface. Consequently, the influence of the interface state on the current flow is significantly reduced. Consequently, the channel mobility of the power MOSFET is further improved. , Preferably, the surface inclined by between 10° and 20° relative to the (0001)-Si surface has an area larger than the area of (OOOU-Si surface. In this case, the above-mentioned influence is significantly reduced. Furthermore, as described in claim 6, a surface inclined by between 10° and 20° relative to the (0001)-Si surface is inclined towards a <11-20> direction. In this case, the above-mentioned influence is significantly reduced, so this is preferable.

In particular, the surface inclined by between 10° and 20° relative to the (0001) Si surface is a (11-2N) surface, where N satisfies the equation 17 s N s 38. In this case, the above-mentioned influence is significantly reduced, so this is preferable.

Furthermore, in a silicon carbide semiconductor substrate, the main surface of the substrate is a surface inclined by 10° or more with respect to a (0001)-Si surface. Accordingly, the surface has an excellent surface state and excellent smoothness with a suppression of defects, compared with a substrate with an offset of 8°, which is a silicon carbide semiconductor substrate with a main surface inclined by 8° with respect to the (0001)-Si surface. Accordingly, the surface has a homogeneous and stable surface state in the area of the substrate surface, so that the surface provides a surface for forming semiconductor devices. Here, preferably, an angle equal to or greater than 10° of the silicon carbide semiconductor substrate is in the range of 10° to 20°. Preferably, the angle equal to or greater than 10° is in the range of 13° to 20°. Furthermore, an epitaxial layer is formed on the main surface of the silicon carbide semiconductor substrate. In this case, the epitaxial layer has an excellent surface condition and further, generation of crystal defects can be prevented.

Furthermore, in a silicon carbide semiconductor substrate, the main surface of the substrate is composed of two surfaces, one of which is a (0001)-Si surface, and the other is a surface inclined by 10° or more with respect to the (0001)-Si surface. Accordingly, the surface has an excellent surface state and excellent smoothness with suppression of defects, compared with a substrate with an 8° offset, which is a silicon carbide semiconductor substrate with a main surface inclined by 8° with respect to the (0001)-Si surface. Accordingly, the surface has a homogeneous and stable surface state in an area of the substrate surface, so that the surface provides a surface for forming a semiconductor device.

It is preferred that, considering the area of the surface inclined by 10° or more with respect to the (0001)-Si surface and an area of the (0001)-Si surface, the area of the surface inclined by 10° or more from the (0001)-Si surface is larger than the area of the (0001)-Si surface of the silicon carbide semiconductor substrate. It is preferred that the surface inclined by 10° or more with respect to the (0001)-Si surface is an (11-2N) surface, where N satisfies the equation 17 s N s 38 in the silicon carbide semiconductor substrate. Furthermore, a method for producing a silicon carbide semiconductor substrate comprises the steps of: a first step of manufacturing a silicon carbide semiconductor substrate having a main surface inclined by 10° or more with respect to a (0001)-Si surface by a scribing process; a second step of mirror polishing the main surface of the silicon carbide semiconductor substrate; and a third step of forming an epitaxial layer on the main surface in such a way that the epitaxial layer grows epitaxially on the main surface of the silicon carbide semiconductor substrate.

Furthermore, a method for manufacturing a silicon carbide semiconductor substrate comprises the steps of: a first step of manufacturing a silicon carbide semiconductor substrate having a main surface consisting of at least two surfaces, one of which is a surface inclined by 10° or more relative to a (0001)-Si surface, and the other is the (0001)-Si surface, where two surfaces are formed in such a manner that the mirror-polished silicon carbide semiconductor substrate is preformed by heat treatment in a vacuum and in an atmosphere containing silicon, so that the two surfaces are formed on the main surface of the silicon carbide semiconductor substrate by a stepwise clustering process; and a second step of forming an epitaxial layer on the main surface in such a manner that the epitaxial layer grows epitaxially on the main surface of the silicon carbide semiconductor substrate.

Furthermore, a method for manufacturing a silicon carbide semiconductor substrate includes the steps of: a first step of manufacturing a semiconductor substrate having a main surface consisting of at least two surfaces, one of which is a surface inclined by 10° or more with respect to a (O001)-Si surface, and the other is the (0OO1)-Si surface, the two surfaces being formed in such a manner that the mirror-polished silicon carbide semiconductor substrate is manufactured by heat treatment in a vacuum, in a hydrogen gas atmosphere and a hydrogen chloride gas atmosphere, so that the two surfaces are formed on the main surface of the silicon carbide semiconductor substrate by a stepwise clustering process; and a second step of forming an epitaxial layer on the main surface in such a manner that the epitaxial layer grows epitaxially on the main surface of the silicon carbide semiconductor substrate. _ The above and other objects, features and advantages of the invention will become apparent upon reading the following detailed description with reference to the accompanying figures, in which: 10 15 20 25 30 35 5291174 S' Fig. 1 shows a cross-section of a power MOSFET according to a first embodiment of the invention.

Fig. 2A - 2C show cross-sectional views explaining a method for manufacturing the power MOSFET in Fig. 1. ' Fig. 3A - 3C show cross-sectional views explaining a method for manufacturing the power MOSFET in Fig. 1. i ' Fig. 4A - 4C show cross-sectional views explaining the method for manufacturing the power MOSFET in Fig. 1.

Fig. 5A shows an energy band structure in a case where a gate insulating film is composed of a high dielectric constant film, and Fig. 5B shows another energy band structure in another case where the gate insulating film is composed of an oxide film (i.e., SiO 2 ).

Fig. 6 shows an enlarged cross-sectional view illustrating a power MOSFET according to a second embodiment of the invention.

Fig. 7 shows an energy band structure near the gate insulating film in the power MOSFET shown in Fig. 6. Figs. 8A to 8C are cross-sectional views illustrating a method for manufacturing an N-type conductive semiconductor substrate according to a third embodiment of the invention.

Figs. 9A and 9B are cross-sectional views illustrating a method of manufacturing a power MOSFET according to a fourth embodiment of the invention. Figs. 10A to 10C are vertical cross-sectional views illustrating a method of manufacturing a silicon carbide semiconductor substrate according to a fifth embodiment of the invention.

Fig. 11 is a cross-sectional view illustrating a silicon carbide semiconductor substrate according to the fifth embodiment. j Fig. 12 is a graph illustrating a result of a shifted angle of the substrate and defect density caused by polishing, according to the fifth embodiment. j Figs. 13a and 13b are vertical cross-sectional views illustrating a method for manufacturing a silicon carbide semiconductor substrate according to a sixth embodiment of the invention. i Figs. 14A - 14F are vertical cross-sectional views explaining the method for manufacturing the silicon carbide semiconductor substrate according to the sixth embodiment.

Fig. 15 is a cross-sectional view explaining a structure of a substrate surface according to the sixth embodiment.

Fig. 16 is a cross-sectional view explaining the structure of the substrate surface according to the sixth embodiment.

Fig. 17 shows a cross-sectional view explaining the structure of the substrate surface, according to the sixth embodiment.

Fig. 18 is a cross-sectional view explaining the structure of the substrate surface according to the sixth embodiment. 10 15 20 25 30 35 i 529 174 r; Figs. 19A and 19B are cross-sectional views explaining the structure of the substrate surface according to the sixth embodiment. i Fig. 20 is a schematic view illustrating a cross-sectional view and a plan view of a semiconductor wafer according to a comparison of the fifth embodiment.

Fig. 21 is a cross-sectional view illustrating the semiconductor wafer according to the comparison of the fifth embodiment.

Fig. 22 is a cross-sectional view illustrating a MOS transistor according to the comparison of the fifth embodiment.

Fig. 23 is a cross-sectional view illustrating a diode according to a comparison of the fifth embodiment.

(First Embodiment) Fig. 1 is a cross-sectional view illustrating a normal N-channel gate MOSFET (i.e., a vertical power MOSFET) according to a fifth embodiment of the invention.

The device is preferably used for a rectifier of an inverter or an inverter of a vehicle. The design of the planar MOSFET is described with reference to Fig. 1 as follows. In particular, the device provides an insulated gate type field effect transistor for use at high power.

An N-type 1 conductive semiconductor substrate of silicon carbide has an upper surface as a main surface 1a, and a lower surface as a lower surface 1b, which is opposite to the main surface 1a. An N'-type conductive epitaxial layer (i.e., an N'-type conductive epitaxial layer) 2 is stacked on the main surface 1a of the N'-type conductive semiconductor substrate 1. The N'-type conductive epitaxial layer 2 is made of silicon carbide and has a dopant concentration lower than that of the substrate 1. Here, the top surface of the N'-type conductive semiconductor substrate 1 and the top surface of the N'-type conductive epitaxial layer 2 are a (0001)-Si surface. However, the top surface of the N'-type conductive semiconductor substrate 1 and the top surface of the N'-type conductive epitaxial layer may be a (11-20)-A surface. When the (0001)-Si surface is used, the lower surface density of the state is obtained and in addition, the crystal without screw dislocations is achieved.

A P-type conductive base region 3a and a P'-type conductive base region 3b are separately formed on a predetermined area on the surface portion of the N'-type conductive epitaxial layer 2. The P'-type conductive base regions 3a and 3b have a predetermined depth. Deep base regions 30a, 30b are formed in the base regions 3a, 3b. Each deep base region 30a, 30b has a portion that is partially thickened. The deep base region 30a, 30b is formed on a portion, SOFT! iflfè Övéfïappaf against the Nïtype conductive emitter region 4a, 4b. The thick part of the P type silicon carbide conductive base region 3a, 3b, the thick part where the deep base region 30a, 30b is formed, has an impurity concentration higher than that of a thin part where the deep base region 30a, 30b is not formed. The thickness of the N type 2 conductive epitaxial layer disposed under the deep base region 30a, 30b becomes thinner according to the deep base region 30a, 30b (i.e., the distance between the N type 1 conductive semiconductor substrate and the deep base region 30a, 30b becomes smaller).

Consequently, the field strength increases. Consequently, it is easy for an avalanche breakthrough to occur.

The N-type conductive emitter regions 4a, 4b are formed on predetermined areas of the surface portion of the P-type conductive base regions 3a and 3b, respectively. The N-type conductive emitter regions 4a, 4b are shallower than the base regions 3a, 3b. Furthermore, an N-type conductive surface channel layer 5 of silicon carbide extends on the surfaces of the N-type conductive epitaxial layer 2 and the P'-type conductive base region 3a, 3b and is arranged between the N-type conductive emitter region 4a and the N-type conductive emitter region 4b. Accordingly, the N-type conductive channel layer 5 is arranged on the surfaces of the P-type conductive base regions 38. 3b to provide a connection between the emitter regions 4a, 4b and the N'-type conductive epitaxial layer 2.

This N-type conductive surface channel layer 5 includes a Nitt/P conductive layer 53 with a low impurity concentration and a Nitt type conductive layer 5b with a high impurity concentration. The Nitt type conductive layer 5a is located on the surface portion of the P' type conductive base regions 3a, 3b. The Nitt type conductive layer 5b is arranged on the surface portion of the N' type conductive epitaxial layer 2. The N' type conductive channel layer 5 works with a portion for forming a channel on a device surface when the device is used. The surface portion of the P' type conductive base layers 3a, 3b in the N' type conductive channel layer 5 is composed of the N' type conductive layer 5a with a low impurity concentration, so that the impurity concentration of the portion to form a channel is substantially controlled. Furthermore, the surface portion of the N"-type conductive epitaxy layer 2 is composed of the N type conductive layer 5b with a high impurity concentration, so that the internal resistance of the N type conductive channel layer 5 is reduced. Accordingly, the resistance at the on state is reduced. A gate insulating film 7 is formed on the top of the surface channel layer 5 and the top of the N type conductive emitter regions 4a, 4b. Furthermore, a polycrystalline silicon gate electrode 8 is formed on the gate insulating film 7. The polycrystalline silicon gate electrode 8 is covered with an insulating film 9. The insulating film 9 is made of an LTO (Low Temperature Oxide) film. An emitter electrode 10 is formed on the insulating film 9, so that the emitter electrode 10 contacts the N* type conductive emitter regions 4a, j4b and the P type conductive base regions 3a, 3b. A collector electrode 11 has a backside electrode formed on the backside surface 1b of the N type conductive semiconductor substrate 1.

A J-FET part is provided with a portion of the N'-type conductive epitaxial layer 2 arranged between the P'-type conductive base regions 3a and 3b.

Now, a method for manufacturing a vertical power MOSFET shown in Fig. 1 will be explained with reference to Fig. 2A - Fig. 4G. i 10 15 20 25 30 35 i529 174 Q , (Method shown in Fig. 2A) First, an N-type conductive SiC substrate with 4H, 6H or 3C crystal structure is shown as the N-type conductive semiconductor substrate 1. For example, the N-type conductive semiconductor substrate 1 has a thickness of 400 µm and a main surface 1a of a (0001)-Si surface or a ~(11-20)-A surface. The N-type conductive epitaxial layer 2 is provided on the main surface 1a of the substrate 1 by an epitaxial growth method. The N-type conductive layer 2 has a thickness of 5 µm.

Accordingly, the N'-type conductive epitaxial layer 2 has the same crystallinity as the substrate 1 as a base, so that the N'-type conductive epitaxial layer 2 provides an N-type conductive 4H, 6H or 3C-SiC layer. (Process shown in Fig. 28) The LTO film 20 is arranged on a predetermined area of the N'-type conductive epitaxial layer 2. The LTO film 20 functions as a mask, so that Bi ions (or Al ions) are implanted.

Accordingly, the P type conductive base regions 3a, 3b have been formed. At this time, the ion implantation conditions are such that the temperature is 700°C, and the ion dose is 1 x 10" om? (Process shown in Fig. 2C) After the LTO film 20 is removed, the N ions are implanted from the top of the substrate 1, so that the surface channel layer 5 is formed on the surface part of the N type conductive epitaxial layer 2 and the surface part (i.e., the surface layer) of the P type conductive base regions 3a, 3b. At this time, the ion implantation conditions are such that the temperature is 700°C, and the ion dose is 1 x 1016 om". Accordingly, the surface channel layer 5 at the surface portion of the P'-type conductive base regions 3a, 3b is compensated, so that the conductive concentration of N-type impurities becomes a thin N-type conductive layer 5a. Furthermore, the conductive concentration of N-type impurities at the surface portion of the N"-type conductive epitaxial layer 2 becomes the thick N-type conductive layer 5b.

In order to form the normally-off type vertical power MOSFET, the above-mentioned ion implantation conditions are determined in such a way that the total size of the depletion region extension has an extension from the P-type conductive base regions 3a, 3b and the extension of the depletion region with its extension from the gate insulating film 7 is equal to or greater than a thickness of the surface channel layer 5.

The above-mentioned vertical power MOSFET that is normally off has been reliably compared to a MOSFET of the type that is normally on. This is because the normally off MOSFET can stop current flow through it, even when voltage is not applied to the gate electrode due to a fault.

(Process shown in Fig. 3A) An LTO film 21 is provided on a predetermined area of the surface channel layer 5. The LTO film 21 works as a mask for ion implantation of N ions. Accordingly, conductive emitter regions 4a, 4b of N type are formed. At this time, the conditions for ion implantation are such that the temperature is 700°C, and the dose of ions is 1 x 1015 cm-2.

(Process shown in Fig. 3B) _ After the LTO film 21 is removed, another LTO film 22 is formed on a predetermined area of the surface channel layer 5 by using a photoresist process. The LTO film 22 works as a mask for a reactive ion etching process. Accordingly, the surface channel layer 5 provided on the Pf-type silicon carbide conductive base regions 3a, 3b is partially etched or removed.

(Process shown in Fig. 3G) Further, the B ions are implanted by using the LTO film 22 as a mask, so that the deep base layers 30a, 30b are formed. Accordingly, a part of the base region 30a, 30b becomes thicker, so that the deep base layer 30a, 30b is provided. The deep base layer 30a, 30b is formed on a part that does not overlap the N type conductive emitter region 4a, 4b. The part of the P' type conductive base region 3a, 3b, where the deep base layer 30a, 30b is formed so that its thickness becomes larger, has an impurity concentration higher than that of the other part of the P type conductive base region 3a, 3b, where the deep base layer 30a; 30b is shaped so that its thickness becomes small.

(Process shown in Fig. 4A) After the LTO film 22 is removed, the HfO2 film is formed as a film with a high dielectric constant, so that the gate insulating film 7 is formed on the substrate. At the same time, for example, the HfO2 film is formed by a sputtering process with a substrate temperature of 500°C. After the sputtering, the substrate is processed by heat treatment in a D2 atmosphere, if necessary.

(Process shown in Fig. 4B) Then, the excess of the gate insulating film 7 is removed. Then, the insulating film 9 made of LTO is formed in order to cover the gate insulating film 7. At this time, the deposition temperature of LTO is set to be 425°C, and then, after the deposition, the substrate is cured at 1000°C.

(Process shown in Fig. 4C) _ The emitter electrode 10 and the collector electrode 11 are formed at room temperature by a metallic sputtering method. Further, after sputtering, the substrate is hardened at . 1000°C. In this way, the vertical power MOSFET shown in Fig. 1 is completed.

The operation (i.e., function) of the vertical power MOSFET is now described. The MOSFET operates in normal off-type accumulation mode. When no voltage is applied to the polycrystalline silicon gate electrode, a carrier is depleted in the surface channel layer 5 in the entire area of the surface channel layer 5 by a difference in electrostatic potential between the P type conductive base region 3a, 3b and the surface channel layer 5, and the difference in work function between the surface channel layer 5 AND the polycrystalline silicon gate electrode 8. When voltage is applied to the polycrystalline silicon gate electrode 8, the electric potential generated from the sum of the applied voltage from the external circuit and the difference in work function between the surface channel layer 5 and the polycrystalline silicon gate electrode 8 changes. In this way, the state of the channel is controlled. In particular, the work function of the polycrystalline silicon gate electrode 3 is defined as the first work function, and the work function of the P'-type conductive base region 3a, 3b is defined as the second work function, and the work function of the surface channel layer 5 is defined as the third work function. In this case, the first to third functions, the impurity concentration and the thickness of the surface channel layer 5 are determined in such a way that the N-type conductive carrier in the surface channel layer 5 is depleted by using the first to third work functions in When the device is in the off state, the depletion region in the surface channel layer 5 is formed by the electric field generated by the P"-type conductive base region 3a, 3b and the polycrystalline silicon gate electrode 8. When the positive bias is applied to the polycrystalline silicon gate electrode 8 in the above-mentioned state, the channel region is formed at the interface between the gate insulating film (i.e., SiO2) 7 and the surface channel layer 5. The channel region extends in a direction from the N-type conductive emitter region 4a, 4b to the N-type conductive drift region 2. In this way, the the device from off state to on state.

At this time, electrons flow from the N"-type conductive emitter region 4a, 4b to the N"-type conductive epitaxial layer 2 via the surface channel layer 5. When the electrons reach the N"-type conductive epitaxial layer 2 (i.e., the operating region), the electrons flow to the N"-type conductive semiconductor substrate 1 consisting of the collector region in the vertical direction.

Accordingly, the positive voltage is supplied to the gate electrode 8 so that the accumulation type channel is induced at the surface channel layer 5. Accordingly, the carrier flows between the emitter electrode 10 and the collector electrode 11. Accordingly, in the planar type MOSFET, the operating mode becomes the accumulation mode in which the channel is induced without reversing the conduction type of the layer to form the channel. Accordingly, the channel mobility of the device is increased so that the on-state resistance is reduced, as compared with a MOSFET with a reversal mode in which the channel is induced by reversing the conduction type of the layer to form the channel. In this embodiment, the gate insulating film 7 of the power MOSFET with the above-mentioned structure is made of HfO2 film as a high dielectric constant film. Here, FIG. 5A shows an energy band structure in a case where the gate insulating film 7 is made of a high dielectric constant film, and FIG. 5B shows an energy band structure in a case where the gate insulating film 7 is made of an oxide film (SiO 2 ) according to the prior art. Figs. 5A and 5B show the energy band at a cross-sectional portion shown as V-V in Fig. 1. 10 15 20 25 30 35 s29j174 When the gate insulating film 7 is made of the oxide film as shown in Fig. 5, the interface state of the negative charge is formed in the vicinity of the high-density conduction band.

Accordingly, the interface state affects the current flow, so that the channel mobility is reduced. On the other hand, when the gate insulating film 7 is made of the film with high dielectric constant, as shown in Fig. 5A, although the interface state exists, the interface state is not concentrated in the vicinity of the high-density conduction band. Accordingly, the interface state does not significantly affect the current flow, so that the channel mobility is not reduced.

As described above, in the power MOSFET according to this embodiment, the gate insulating film 7 is made of the film with high dielectric constant. Accordingly, the interface state cannot be concentrated in the vicinity of the high-density conduction band. Accordingly, the problem that the channel mobility is reduced under the influence of the interface state of the current flow has been reduced. In this way, the channel mobility has been improved.

(Modifications) In the above-mentioned first embodiment, although the HfO film has been used as the high dielectric constant film forming the gate insulating film 7, other films with high dielectric constant can be used for the gate insulating film 7. For example, an HfAlOx film can be used as the high dielectric constant film. In this case, the HfAlOx film is formed in the step shown in Fig. 4A of the first embodiment by, for example, the lVlO-CVD method. For example, the HfAlOx film is deposited at a temperature of 500°C in an O2 atmosphere. After deposition, the substrate is heat-treated at 700°C. In this way, the gate insulating film 7 is formed. Furthermore, the HfSiON film can be used as the high dielectric constant film. For example, the HfSiON film is formed by a reactive sputtering method. The substrate is then heat-treated at a temperature between 950°C and 1100°C in an atmosphere of N2 gas. In this way, the gate insulating film 7 is formed.

(Second embodiment) A second embodiment of the invention is described. In this embodiment, the construction of the gate insulating film 7 has been changed compared to the first embodiment.

Fig. 6 is a partially enlarged view illustrating a part of the gate insulating film 7 of the power MOSFET according to this embodiment. i _ As shown in this figure, in this embodiment, the insulating film 7 is composed of a stacked film, which is provided by stacking the high dielectric constant film 7a and the oxide film 7b. In particular, the gate insulating film 7 is formed in such a way that the high dielectric constant film 7a is formed on the surface of the surface channel layer 5, and then the oxide film 7b is formed on the surface of the high dielectric constant film 7a. V Fig. 7 shows an energy band structure in the above-mentioned case. As shown in this figure, in the high dielectric constant film 7a formed on the surface of the surface channel layer 5 made of silicon carbide, the interface state is not concentrated near the high-density conduction band. 10 15 20 25 30 1529 174 :fä However, when the gate insulating film 7 is formed of only the high dielectric constant film, the gate leakage current may flow to a large extent during the application of a high gate voltage at a high temperature, compared with the case where the gate insulating film 7 is made of only the oxide film. This is because the difference ΔEc between the edge Ec of the energy level of silicon carbide on the conduction band side and the energy level Ec of the high dielectric constant film becomes smaller than the difference ΔEc between the energy level Ec of silicon carbide and the energy level Ec of the oxide film. Accordingly, the energy barrier is easily exceeded, so that the gate leakage current flows to a large extent. , Accordingly, in this embodiment, a part of the gate insulating film 7, which contacts the surface channel layer 5, is composed of the high dielectric constant film 7a. Furthermore, the oxide film 7b is formed on the surface of the high dielectric constant film 7a. Accordingly, the interface state at the portion of the gate insulating film 7 that contacts the surface channel layer 5 is not concentrated near the high-density conduction band. Furthermore, since the oxide film 7b is formed on the high dielectric constant film 7a, the difference ΔEc from the edge of the silicon carbide energy level becomes higher.

Accordingly, the energy barrier required to generate the gate leakage current becomes higher, and consequently the generation of the gate leakage current is prevented. The MOSFET of the above-mentioned structure can be manufactured by a method obtained by adding a known oxide film forming method to the manufacturing method described in the first embodiment. For example, the high dielectric constant film 7a made of 1-1fAlOx film is formed at 500°C in an O gas atmosphere by the MO-CVD method. Then, the substrate is cured at 700°C. Further, the oxide film 7b is deposited on the surface of the high dielectric constant film 7a by the CVD method. Accordingly, the gate insulating film 7 is formed. Furthermore, the HfSiON film can be used as the high dielectric constant film. For example, the HfSiDN film is formed by a reactive sputtering method. Then, the substrate is processed by heat treatment at a temperature between 950°C and 1100°C in an N2 gas atmosphere, so that the gate insulating film 7 is formed.

(Third Embodiment) A third embodiment of the invention is explained below. This embodiment is achieved by changing the surface direction of the N type 1 conductive semiconductor substrate in the first embodiment. In this embodiment, the N type 1 conductive semiconductor substrate is processed with the main surface inclined by between 10° and 20° from the (0001) Si surface. The method for manufacturing this N type 1 conductive semiconductor substrate is explained with reference to the manufacturing process diagram shown in Figs. 8A - 8C. 10 15 20 25 30 35 529 174' /o id="p-61"

[0061] First, as shown in Fig. 8A, a 4H-Sic single crystal block with the (0001)-Si surface is fabricated.

Then, as shown in Fig. 8B, the block is cut using a wire saw at a surface inclined by 10° to 20° relative to the (0001)-Si surface. At this time, the surface inclined by 10° to 20° relative to the (0001)-Si surface has high stability, so that a mirror surface without polishing defects can be obtained. In this way, the N'-type conductive semiconductor substrate 1 with the main surface inclined by between 10° and 20° with respect to the (oool) surface can be manufactured. Then, as shown in Fig. 8G, the N'-type conductive epitaxial layer 2 is caused to epitaxially grow on the main surface of the N'-type conductive semiconductor substrate 1 by using CVD equipment or the like. Then, processes similar to those shown in Figs. 2A - 3C are carried out. In this way, the power MOSFET described first is manufactured.

The surface inclined by between 10° and 20° with respect to the (OOO1)-Si surface can reduce the interface state, compared with other surfaces. Accordingly, the influence of the interface state on the current flow is significantly reduced. In this way, the channel mobility of the power lvlosFET can be significantly improved. ' Here, as described in the first embodiment, when the Nïtype 1 conductive semiconductor substrate with the surface inclined by between 10° and 20° with respect to the (OOO1)-Si surface is used, it is preferable that the surface is inclined along a <11-20> direction. Experiments have confirmed that the interface state of the surface inclined along the <11-20> direction becomes lower. Accordingly, the surface is tilted by between 10° and 20° with respect to the (0001)-Si surface, the surface is tilted along the <11-20> direction, so that the interface state becomes smaller. In this way, the channel mobility of the power MOSFET is improved in a more effective manner.

When the N'-type conductive semiconductor substrate 1 with the surface inclined by between 10° and 20° with respect to the (0001) Si surface is used, the surface is preferably an (11-2N) surface, where N satisfies the equation 17 s N s 38. Experiments have confirmed that the interface state of the (11-2N) surface, where N satisfies an equation 17 s N s 38, is reduced. Accordingly, when this 'surface is used, the channel mobility of the power MOSFET can be effectively improved.

(Fourth Embodiment) A fourth embodiment of the invention will be explained below. This embodiment, similar to the third embodiment, is obtained by changing the surface direction of the N'-type conductive semiconductor substrate 1 in the first or second embodiment.

Fig. 9A and 9B show a manufacturing method for manufacturing the power MOSFET according to this embodiment. In this embodiment, as shown in Fig. 9A, a shifted substrate is manufactured as the N'-type conductive semiconductor substrate 1. The shifted substrate has a shift of 8° with respect to the (0001) Si surface. 10 15 20 25 30 35 1529 114 11-1 Then, the LTO film is formed on the surface of the N"-type conductive semiconductor substrate 1. Then, the LTO film is removed. Furthermore, the surface of the N'-type conductive semiconductor substrate 1 is cleaned. Then, a silicon carbide layer with a thickness of, for example, 5 nm is applied to the surface of the N'-type conductive semiconductor substrate 1. Then, a vacuum chamber is heated so that the temperature of the N'-type conductive semiconductor substrate 1 is in a range between 500°C and 1100°C. Preferably, the temperature is constant at 1500°C. This high heat treatment produces a step cluster applied to the surface of the N'-type conductive semiconductor substrate 1. In this way, two surfaces are obtained, where one is the (OOO1)-Si surface and the other is the surface tilted by between 10° and 20° relative to the (OOOU-Si surface.

At this time, the area of the surface inclined by 10° to 20° with respect to the (0001)-Si surface becomes larger than the area of the (0001)-Si surface. The ratio of the area ratio can be controlled by temperature control of the heat treatment process. For example, two or more heat treatment processes, one of which is carried out at 1050°C and the other is carried out at 950°C, can be combined so that the ratio of the area ratio can be controlled. The (0001)-Si surface and the surface inclined by 10° to 20° with respect to the (0001)-Si surface are formed as the main surface 1a of the N'-type conductive semiconductor substrate 1. Then, the N'-type conductive semiconductor substrate 1 with these two surfaces is used, so that the power MOSFET having the structure described in the first embodiment is manufactured.

Then, as shown in Fig. 9B, the N'-type conductive epitaxial layer 2 is epitaxially grown on the main surface of the N'-type conductive semiconductor substrate 1 by using CVD equipment or the like. Then, processes similar to the processes described in Figs. 2A - 3C are carried out. In this way, the power MOSFET described in the first embodiment is completed. Then, the N'-type conductive epitaxial layer 2 is epitaxially grown on the main surface of the N'-type conductive semiconductor substrate 1 by using CVD equipment or the like. Then, processes similar to the processes described in Figs. 2A - 3C are carried out. In this way, the power MOSFET according to the first embodiment is completed.

It is confirmed that a single crystal silicon carbide substrate with the main surface of the (0001)-Si surface and the surface inclined by between 10° and 20° relative to this surface can reduce the interface state, compared to single crystal silicon carbide substrates with the main surface of other surfaces.

Accordingly, the influence of the interface state on the current flow can be significantly reduced. In this way, the channel mobility of the power MOSFET can be significantly improved. _ Furthermore, the area of the surface inclined by between 10° and 20° relative to the (0001) Si surface is larger than the area of the (0001) surface; and accordingly, the above-mentioned effect can be effectively achieved. 10 15 20 25 30 35 529 174 IÉ* (Modifications) In the above embodiments, the surface channel layer 5 is formed in such a way that the ions are implanted directly onto the surface portion of the N"-type conductive silicon carbide epitaxial layer 2 and onto the surface portion (i.e., the surface layer) of the P"-type conductive silicon carbide base regions 3a, 3b. The above embodiments can be applied to a power MOSFET manufactured in such a way that the N"-type conductive surface channel layer 5 is caused to epitaxially grow on these surface portions.

Furthermore, in the above embodiments, the power MOSFET with the first conduction type as N conduction type and the second conduction type as P conduction type is described as an example. However, this is an example; and accordingly, the invention can be applied to a P-type channel power MOSFET obtained by reversing the conduction type in each part. v g Here, when a crystal direction is defined, a dash (-) should usually be added to a number.

However, there are limitations of expression arising from a data filing system. Accordingly, in this description, a dash is added in front of the number. I i (Fifth Embodiment) The inventors have preliminarily studied an SiC substrate. An 8° offset surface of the SiC substrate is not a stable surface. Accordingly, as shown in Figs. 20 and 21, a defect caused by polishing is easily generated when a semiconductor wafer 100 is manufactured. Accordingly, it is difficult to form a homogeneous surface state in a semiconductor wafer surface. Accordingly, for example, as shown in Fig. 22, a device failure occurs at a part of a substrate 110 with a poor surface state, such as a defect 130 caused by polishing in a MOS transistor. The MOS transistor includes an emitter region 111, a collector region 112, a gate oxide film 113, and a gate electrode 114 formed on a surface portion of the substrate 110. Specifically, when the defect 130 caused by polishing exists on the surface of the substrate 110, slight current leakage occurs at the gate oxide film 113.

Furthermore, when a device is formed on the SiC substrate after epitaxial growth, as shown in Fig. 23 for example, a crystal defect 131 caused by the defect 130 caused by polishing on the surface of the substrate 120 may occur in the epitaxial layer 121 of the device (i.e., the diode), so that the current leakage (i.e., a PN junction leakage) easily occurs. The device has the epitaxial layer 121 on the substrate 120, where a P-type conductive region 122 is formed, and an anode electrode 123 and a cathode electrode 124. In view of the above problems, a silicon carbide semiconductor substrate and a method for manufacturing the substrate are described with reference to Figs. 10A to 10C.

As shown in Fig. 10A, a 4H-SiC single crystal substrate 501 is manufactured. The surface inclined by between 10° and 20° with respect to the (0001)-Si surface of the 4H-SiC single crystal substrate 501 is cut out from the 4H-SiC single crystal substrate 501 by using a wire saw. In particular, the substrate 501 is cut with the wire saw at a pair of lines shown as L1 and L2 in Fig. 10A. This results in the formation of the substrate 1 shown in Fig. 10B. 10 15 20 25 30 35 i 529 174 /é Further, the surface of the substrate 1 is mirror polished by a chemical mechanical planing method with a diamond abrasive. At this time, the surface of the substrate 1 inclined by between 10° and 20° with respect to the (0001)-Si surface becomes a finished mirror surface without defects caused by polishing, so that the stability of the surface becomes higher. _ Then, as shown in Fig. 100, an epitaxial film is grown on the main surface of the substrate 1 by using CVD equipment, so that the epitaxial layer 2 is formed on the substrate 1.

By using this substrate, the vertical power MOS transistor is formed, as shown in Fig. 11. In particular, the N type conductive region 2 is epitaxially grown on the N type conductive SiC substrate 1. The P' type conductive region 3a, 3b is formed on the surface portion of the main surface of the substrate (i.e., the upper surface of the N" type conductive region 2), and then the N type conductive emitter region 4a, 4b is formed on the surface portion of the P type conductive region 3a, 3b. Furthermore, a low concentration layer as a N type conductive surface channel layer 505 is formed in the channel region of the surface portion of the N type conductive region 2.

The ground electrode 8 is formed on the low concentration layer 505 via the gate oxide film (i.e., usually the gate insulating film) 7. The emitter electrode 10 is formed on the gate electrode 8 via the insulating film 9, so that the emitter electrode 10 contacts the N-type conductive emitter region 4a, 4b and the P-type conductive region 3a, 3b. On the other hand, the collector electrode 11 is formed on the lower surface (i.e., bottom) of the N-type conductive SiC substrate.

Fig. 12 shows a result of measuring a relationship between the offset angle and the defect density caused by polishing. Here, various substrates with different offset angles are prepared. The horizontal axis in Fig. 12 represents the offset angle of the substrate, and the vertical axis in Fig. 12 represents the defect density caused by polishing. As shown in Fig. 12, when the offset angle becomes equal to or greater than 10°, the defect caused by polishing is rapidly reduced. Furthermore, when the offset angle becomes equal to or greater than 10°, the roughness of the substrate surface is reduced. Furthermore, when the offset angle becomes equal to or greater than 13°, the defect caused by polishing disappears.

Accordingly, the main surface of the silicon carbide semiconductor substrate is designed to be the surface inclined by 10° or more with respect to the (0001)-Si surface, so that the main surface becomes stable. In particular, it is preferred that the main surface is designed to be the surface inclined by between 10° and 20° with respect to the (0001)-Si' surface. In particular, the main surface is designed to be the surface inclined by between 13° and 20° with respect to the (0001)-Si surface. By using this surface, the epitaxial layer is formed with a small amount of crystal defects. In particular, when the epitaxial substrate is manufactured, the defect caused by polishing can be reduced (i.e., the roughness is reduced) so that a properly controlled surface state is formed before the epitaxial film is grown. Accordingly, the epitaxial film is made to grow under the condition that the generation of crystal defects is limited. That is, the production rate of the device is improved (i.e., the generation rate of chip defects in the semiconductor wafer is reduced).

The vertical power MOS transistor shown in Fig. 11 is formed by using the substrate 1 shown in Fig. 10C. However, the MOS transistor shown in Fig. 22 can be formed by using the substrate shown in Fig. 10B. Furthermore, the block to be cut into the substrate may be a 6H-SiC crystal instead of a 4H-SiC crystal. As described above, this embodiment has the following features. (1) As shown in Fig. 10B, the silicon carbide semiconductor substrate 1 has its main surface inclined by 10° or more with respect to the (0001)-Si surface. Accordingly, the surface has excellent surface condition and smoothness with suppression of a defect, compared with an 8° offset substrate, which is a silicon carbide semiconductor substrate with a main surface inclined by 8° with respect to the (0001)-Si surface. Accordingly, the surface has a homogeneous and stable surface condition in an area of a substrate surface, so that the surface provides a surface for forming a semiconductor device.

Preferably, the angle is equal to or greater than 10° in a range between 10° and 20°. Most preferably, the angle is equal to or greater than 10° in a range between 13° and 20°.

Furthermore, the angle equal to or greater than 10° is in a range of 16° to 20° with respect to the (0001)-Si surface. Furthermore, the surface inclined by 10° or more with respect to the (OOO,1)-Si surface in the silicon carbide semiconductor substrate is an (11-2N) surface, where N satisfies the equation 17 s N s 38. (ll) As shown in Fig. 10C, the epitaxial layer 2 is formed on the main surface 1a of the silicon carbide semiconductor substrate 1a, so that the epitaxial substrate is obtained. Accordingly, the epitaxial layer 2 has an excellent surface state, and further, generation of crystal defect can be prevented. (lll) As shown in Fig. 10A and 10B, a method for manufacturing a silicon carbide semiconductor substrate includes the steps of: the first step of manufacturing the silicon carbide semiconductor substrate 1 with the main surface inclined by 10° or more relative to the (0001)-Si surface by a scribing process; the second step of mirror polishing the main surface 1a of the silicon carbide semiconductor substrate 1; and the third step of bonding the epitaxial layer 2 on the main surface 1a in such a way that the epitaxial layer is caused to grow epitaxially on the main surface 1a of the silicon carbide semiconductor substrate 1. The method provides the silicon carbide semiconductor substrate described in (III).

Here, the angle is equal to or greater than 10° in a range between 10° and 20°. Preferably, the angle is equal to or greater than 10° in a range between 13° and 20°. Furthermore, the angle is equal to or greater than 10° in a range between 16° and 20° relative to the (0001)-Si surface.

(Sixth Embodiment) Now, a sixth embodiment will be described as follows. A silicon carbide semiconductor substrate and a method for manufacturing the same will be explained with reference to Figs. 13A and 13B.

As shown in Fig. 13A, the main surface of the silicon carbide semiconductor substrate 1 consists of at least two surfaces, one of which is the (0001)-Si surface, and the other is a surface inclined by 10° or more relative to the (0001)-Si surface. Preferably, the main surface consists of at least two surfaces, one of which is the (0001)-Si surface, and the other is a surface inclined by between 10° and 20° relative to the (0001)-Si surface. Preferably, the main surface consists of at least two surfaces, one of which is the (0001)-Si surface, and the other is a surface inclined by between 13° and 20° relative to the (0001)-Si surface. This can be derived from the basis of the relationship between the "defect density caused by polishing" and the angle relative to the (0001)-Si surface, as described above with reference to Fig. 12.

As shown in Fig. 13B, the epitaxial layer 2 is formed on the main surface of the silicon carbide semiconductor substrate 1 as a single crystal. In particular, as shown in Fig. 13A, the substrate 1 is manufactured with the substrate surface on which two surfaces of the (0001)-Si surface and the surface inclined by 10° or more with respect to the (0001)-Si surface are formed. The epitaxial layer 2 is grown on the substrate 1 using the DVD equipment. .

To produce the substrate shown in Fig. 13A, the following process is performed.

As shown in Figs. 14A - 14F, the SiC substrate 601 is manufactured on an 8° offset substrate. The substrate 601 has its main surface inclined at a predetermined angle 1 with respect to the (0001) Si surface. As shown in Fig. 14B, the surface of the substrate 601 has been polished to be a mirror surface. At this time, as shown in Fig. 21, a defect caused by polishing remains on the surface portion of the substrate 601 (i.e., the surface portion shown as A1 in Fig. 14B). Further, as shown in Fig. 14C, an LTO film 620 is formed on the surface of the substrate 601. Then, the LTO film 620 is removed, so that the substrate has a state as shown in Fig. 14D. Then, the surface of the SiC substrate 601 is cleaned. , V Further, as shown in Fig. 14E, a Si layer 630 having a thickness of about 5 nm is deposited on the surface of the SiC substrate 601 by an evaporation process and the like. Successively, an ultra-high vacuum chamber is heated so that the temperature of the SiC substrate 601 becomes constant in a range between 500°C and 1500°C (i.e., the temperature of the substrate 601 becomes high- v re). At the same time, the temperature is preferably set to be 1050°C. This temperature increase provides a step clustering on the substrate surface, as shown in Fig. 14F. _ The details thereof are described below. As shown in Fig. 15, which is obtained by enlarging the substrate surface in Fig. 14E (i.e., a part shown as A2), the substrate shifted by 8° has the surface structure shown in Fig. 16. The substrate in this state is subjected to high temperature treatment so that step clustering is formed as shown in Fig. 17, which is obtained by enlarging the substrate surface in Fig. 14F (i.e., a part shown as A3). In this way, the substrate surface has the structure shown in Fig. 18. Accordingly, the step clustering is formed with a ratio of tan"(b/a) s 10° with respect to the (0001)-Si surface. Accordingly, a new surface of the step clustering is inclined by 10° or more with respect to the (0001)-Si surface. .

At this time, the area of the (0001)-Si surface and the area of the surface inclined by 10° or more with respect to the (0001)-Si surface are determined as follows. As shown in Fig. 19B, it is preferable that the area of the surface inclined by 10° or more with respect to the (0001)-Si surface is larger than the area of the (0001)-Si surface, compared with a case where the area of the surface inclined by 10° or more with respect to the (0001)-Si surface is smaller than the area of the (0001)-Si surface, as shown in Fig. 19A.

Furthermore, when the step cluster is formed, the surface structure is restructured so that the defect caused by the polishing disappears. In this way, the surface becomes stable. As shown in Fig. 14E, the Si layer 630 is applied to the substrate surface before the substrate temperature becomes higher. This is because the substrate surface is protected from carbonization when the substrate temperature increases in the ultra-high vacuum. Although the method of applying Si to the surface is used, other methods can be used, such as increasing the vapor pressure of silicon near the surface of a silicon flux sample and the like. A method can be used as long as the substrate is processed by heat treatment in vacuum and atmosphere containing silicon. Accordingly, as shown in Fig. 13A, the substrate is obtained with the surface consisting of two surfaces. One surface is the (0001)-Si surface and the other is the surface inclined by 10° or more with respect to (0001)-Si surface. In particular, the substrate with the well-controlled surface state is obtained before the epitaxial growth. Then, the vertical power MOS transistor shown in Fig. 11 is formed by using the substrate shown in Fig. 13B. However, the MOS transistor in Fig. 22 is formed by using the substrate shown in Fig. 13A. Preferably, the substrate 601 in Fig. 14A is made of 4H or 6H single crystal.

Accordingly, this embodiment has the following characteristics. (IV) As shown in Fig. 13A, the main surface of the silicon carbide semiconductor substrate 1 i consists of at least two surfaces, one of which is the (0001)-Si surface, and the other is the surface inclined by 10° or more with respect to the (0001)-Si surface. Accordingly, the surface has an excellent surface condition and excellent smoothness with suppression of defects, compared with an 8°-offset substrate, which is a silicon carbide semiconductor substrate with a main surface inclined by 8° with respect to the (0001)-Si surface. Accordingly, the surface has excellent surface condition. In particular, the surface has a homogeneous and stable surface condition in an area of a substrate surface, so that the surface provides a surface for forming a semiconductor device.

Here, the angle is equal to or greater than 10° in a range between 10° and 20°. Preferably, the angle is equal to or greater than 10° in a range between 13° and 20°. Even more preferably, the angle is equal to or greater than 10° in a range between 16° and 20° relative to the (0001)-Si surface.

Preferably, regarding an area of the surface inclined by 10° or more with respect to the (0001)-Si surface and an area of the (00O1)-Si surface, the area of the surface inclined by 10° or more with respect to the (0001)-Si surface is larger than the area of the (0001)-Si surface of the silicon carbide semiconductor substrate. j Furthermore, the surface inclined by 10° or more with respect to the (0001)-Si surface of the silicon carbide semiconductor substrate is an (11-2N) surface, where N satisfies the equation 17 s N s 38.

(V) As shown in Fig. 13B, the epitaxial layer 2 is formed on the main surface of the single crystal silicon carbide semiconductor substrate 1, so that the epitaxial substrate is obtained.

(Vl) As shown in Figs. 14A - 14F, a method for manufacturing a silicon carbide semiconductor substrate includes the steps of: a first step of manufacturing a silicon carbide semiconductor substrate having a main surface consisting of at least two surfaces, one of which is a surface inclined by 10° or more with respect to a (0001)-Si surface, and the other is the (0001)-Si surface, the two surfaces having been formed in such a manner that the mirror-polished silicon carbide semiconductor substrate 601 is obtained by heat treatment in a vacuum and an atmosphere containing silicon, so that two surfaces are formed on the main surface of the silicon carbide semiconductor substrate 601 by a step-clustering process; and a method for forming an epitaxial layer 2 on a main surface in such a way that the epitaxial layer 2 is caused to grow epitaxially on the main surface of the silicon carbide semiconductor substrate 1. In this way, the silicon carbide semiconductor substrate described in (V) is obtained.

Preferably, the angle is equal to or greater than 10° in a range between 10° and 20°. More preferably, the angle is equal to or greater than 10° in a range between 13° and 20°. Most preferably, the angle is equal to or greater than 10° in a range between 16° and 20° relative to the (0001)-Si surface. In the sixth embodiment described above, although the mirror-polished silicon carbide semiconductor substrate is processed by heat treatment in vacuum and an atmosphere comprising silicon, instead, the mirror-polished silicon carbide semiconductor substrate may be processed by heat treatment in vacuum, hydrogen atmosphere and hydrogen chloride atmosphere. In particular, the substrate is processed by heat treatment at a temperature in a range between 1300°C and 1500°C with flowing hydrogen gas (i.e. H 2 ) and hydrogen chloride gas (i.e. HCl, comprising 0.1 - 10% HCl gas).

Accordingly, the silicon carbide semiconductor substrate is formed with the main surface consisting of at least two surfaces. The two surfaces are the (0001)-Si surface, and the surface inclined by 10° or more with respect to the (0001)-Si surface, and the two surfaces are provided by step clustering on the main surface of the silicon carbide semiconductor substrate. The other details are the same as a case where the mirror-polished silicon carbide semiconductor substrate is processed by heat treatment in a vacuum in 529,174 eel! and an atmosphere containing silicon (i.e., the other details are the same as those listed above from (IV) to (Vl).

Such changes and modifications as are considered to be within the scope of the invention are defined by the appended claims.

Claims (20)

10 15 20 25 30 35 i 529: lit 174 A silicon carbide semiconductor substrate comprising: - _. a major surface (1a) of the substrate (1) inclined relative to a (0001) -Si surface having an angle equal to or greater than 10 °, wherein the angle equal to or greater than 10 ° is in a range between 10 ° and 20 °, and the substrate (1) provides a power MOS transistor. A silicon carbide semiconductor substrate according to claim 1, wherein the angle equal to or greater than 10 ° is in a range between 16 ° and 20 °. The silicon carbide semiconductor substrate according to claim 1, wherein the angle is equal to or greater than 10 °. is in a range between 13 ° and 20 °. The silicon carbide semiconductor substrate according to any one of claims 1 to 3, further comprising: an epitaxial layer (2) applied to the main surface (1a) of the silicon carbide semiconductor substrate (1) - The silicon carbide semiconductor substrate according to claim 1, wherein the surface inclined relative to a (0001) -Si surface at an angle equal to or greater than 10 ° is a (11-2N) surface, where N satisfies the equation 17 ss 38. A silicon carbide semiconductor substrate comprising: a major surface (1a) of the substrate (1) comprising two surfaces, one of which is a (O001) -Si surface and the other is a surface inclined relative to a (OOOU-Si surface at an angle equal to or greater than 10 ° i A silicon carbide semiconductor substrate according to claim 6, wherein the angle equal to or greater than 10 ° is in a range between 10 ° and 20 °. A silicon carbide semiconductor substrate according to claim 6, wherein the angle equal to or greater than 10 ° is in a range between 13 ° and 20 °. A silicon carbide semiconductor substrate according to any one of claims 6 to 8, further comprising: an epitaxial layer (2) applied to the main surface (1a) of the silicon carbide semiconductor substrate (1) - A silicon carbide semiconductor substrate according to any one of claims 6 to 9, wherein the surface is inclined relative to a (00O1) -Si surface having an angle equal to or greater than 10 ° has an area greater than an area of the (0001) -Si surface. A silicon carbide semiconductor substrate according to any one of claims 6 to 10, wherein the surface is inclined relative to a (OOOU-Si surface with an angle equal to or greater than 10 ° is one (11-2N surface), where N satisfies the equation 17 s N s 38. A method of manufacturing a semiconductor substrate of silicon carbide (1), the method comprising the step of: - manufacturing a semiconductor substrate of silicon carbide (1) having a main surface (1a) inclined relative to a (1001) -Si surface having an angle equal to or greater than 10 ° by a cutting method, in the mirror polishing of the major surface (1a) of the silicon carbide semiconductor substrate (1); and applying an epitaxial layer (2) in an epitaxial manner to the main surface (1a), wherein the angle equal to or greater than 10 ° is in a range between 10 ° and 20 °, and the substrate (1) provides a power MOS transistor . ' A method of manufacturing the silicon carbide semiconductor device according to claim 12, wherein the angle equal to or greater than 10 ° is in a range between 16 ° and 20 °. A method of manufacturing the silicon carbide semiconductor device according to claim 12, wherein the angle equal to or greater than 10 ° is in a range between 13 ° and 20 °. A method of manufacturing a silicon carbide semiconductor substrate (1), the method comprising the steps of: manufacturing a silicon carbide semiconductor substrate (1) having a main surface (1a) comprising at least two surfaces, one of which is a surface inclined relative to one (0001) -Si surface having an angle equal to or greater than 10 ° and the other being (0001) -Si surface; and applying an epitaxial layer (2) in an epitaxial manner to the main surface (1a), wherein the step of manufacturing the silicon carbide semiconductor device (1) comprises the steps of: mirror polishing the main surface (1a) of the silicon carbide semiconductor substrate (1): and heating the semiconductor carbide substrate of (1) in vacuum and an atmosphere comprising silicon, so that the two surfaces are formed on the main surface (1a) of the semiconductor substrate of silicon carbide (1) by a step cloning process. i 10 15 20 i 529 174 '_29 A method according to claim 15, wherein the angle equal to or greater than 10 ° is in a range between 10 ° and 20 °. A method according to claim 15 or 16, wherein the angle equal to or greater than 10 ° is in a range between 13 ° and 20 °. A method of manufacturing silicon carbide semiconductor substrates (1), the method comprising the steps of: V manufacturing a silicon carbide semiconductor substrate (1) having a major surface (1a) comprising at least two surfaces, one of which is a surface inclined relative to a (0001) -Si surface with an angle equal to or greater than 10 °, and the other is (0001) -Si surface; and applying an epitaxial layer (2) in an epitaxial manner to the main surface (1a), the step of manufacturing the semiconductor substrate of silicon carbide (1) comprising the steps of: mirror polishing the main surface (1a) of the silicon carbide semiconductor device (1); and heating the semiconductor substrate of silicon carbide (1) in vacuum, hydrogen atmosphere and hydrogen chloride gas atmosphere so that the two surfaces are formed on the main surface (1a) of the semiconductor substrate of silicon carbide (1) by a step cloning process. A method according to claim 18, wherein the angle equal to or greater than 10 ° is in the range between 10 ° and 20 °. A method according to claim 18 or 19, wherein the angle equal to or greater than 10 ° is in the range between 13 ° and 20 °.