RU2842329C1 - Digital-analogue converter based on delta-sigma - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to digital-to-analogue converters of integrating type with sigma-delta-architecture. Disclosed is a delta sigma-based digital-to-analogue converter, which includes: first 1, second 2, third 3 and fourth 4 integrators, first adder-subtractor 5, adder 6, adder 7, adder 8, shifters 9, 10, 11, 12, 13, 14, 15 and 16, digital-to- analogue converter also includes sign determiner unit 17 and delay element 18.

EFFECT: reduction of high-frequency noise in the DAC frequency characteristic, namely reduction of high-frequency interference in the range of useful frequencies and reduction of the DAC resonance mode risk.

1 cl, 4 dwg

Description

Field of technology

The invention relates to special-purpose electronic equipment, specifically to analog-to-digital converters of the integrating type with sigma-delta architecture. This proposed digital-to-analog converter (hereinafter referred to as DAC) can be used in various fields - in particular - digital-signal processors, conversion of digital signals into analog ones, in this case - into a bit sequence that can be directly fed to a speaker, for example, via an H-bridge.

State of the art

Sigma-delta and delta-sigma modulators are known and are described in the following sources:

1. "Continuous-time delta-sigma modulators for high-speed A/D conversion", James A. Cherry, Kluwer Academic Publishers, 1999.

2. "Architecture of a high-frequency delta-sigma modulator based on a fully digital gigahertz transmitter", Subbotin O.D., Journal of Radioelectronics, eISSN: 1684-1719, 2016.

3. "Sigma-delta analog-to-digital converter", Bartashev S.V. et al. Patent number: RU 2145.149 C1, 2000.

4. "Delta-sigma digital-to-analog converter", Lully R. et al. Patent number: RU 2551812 C2, 2015.

In this spectrum of known DACs and ADCs, the architecture is based on sigma-delta or delta-sigma. Basically, these architectures are built on feedback only. This is explained by the fact that with an increase in the order of sigma-delta or delta-sigma, the device can quickly go into resonant mode.

The closest technical solution is the delta-sigma (DAC), described in "Top-down design of high-performance sigma-delta modulators", Fernando Medeiro, 1999, Kluwer Academic Publishers, page 121, with a cascaded 2-1-1 architecture. This delta-sigma includes four integrators connected in a cascaded scheme. The disadvantage of the solution is that such an architecture does not provide a stable transient response with reduced noise levels in the useful frequency range (e.g. audio).

Disclosure of invention

The technical problem that the claimed invention is aimed at solving is improving the quality characteristics of the converter.

The technical result of the claimed solution is a significant reduction in high-frequency noise in the frequency response of the DAC, namely a reduction in high-frequency interference in the range of useful frequencies and a reduction in the risk of the DAC resonant mode.

The technical result is achieved in that a digital-to-analog converter based on delta-sigma is proposed, including a first, second, third, fourth, fifth, sixth, seventh and eighth shifters, an adder-subtractor, the first, second and third adders, a delay element and a sign determiner unit, wherein the input of the converter is connected to the first input of the adder-subtractor, the output of which is connected to the input of the first integrator, the output of which is connected to the input of the first shifter, the output of the first shifter is connected to the input of the second integrator, the output of which is connected to the inputs of the second and third shifters, the output of the second shifter is connected to the first input of the first adder, and the output of the third shifter is connected to the input of the third integrator, the second input of the first adder is connected to the output of the second adder, and the output is connected to the input of the fifth shifter, the output of which is connected to the first input of the third adder, the output of the third integrator is connected to the fourth and sixth shifters, the output of the fourth shifter is connected to the first input of the second adder, the second input of which is connected to the output of the seventh shifter, the input of which is connected to the output of the fourth integrator, the input of which is connected to the output of the sixth shifter, the input of the eighth shifter is connected to the output of the first integrator and the output to the input of the third adder, the output of the third adder is connected to the input of the sign determiner block, the output of which is the output of the converter and is connected to the second input of the adder-subtractor through a delay element.

The combination of the above essential features results in the following opportunities being provided:

Creating a high-performance DAC

Reducing interference in the zone of useful signal frequencies

The resonance risk issues in DACs with delta-sigma architecture with direct and feedback connections are addressed.

Brief description of the drawings

Figure 1 shows the circuit diagram of a digital-to-analog converter.

Figure 2 shows the frequency response of delta-sigma when a signal close to zero is received at the input.

Figure 3 shows the delta-sigma frequency response when two signals are received.

Figure 4 shows the Verilog modeling of delta-sigma.

Implementation and implementation examples Below is an example of a specific implementation of the device, which does not limit the options for its implementation.

The proposed device - a delta-sigma-based DAC - is built on the principle of direct and feedback with corresponding shift structures that reduce the risk of switching the delta-sigma to resonance.

The digital-to-analog converter - the proposed device - is schematically shown in Figure 1.

The digital-to-analog converter based on delta-sigma includes the first 1, second 2, third 3 and fourth 4 integrators, the first adder-subtractor 5, adder 6, adder 7, adder 8, shifters 9, 10, 11, 12, 13, 14, 15 and 16, the digital-to-analog converter also includes a sign determiner block 17 and a delay element 18. Input 19 of the converter is connected to the first input of adder-subtractor 5, the output 20 of which is connected to input 21 of integrator 1, the output 22 of which is connected to input 23 of shifter 9 and input 24 of shifter 16, and output 25 of shifter 9 is connected to input 26 of integrator 2, the output 27 of which is connected to input 28 of shifter 10 and input 29 of shifter 11, the output 30 of which is connected to the input 31 of integrator 3. The output 32 of integrator 3 is connected to the input 33 of shifter 12 and to the input 34 of shifter 14, the output 35 of which is connected to the input 36 of integrator 4, the output 37 of which is connected to the input 38 of shifter 15, the output 39 of which is connected to the input 40 of adder 7, the input 41 of which is connected to the output 42 of shifter 12, and the output 43 of adder 7 is connected to the input 44 of adder 6, the input 45 of which is connected to the output 46 of shifter 10, and the output 47 of adder 6 is connected to the input 48 of shifter 13, the output 49 of which is connected to the input 50 of adder 8, and the input 51 is connected to the output 52 of shifter 16. The output 53 of adder 8 is connected to the input 54 of the block sign determinator 17, output 55 of which is the output of the converter and is connected to input 56 of delay element 18, output 57 of which is connected to input 58 of adder-subtractor 5.

The digital-to-analog converter (DAC) operates as follows. A digital signal is fed to input 19, for example, a 24-bit word with a frequency lower than the quantization frequency of the DAC itself - the so-called oversampling ratio - the coefficient of the ratio of the quantization frequency to the frequency of the signals arriving at the input. The quantization frequency is always higher than the frequency of the signals arriving at the input of the DAC. This meets the Nyquist requirements. In the adder-subtractor 5, to input 58 of which the feedback signal is fed from output 57 of delay element 18. This is the signal of the senior (sign) digit. This ensures negative feedback. From output 20 of adder-subtractor 5, the subtraction result is fed to input 21 of the first integrator 1, accumulation in which occurs according to the quantization frequency. Then, from output 22, the signal is fed to shifter 9, in which the shift is carried out towards the junior digits, thereby reducing the signal value. Also, from output 22, the signal is sent in parallel to input 24 of shifter 16, in which the number is also shifted toward the least significant digits. From output 25 of shifter 9, the signal is sent to input 26 of the second integrator 2 and then from its output 27 to inputs 28 and 29 of shifters 10 and 11, respectively. In this case, the number is shifted in these shifters 10 and 11 toward the least significant digits, that is, the absolute value of the number is reduced. The number shift depth is different in each shifter. This is determined by the sigma-delta transfer characteristic. From output 46 of shifter 10, the signal is sent to first input 45 of adder 6, and from output 30 of shifter 11, the signal is sent to input 31 of the third integrator 3, and then from its output 32 to inputs 33 and 34 of motors 12 and 14, respectively. From output 35 of shifter 14 the signal goes to the fourth integrator 4, in which the next (fourth) integration of the input signal occurs according to the quantization frequency. The signal from output 37 of the fourth integrator 4 goes to input 38 of shifter 15. The number is also shifted towards the least significant digits. The reduction of the signal values in the shifters is necessary to prevent the sigma-delta from switching to the resonant mode. From output 42 of shifter 12 the signal goes to input 41 of adder 7, to input 40 of which the signal comes from output 39 of shifter 15. In adder 7, the first summation of all four integrators is thus performed by means of the corresponding coefficients (via the shifters). From output 46 of shifter 10 the first operand goes to input 45 of adder 6, to input 44 of which the second operand comes from output 43 of adder 7, which ensures the second summation in the direct delta-sigma connection. Next, from the output 47 of the adder 6 the result goes to the input 48 of the shifter 13, from the output 49 of which the signal goes to the input 50 of the adder 8, to the second input 51 of which the signal from the output 52 of the shifter 16 goes, thereby performing the next summation in the forward direction to the output of the delta-sigma. From the output 53 of the adder 8 the signal goes to the input 54 of the sign determiner block 17, from the output 55 of which the signal goes to the output of the DAC and to the input 56 of the delay element 18 for implementing the feedback, and from the output 57 of the delay element 18 the signal goes to the second input 58 of the adder-subtractor 5. Thus, the delta-sigma architecture is both direct and feedback. This ensures a reduction in quantization noise (high frequencies) in the range of useful signals. Figure 2 shows the frequency response of the delta-sigma when a signal close to zero is received at the input. And in figure 3 the frequency characteristic is shown when two useful signals are received, which is reflected in the Fourier transform graph as two peaks. Modeling of delta-sigma was carried out when describing this device in the Verilog system. In this case, 24-bit digit numbers are received at the input, for example, a sinusoid or a sum of sinusoids with a sampling frequency inherent, for example, to a digital-signal processor processing the audio frequency range. At the output of delta-sigma, a single-digit sequence is formed, which also enters the feedback. The timing diagram of Verilog modeling is shown in figure 4.

Claims (1)

A delta-sigma based digital-to-analog converter is characterized in that it includes a first, second, third, fourth, fifth, sixth, seventh and eighth shifters, an adder-subtractor, the first, second and third adders, a delay element and a sign determinator unit, wherein the input of the converter is connected to the first input of the adder-subtractor, the output of which is connected to the input of the first integrator, the output of which is connected to the input of the first shifter, the output of the first shifter is connected to the input of the second integrator, the output of the second shifter is connected to the first input of the first adder, and the output of the third shifter is connected to the input of the third integrator, the second input of the first adder is connected to the output of the second adder, and the output is connected to the input of the fifth shifter, the output of which is connected to the first input of the third adder, the output of the third integrator is connected to the inputs of the fourth and sixth shifters, the output of the fourth shifter is connected to the first input of the second adder, the second input of which is connected to the output the seventh shifter, the input of which is connected to the output of the fourth integrator, the input of which is connected to the output of the sixth shifter, the input of the eighth shifter is connected to the output of the first integrator, and the output to the input of the third adder, the output of the third adder is connected to the input of the sign determiner block, the output of which is the output of the converter and is connected to the second input of the adder-subtractor through a delay element.