RU2739343C1 - Device for bit-by-bit computing of logic and arithmetic operations - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to a device for bit-by-bit computing of logic and arithmetic operations. Device comprises interconnected logic and arithmetic operations unit, result storage unit, control unit, number input unit, first number register unit and second number register unit.

EFFECT: technical result is higher accuracy of performing logic and arithmetic operations.

1 cl, 2 tbl, 17 dwg

Description

The invention relates to technical means of informatics and computer technology and can be used to create high-speed, specialized and high-performance digital devices that perform logical operations: conjunction, disjunction, inversion, exclusive OR, equivalence, arithmetic summation and subtraction operations.

Known "Device for computing" (US Pat. RU No. 2042186, from 20.08.1995), which allows specialized processors to process fuzzy information to perform arithmetic and logical operations.

Known "Adder" (z-ka 94007826 from 27.02.1996), which performs the functions of conjunction, disjunction, equivalence, constants "0" and units.

Known "Device for performing logical operations" Pat. No. 2288500, Russian Federation, IPC G06F 7/50, publ. 27.11.2006, Bul. No. 33.

The "Computational module of logical operations" Pat. No. 2716026, Russian Federation, IPC G06F 17/00, publ. 03/05/2020, Bul. No. 7.

The disadvantage of the proposed technical solutions is the low speed of execution of logical operations, a complex algorithm of work.

In the presented device for the bitwise computation of logical and arithmetic operations, the main logical operations are performed: conjunction, disjunction, exclusive OR, equivalence, inversion, arithmetic operations: addition and subtraction.

The technical task of the proposed solution is to expand the functionality, increase the speed of logical operations, and simplify the algorithm of the device.

The solution to the problem is carried out by the fact that a device for bitwise calculation of logical and arithmetic operations containing a unit for performing logical and arithmetic operations, a result storage unit, a control unit, which are additionally introduced: a number input unit, a register unit of the first number, a register unit of the second number, and the information output of the number input unit is connected to the first information input of the second number register unit and to the first information input of the first number register unit, the second information input of which is connected to the fourth information output of the control unit, the first information output of which is connected to the second information input of the second number register unit, the information output of which is connected to the third information input of the block for performing logical and arithmetic operations, the first information input of which is connected to the information output of the register block of the first number, the control output of the input block e is connected to the control input of the block for performing logical and arithmetic operations, the information output of which is connected to the first information input of the result storage unit, the second information input of which is connected to the second information output of the control unit, the third information output of which is connected to the second information input of the block for performing logical and arithmetic operations, the first and second control inputs "RESET" and "START" of the control unit are external inputs of the device for bitwise calculation of logical and arithmetic operations.

BVCh - the block for entering numbers is used to enter binary codes of operands, the sign of the operation and determine the sign of the operation.

БРгПч - the register block of the first number is used to store the binary codes of the first number when performing logical and arithmetic operations.

BVLAO - a block for performing logical and arithmetic operations is used to perform logical operations: conjunction, disjunction, inversion, exclusive OR, equivalence, arithmetic operations: summation and subtraction.

БРгВч - the register unit of the second number is used to store the binary codes of the second number when performing logical and arithmetic operations.

BHR - results storage unit is used to record and store the results of logical and arithmetic operations.

BU - the control unit is used to generate information signals of the device for bitwise computation of logical and arithmetic operations.

In a device for bitwise computing of logical and arithmetic operations, the sequence of performing logical and arithmetic operations is determined by setting control signals at the inputs of electronic keys to a single state. The keys are opened, through which the values of the variables and the previously obtained results of other blocks are fed to the inputs of the next block of the device.

FIG. 1 shows a block diagram of a device for bitwise computation of logical and arithmetic operations.

FIG. 2 shows a variant of the technical implementation of the number input unit.

FIG. 3 shows a variant of the technical implementation of the register block of the first number and the register block of the second number.

FIG. 4 shows a block diagram of a block for performing logical and arithmetic operations.

FIG. 5 shows a variant of the technical implementation of a block for performing a logical conjunction operation.

FIG. 6 shows a variant of the technical implementation of a block for performing a logical disjunction operation.

FIG. 7 shows a variant of the technical implementation of the unit for performing the logical operation of inversion of the first binary number.

FIG. 8 shows a variant of the technical implementation of the unit for performing the logical operation of inversion of the second binary number.

FIG. 9 shows a variant of the technical implementation of the unit for performing the logical operation of the sum modulo two binary numbers.

FIG. 10 shows a variant of the technical implementation of the unit for performing a logical operation of the equivalent of binary numbers.

FIG. 11 shows a block diagram for determining the sign of the result and an adder-subtractor circuit.

FIG. 12 shows a functional diagram of the adder-subtractor.

FIG. 13 is a functional diagram for determining the sign of the result.

FIG. 14 shows schematic diagrams of switching and adder-subtractor.

FIG. 15 shows a variant of the technical implementation of the result storage unit.

FIG. 16 - meaningful GAW of the module.

FIG. 17 - labeled GAW device operation.

The device for the bitwise calculation of logical and arithmetic operations contains: a number input unit, a register unit of the first number, a unit for performing logical and arithmetic operations, a register unit for the second number, a results storage unit, a control unit, threshold elements, neurons (Fig. 1).

The following identifiers are used to describe the operation algorithm of the control unit 6.

1. BVCH - block for entering numbers.

2. БРгПч - register block of the first number.

3. BVLAO - block for performing logical and arithmetic operations.

4. БРгВч - register block of the second number.

5. BHR - block for storing results.

6. BU - control unit.

7. DKCH - binary code of a number.

8. SV - sign of the operation, the signal of summation or subtraction.

9. DPCH - binary code of the first number.

10. DVCh - binary code of the second number.

11. RES - binary digits of the result.

12. УП - information signal of control of the register unit of the second number, which includes signals: synchronization, zeroing, recording permission, issue.

13. SPC - information signal to control the operation of the result storage unit, which includes signals: synchronization, zeroing, recording permission, issue.

14. UPR - information control signal of the block for performing logical and arithmetic operations, which includes signals: synchronization, zeroing, recording permission, issue.

15. SU - information signal to control the operation of the register unit of the first number, which includes signals: synchronization, zeroing, recording permission, issue.

16. ЗнР А - sign bit of the first number.

17. ЗнР В - sign bit of the second number.

18. COP - operation code.

19. SYNC is a synchronization signal that is fed to the input of the block registers.

20. SET 0 - signal of setting to zero, arriving at the input of the block registers.

21. REC - write enable signal, which is fed to the input of the block registers.

22. VYD - a signal of permission to issue, coming to the input of the block registers.

23. BKON - a block for performing a logical conjunction operation.

24. BDIZ - block for performing logical disjunction operation.

25. BIN A - block for performing logical operations

26. BIN B - block for performing the logical operation of inversion of the second number.

27. BSum M 2 - a block for performing a logical operation of the sum modulo two.

28. BECV - a unit for performing a logical operation of the equivalent.

29. BSUM-VYCH - block for performing arithmetic operations of summation and subtraction.

30. UPKN - control signal of the block for performing the logical operation of the conjunction.

31. UPDZ - control signal of the block for performing the logical operation of disjunction.

32. UPIN A - control signal of the unit for performing the logical operation of inversion of the first number.

33. UPIN B - control signal of the unit for performing the logical operation of inversion of the second number.

34. UpSum 2 - control signal of the block for performing the logical operation of the sum modulo two.

35. UpEKV - control signal of the unit for performing the logical operation of the equivalent.

36. UPSUM-VYCH - control signal of the unit for performing arithmetic operations of summation and subtraction.

37. RKN1 - the first result of the logical conjunction operation by the conjunction block.

38. RKNn - the result of performing a logical operation of conjunction of the least significant bits of binary numbers by the conjunction block.

39. RESCON - the result of a logical conjunction operation by the conjunction block.

40. RDZ1 - the first result of the logical operation of disjunction by the disjunction block.

41. RDZn - the result of performing a logical operation of disjunction of the least significant bits of binary numbers by the disjunction block.

42. RESDIZ - the result of a logical disjunction operation by a disjunction block.

43. RESET A - the result of performing the logical operation of the inversion by the block of inversion of the first number.

44. RESERVE B - the result of the execution of the logical operation of inversion by the block of inversion of the second number.

45. ResSum M21 - the first result of performing a logical operation of sum modulo two by a sum modulo two block.

46. ResSum M2n - the result of performing a logical operation of the sum modulo two of the least significant bits of binary numbers by the sum modulo two block.

47. ResSum 2 - the result of performing the logical operation of the sum modulo two by the sum modulo two block.

48. - первый результат выполнения логической операции эквиваленции блоком эквиваленции.

48. - the first result of the execution of the logical operation equivalent by the block of equivalence.

49. - результат выполнения логической операции эквиваленции младших разрядов двоичных чисел блоком эквиваленции.

49. - the result of performing a logical operation equivalent to the least significant bits of binary numbers by an equivalent block.

50. ReEKV is the result of performing a logical operation equivalent by an equivalent block.

51. ZnREZ - sign bit of the result.

52. ЗмЗнР - a loan from a sign bit when performing a subtraction operation.

53. A1…. Аn - binary digits of the first number.

54. В1…. Вn - binary digits of the second number.

55. Pi + 1 / Zi + 1 - signal to carry to the high order bits when adding or borrowing from the high order bits of binary numbers when subtracting.

56. Si - the category of the sum.

57. Ri - difference digit

58. Pi - transfer to the most significant bit during summation.

59. Zi - a loan from the most significant category when subtracted.

60. RES1 - the result of the execution of the first block SUM-EXCH1.

61. RES2 - the result of the second block SUM-VYCH2.

62. RESn - the result of execution of the lower block SUM-EXCHn.

63. RESUM-VYCH - the result of performing arithmetic operations, summation and subtraction.

64. OOZR - scheme for determining the sign of the result.

65. OB - the command to reset the binary counter Сч1 of the result storage unit.

66. US “0” - command to reset the binary counter Сч2 of the result storage unit.

67. GI - a pulse generator coming from the control unit to the summing input (+) of the binary counter Сч1 of the result storage unit.

68. ТИ - clock pulses coming from the control unit to the summing input (+) of the binary counter Сч2 of the result storage unit.

69. VK - the command to select the crystal of the random access memory of the RAM of the result storage unit.

70. Сч / Зп - command to read / write the RAM of the result storage unit.

71. REO - information input of the result storage unit.

72. RESET - a signal for resetting (zeroing) the memory elements of the device for bitwise calculation of logical and arithmetic operations.

73. START - signal to start the device.

The operation of the control unit of the device for bitwise computation of logical and arithmetic operations.

The concise GAW control is shown in Fig. 16 and it reflects the operation of the device for bitwise calculation of logical and arithmetic operations (figure 1).

In block 2 of the algorithm, a signal is applied to set to zero state - RESET to the inputs of all elements of the device.

In block 3 of the algorithm, the signal is set - start at a single value START: = 1.

In block 4 of the algorithm by the commands: OB: = 1, US "0": = 1, the binary counters Сч1 and Сч2 are set to zero value of the block 5 for storing the results, which form the addresses of the rows and columns of the random access memory (Fig. 15).

In block 5 of the algorithm, numbers are entered in the decimal number system A10, B10 and the numbers are converted into a binary number system (Fig. 2).

In block 6 of the algorithm, according to the commands: БРгПч: = SU, БРгВч: = УП, information signals are sent from the output of the control unit 6 to the inputs of the registers of the blocks of the first and second numbers to perform operations: zeroing, synchronization, writing and issuing. By commands: БРгПч: = ДКЧ and БРгВч: = ДКЧ, binary codes of input numbers are sent to the inputs of the registers of the first and second numbers for recording and storage.

In block 7 of the algorithm, by command: BVLAO: = UPR, an information signal is received at the input of the block for performing logical and arithmetic operations, which consists of control signals. These signals are fed to the inputs of blocks that perform logical and arithmetic operations. According to the commands: BVLAO: = DPCH, BVLAO: = DPCH, binary codes of the first and second numbers are received at the inputs of the block for performing logical and arithmetic operations to perform operations (Fig. 4).

In block 8 of the algorithm, the sign of the execution of the logical operation of the KOH conjunction is analyzed. If the block for performing logical and arithmetic operations performs another operation, then the transition to block 11 of the algorithm is carried out. If the operation is conjunction, then the transition to block 9 of the algorithm is carried out.

In block 9 of the algorithm, by the command BKON: = UPKN, a control signal is sent to the control inputs of the electronic keys of the block for performing the logical conjunction operation to enable the execution of the logical operation I. By the commands: BKON: = DPCH, BKON: = DPCH, the input of the unit for performing the logical conjunction operation is fed binary codes of the first and second numbers (figure 5).

In block 10 of the algorithm, by the command RES: = RESCON, the result of the logical conjunction operation on the input numbers for recording and storage is received at the input of the result storage unit (Fig. 5).

In block 11 of the algorithm, a sign of the execution of the logical operation of disjunction of the DIZ is analyzed. If the block for performing logical and arithmetic operations performs another operation, then the transition to block 14 of the algorithm is carried out. If the disjunction operation is performed, then the transition to block 12 of the algorithm is carried out.

In block 12 of the algorithm, at the command BDIZ: = UPDZ, a control signal is sent to the control inputs of the electronic keys of the block for performing the logical disjunction operation to enable the execution of the logical OR operation. According to the commands: BDIZ: = DPCh, BDIZ: = DPCh, binary codes of the first and second numbers are fed to the input of the block for performing the logical operation of disjunction (Fig. 6).

In block 13 of the algorithm, by the command RES: = RESDIZ, the result of performing a logical disjunction operation on the input numbers for recording and storage is received at the input of the result storage unit (Fig. 6).

In block 14 of the algorithm, a sign of the execution of a logical operation of inversion of the first number of ID A is analyzed. If the block for performing logical and arithmetic operations performs another operation, then the transition to block 17 of the algorithm is carried out. If the operation of inversion of the first number is performed, then the transition to block 15 of the algorithm is carried out.

In block 15 of the algorithm, at the command BIN A: = UpIN A, a control signal is sent to the control inputs of the electronic keys of the block for performing the logical operation of inversion of the first number to enable the execution of the logical operation of inversion. According to the commands: BIN A: = DPCh, the binary digits of the first number are fed to the input of the block for performing the logical operation of inversion of the first number (Fig. 7).

In block 16 of the algorithm, by the command RES: = RESIN A, the result of performing the logical operation of inversion of the first number for recording and storage is received at the input of the result storage unit (Fig. 7).

In block 17 of the algorithm, a sign of the execution of a logical operation of inversion of the second number of ID B is analyzed. If the block for performing logical and arithmetic operations performs another operation, then the transition to block 20 of the algorithm is carried out. If the operation of inversion of the second number is performed, then the transition to block 18 of the algorithm is performed.

In block 18 of the algorithm, on the command BIN B: = UpIN B, a control signal is sent to the control inputs of the electronic keys of the block for performing the logical operation of inversion of the second number to enable the execution of the logical operation of inversion. According to the commands: BIN B: = DVCh, the binary digits of the second number are fed to the input of the block for performing the logical operation of inverting the second number (Fig. 8).

In block 19 of the algorithm, by the command RES: = RESIN B, the result of the execution of the logical operation of inversion of the second number for recording and storage is sent to the input of the result storage unit (Fig. 8).

In block 20 of the algorithm, a sign of performing a logical operation of the sum modulo two Sum M 2 is analyzed. If the block for performing logical and arithmetic operations performs another operation, then the transition to block 23 of the algorithm is carried out. If the operation is the sum modulo two binary numbers, then the transition to block 21 of the algorithm is performed.

In block 21 of the algorithm, at the command BSum M 2: = UpSum2, a control signal is sent to the control inputs of the electronic keys of the block for performing the logical operation of the sum modulo two to enable the execution of the logical operation of the sum modulo two. By commands: BSum M 2: = DPCh, BSum M 2: = DHCH at the inputs of the block for performing the logical operation of the sum modulo two, binary codes of the first and second numbers are fed (Fig. 9).

In block 22 of the algorithm, by the command RES: = ResSum 2, the result of performing the logical operation of the sum modulo two over the input numbers for recording and storage is sent to the inputs of the result storage unit (Fig. 9).

In block 23 of the algorithm, the sign of the execution of the logical operation of the EKV equivalent is analyzed. If the block for performing logical and arithmetic operations performs another operation, then the transition to block 26 of the algorithm is performed. If the operation is the equivalent of binary numbers, then the transition to block 24 of the algorithm is carried out.

In the block 24 of the algorithm, on the command BECV: = UpEKV, a control signal is sent to the control inputs of the electronic keys of the block for performing the logical operation of equivalence to enable the execution of the logical operation of the equivalent. By commands: BEKV: = DPCH, BEKV: = DPCH, binary codes of the first and second numbers are fed to the inputs of the block for performing the logical operation of the equivalence (Fig. 10).

In block 25 of the algorithm, by the command RES: = RESEKV, the result of performing a logical operation of equivalence on the input numbers for recording and storage is received at the inputs of the result storage unit (Fig. 10).

In block 26 of the algorithm, a sign of performing arithmetic operations, summing or subtracting SUM-MULT, is analyzed. If the block for performing logical and arithmetic operations does not perform any calculations, then the transition to the final block 31 of the algorithm is performed. If the operation of addition or subtraction of binary numbers is performed, then the transition to block 27 of the algorithm is performed.

In block 27 of the algorithm, by the command BSUM-VUCH: = UPSUM-VYCH, a control signal is sent to the inputs of the electronic keys of the SUM-VYCH block to enable the execution of arithmetic operations, summation or subtraction. By commands: BSUM-VYCH: = DPCH, BSUM-VYCH: = DVCH, binary codes of the first and second numbers are fed to the inputs of the block for performing arithmetic operations, summing or subtracting (Figs. 13, 14).

In the block 28 of the algorithm, by the command RES: = RESUM-OUCH, the result of performing arithmetic operations, summing or subtracting binary numbers for recording and storage, arrives at the inputs of the result storage unit (Fig. 13, 14).

In block 29 of the algorithm, according to the commands: VK: = 0, ZpSch: = 0, zero values are supplied to the control inputs of the RAM of the results storage unit to create a mode for recording the results into the device memory (Fig. 15).

In the block 30 of the algorithm, by the command RAM: = RES, the results of performing logical and arithmetic operations for recording and storage are fed to the information inputs of the RAM of the results storage unit (Fig. 15).

Algorithm block 31 is final.

The device for bitwise computing of logical and arithmetic operations performs logical bitwise operations: conjunction (AND), disjunction (OR), exclusive OR (⊕), equivalence (~), inversion (NOT) of binary numbers, arithmetic operations: summation and subtraction. Bitwise execution of logical operations applies to each pair of bits that are at the same position in the binary representation of numbers. These operations are used when comparing numbers, adding and subtracting. Bitwise operations are implemented in the arithmetic logic unit (ALU) of the processor. Most processors implement register NOT as instructions; register two-argument AND, OR, exclusive OR; check for equality to zero; three types of bit shifts as well as cyclic bit shifts. The AND register operation is used to: check a bit for 0 or 1, set 0 to the specified bit (clear the bit). The OR register operation is used to: set 1 to the specified bit. An exclusive OR register operation is used to invert register bits by mask. Shifts left and right are used for multiplication by 2 and integer division by 2, respectively, and separating individual bits.

The operation of the device for bitwise calculation of logical and arithmetic operations is as follows.

External control signals "RESET" and "START" enter the control unit 6.

Block 1 input numbers contains the encoder SHF DD7, adders modulo two DD8 and DD9 (figure 2). This block allows you to enter binary numbers. From the output of the encoder, binary codes of numbers DKCH are formed with their own signs: ZnRA, ZnRV. Signed digits of numbers and the operation code from the output of the encoder are fed to the inputs of the adders modulo two DD8 and DD9. The summation-subtraction signal CB is formed at the output of element DD9. The adders modulo two are made on neural-like elements. The output signal is calculated by the formula:

(1)

(one)

The output signals of the block 1 for inputting numbers are binary codes of the DKCH operands, presented in direct codes and a sign of the sum-subtraction operation SV (figure 2).

Block 2 of the register of the first number contains n-binary triggers Trn, where n is the number of bits of the input number. This block is designed to store the binary code of the first number. The input information signal of the unit is the control signal of the SU. In parallel, all the trigger inputs receive control signals: synchronization, setting to “0”, recording and outputting the result. Before the start of operation of the adder-subtractor upon arrival of the information signal CS from block 6, all triggers of the block are reset to zero (Fig. 3).

Block 3 for performing logical and arithmetic operations consists of blocks: the BKON conjunction, the BDIZ disjunction, the inversion of the first BIN A number, the inversion of the second BIN number B, the sum operation modulo two BSum 2, the BECV equivalents, arithmetic summation and subtraction operations of the BSUM-VUCH (Fig. .4). The input information signals of the block are binary numbers: the first DPC and the second DHF. These signals come from the outputs of the register blocks of the first and second numbers, respectively. Binary numbers are fed to the inputs of all blocks in parallel. The input information signal of the UPR control comes from the output of the control unit. The structure of this signal includes control signals for performing logical operations: conjunction UPKN, disjunction UPDZ, inversion of the first number UpIN A, inversion of the second number UpIN B, sum modulo two UpSum2, equivalents UpEKV, performing arithmetic operations of summation and subtraction UPSUM-VYCH. The output information signal is the signal of the RES result of performing logical and arithmetic operations by blocks. Structurally, the information signal RES consists of the results of performing logical operations: conjunction RESCON, disjunction RESDIZ, inversion of the first number RezNE A, inversion of the second number RezNE B, sum modulo two RezSum 2, equivalents ReEKV, arithmetic operation summation and subtraction RezSUM-VYCH. The signal of the result of the RES block is fed to the input of the block 6 for storing the results of the BHR (figure 4).

поступают на первые входы пороговых элементов DD23 и DD24 соответственно. Двоичные переменные

поступают на первые входы пороговых элементов DD26 и DD27 соответственно. Управляющим сигналом пороговых элементов DD23, DD24, DD26, DD27 является сигнал управления выполнения логической операции конъюнкции УпКН. Этот управляющий сигнал поступает на вторые управляющие входы пороговых элементов DD23, DD24, DD26, DD27, выполняющих функции электронных ключей. Если управляющий сигнал УпКН равен единице, то электронные ключи будут открыты, входные двоичные переменные

поступают на входы пороговых элементов DD25 и DD28 соответственно, которые выполняют логическую операцию И. На выходе этих элементов формируются результаты выполнения логической операции И над входными переменными. На выходе порогового элемента DD25 определяется сигнал результата конъюнкции РКН1 над переменными

, на выходе порогового элемента DD28 определяется сигнал результата конъюнкции РКНn над переменными

. Если управляющий сигнал УпКН равен нулю, то электронные ключи будут заперты. Логическая операция И на выходе блока выполняться не будет. Выходной информационный сигнал РезКОН является результатом выполнения логической операции И блоком конъюнкции БКОН (фиг.5).Block 16 for performing the logical operation of the BKON conjunction consists of threshold elements DD23 - DD28 (Fig. 5). The input information signals of the block are binary numbers: the first DPC and the second DHF. Threshold elements DD23, DD24, DD26, DD27 function as electronic keys. Binary variables

come to the first inputs of the threshold elements DD23 and DD24, respectively. Binary variables

come to the first inputs of the threshold elements DD26 and DD27, respectively. The control signal of the threshold elements DD23, DD24, DD26, DD27 is the control signal for performing the logical operation of the conjunction UPKN. This control signal is fed to the second control inputs of the threshold elements DD23, DD24, DD26, DD27, which function as electronic keys. If the control signal UPKN is equal to one, then the electronic keys will be open, the input binary variables

come to the inputs of the threshold elements DD25 and DD28, respectively, which perform the logical AND operation. At the output of these elements, the results of the execution of the logical AND operation on the input variables are formed. At the output of the threshold element DD25, the signal of the result of the conjunction RKN1 over the variables is determined

, at the output of the threshold element DD28, the signal of the result of the conjunction RKNn over the variables

... If the control signal UPKN is zero, then the electronic keys will be locked. The logical AND operation will not be performed at the block output. The output information signal RESKON is the result of performing a logical operation AND by the conjunction block BKON (figure 5).

поступают на первые входы пороговых элементов DD29 и DD30 соответственно. Двоичные переменные

поступают на первые входы пороговых элементов DD32 и DD33 соответственно. Управляющим сигналом пороговых элементов DD29, DD30, DD32, DD33 является сигнал управления выполнения логической операции дизъюнкции УпДЗ. Этот управляющий сигнал поступает на вторые управляющие входы пороговых элементов DD29, DD30, DD32, DD33, выполняющих функции электронных ключей. Если управляющий сигнал УпДЗ равен единице, то электронные ключи будут открыты, входные двоичные переменные

поступают на входы пороговых элементов DD31 и DD34 соответственно, которые выполняют логическую операцию ИЛИ. На выходе этих элементов формируются результаты выполнения логической операции ИЛИ над входными переменными. На выходе порогового элемента DD31 определяется сигнал результата дизъюнкции РДЗ1 над переменными

, на выходе порогового элемента DD34 определяется сигнал результата дизъюнкции РДЗn над переменными

. Если управляющий сигнал УпДЗ равен нулю, то электронные ключи будут заперты. Логическая операция ИЛИ на выходе блока выполняться не будет. Выходной информационный сигнал РезДИЗ является результатом выполнения логической операции ИЛИ блоком дизъюнкции БДИЗ (фиг.6).Unit 17 for performing logical operation of disjunction BDIZ consists of threshold elements DD29 - DD34 (Fig. 6). The input information signals of the block are binary numbers: the first DPC and the second DHF. Threshold elements DD29, DD30, DD32, DD33 serve as electronic keys. Binary variables

come to the first inputs of the threshold elements DD29 and DD30, respectively. Binary variables

come to the first inputs of the threshold elements DD32 and DD33, respectively. The control signal of the threshold elements DD29, DD30, DD32, DD33 is the control signal for performing the logical operation of the disjunction UPDZ. This control signal is fed to the second control inputs of the threshold elements DD29, DD30, DD32, DD33, which function as electronic keys. If the control signal UPDZ is equal to one, then the electronic keys will be open, the input binary variables

come to the inputs of threshold elements DD31 and DD34, respectively, which perform a logical OR operation. At the output of these elements, the results of performing a logical OR operation on the input variables are formed. At the output of the threshold element DD31, the signal of the result of disjunction RDZ1 over the variables is determined

, at the output of the threshold element DD34, the signal of the result of the disjunction of RDZn over the variables

... If the control signal UPDZ is zero, then the electronic keys will be locked. The logical OR operation at the block output will not be performed. The output information signal RESDIZ is the result of performing a logical OR operation by the block of disjunction BDIZ (Fig. 6).

поступают на первые входы пороговых элементов DD35, DD37, DD39, DD41 соответственно. Управляющим сигналом пороговых элементов DD35, DD37, DD39, DD41 является сигнал управления выполнения логической операции инверсии первого числа УпИН А. Этот сигнал поступает на вторые управляющие входы пороговых элементов DD35, DD37, DD39, DD41 выполняющих функции электронных ключей. Если управляющий сигнал УпИН А равен единице, то электронные ключи будут открыты, входные двоичные переменные

поступают на входы пороговых элементов DD36, DD38, DD40, DD42 соответственно, которые выполняют логическую операцию инверсию входных переменных, инвертируют двоичные разряды. На выходе этих элементов формируются результаты выполнения логической операции инверсии входных переменных

. Если управляющий сигнал УпИН А равен нулю, то электронные ключи будут заперты. Логическая операция инверсии первого числа на выходе блока выполняться не будет. Выходной информационный сигнал РезИН А является результатом выполнения логической операции инверсии блоком инверсии первого числа БИН А (фиг.7).Block 18 for performing the logical operation of inversion of the first number of BIN A consists of threshold elements DD35 - DD42 (Fig. 7). The input information signals of the block are binary digits of the first number of the DFC. Threshold elements DD35, DD37, DD39, DD41 serve as electronic keys. Binary variables

come to the first inputs of the threshold elements DD35, DD37, DD39, DD41, respectively. The control signal of the threshold elements DD35, DD37, DD39, DD41 is the control signal for performing the logical operation of inversion of the first number of UPIN A. This signal is fed to the second control inputs of the threshold elements DD35, DD37, DD39, DD41 performing the functions of electronic keys. If the control signal UPIN A is equal to one, then the electronic keys will be open, the input binary variables

come to the inputs of threshold elements DD36, DD38, DD40, DD42, respectively, which perform a logical operation inversion of input variables, inverting the binary digits. At the output of these elements, the results of the execution of the logical operation of inversion of the input variables are formed

... If the control signal UpIN A is equal to zero, then the electronic keys will be locked. The logical operation of inversion of the first number at the block output will not be performed. The output information signal RezIN A is the result of performing a logical inversion operation by the inversion unit of the first number of BIN A (Fig. 7).

поступают на первые входы пороговых элементов DD43, DD45, DD47, DD49 соответственно. Управляющим сигналом пороговых элементов DD43, DD45, DD47, DD49 является сигнал управления выполнения логической операции инверсии второго числа УпИН В. Этот сигнал поступает на вторые управляющие входы пороговых элементов DD43, DD45, DD47, DD49 выполняющих функции электронных ключей. Если управляющий сигнал УпИН В равен единице, то электронные ключи будут открыты, входные двоичные переменные

поступают на входы пороговых элементов DD44, DD46, DD48, DD50 соответственно, которые выполняют логическую операцию инверсию входных переменных, инвертируют двоичные разряды. На выходе этих элементов формируются результаты выполнения логической операции инверсии входных переменных

. Если управляющий сигнал УпИН В равен нулю, то электронные ключи будут заперты. Логическая операция инверсии второго числа на выходе блока выполняться не будет. Выходной информационный сигнал РезИН В является результатом выполнения логической операции инверсии блоком инверсии второго числа БИН В (фиг.8).Block 19 for performing the logical operation of inversion of the second number of BIN B consists of threshold elements DD43 - DD50 (Fig. 8). The input information signals of the block are the binary digits of the second number of the DVCH. Threshold elements DD43, DD45, DD47, DD49 function as electronic keys. Binary variables

come to the first inputs of the threshold elements DD43, DD45, DD47, DD49, respectively. The control signal of the threshold elements DD43, DD45, DD47, DD49 is the control signal for performing the logical operation of the inversion of the second number of UPIN B. This signal is fed to the second control inputs of the threshold elements DD43, DD45, DD47, DD49 performing the functions of electronic keys. If the control signal UPIN B is equal to one, then the electronic keys will be open, the input binary variables

come to the inputs of threshold elements DD44, DD46, DD48, DD50, respectively, which perform a logical operation inversion of input variables, inverting the binary digits. At the output of these elements, the results of the execution of the logical operation of inversion of the input variables are formed

... If the control signal UPIN B is equal to zero, then the electronic keys will be locked. The logical operation of inversion of the second number at the block output will not be performed. The output information signal RezIN B is the result of a logical inversion operation performed by the inversion unit of the second number of BIN B (Fig. 8).

поступают на первые входы пороговых элементов DD51 и DD52 соответственно. Двоичные переменные

поступают на первые входы пороговых элементов DD54 и DD55 соответственно. Управляющим сигналом пороговых элементов DD51, DD52, DD54, DD55 является сигнал управления выполнения логической операции суммы по модулю два УпСум 2. Этот управляющий сигнал поступает на вторые управляющие входы пороговых элементов DD51, DD52, DD54, DD55, выполняющих функции электронных ключей. Если управляющий сигнал УпСум 2 равен единице, то электронные ключи будут открыты, входные двоичные переменные

поступают на входы нейроподобных элементов DD53 и DD56 соответственно, которые выполняют логическую операцию сумму по модулю два. На выходе этих элементов формируются результаты выполнения логической операции суммы по модулю два над входными переменными. На выходе нейроподобного элемента DD53 определяется сигнал результата суммы по модулю два РезСумМ 21 над переменными

, на выходе нейроподобного элемента DD56 определяется сигнал результата суммы по модулю два РезСумМ 2n над переменными

. Если управляющий сигнал УпСум 2 равен нулю, то электронные ключи будут заперты. Логическая операция сумма по модулю два на выходе блока выполняться не будет. Выходной информационный сигнал РезСумМ 2 является результатом выполнения логической операции суммы по модулю два блоком суммы по модулю два БСумМ 2 (фиг.9).Block 20 for performing logical operations of the sum modulo two BSum 2 consists of threshold elements DD51, DD52, DD54, DD55 and neural-like elements DD53 and DD56 (Fig. 9). The input information signals of the block are binary numbers: the first DPC and the second DHF. Threshold elements DD51, DD52, DD54, DD55 function as electronic keys. Binary variables

come to the first inputs of the threshold elements DD51 and DD52, respectively. Binary variables

come to the first inputs of the threshold elements DD54 and DD55, respectively. The control signal of the threshold elements DD51, DD52, DD54, DD55 is the control signal for performing the logical operation of the sum modulo two UpSum 2. This control signal is fed to the second control inputs of the threshold elements DD51, DD52, DD54, DD55, which function as electronic keys. If the control signal UpSum 2 is equal to one, then the electronic keys will be open, the input binary variables

come to the inputs of neural-like elements DD53 and DD56, respectively, which perform a logical operation, the sum modulo two. At the output of these elements, the results of the execution of the logical operation of the sum modulo two on the input variables are formed. At the output of the neural-like element DD53, the signal of the result of the sum modulo two ResSum 21 over the variables is determined

, at the output of the neural-like element DD56, the signal of the result of the sum modulo two ResSum 2n over the variables

... If the control signal UpSum 2 is zero, then the electronic keys will be locked. The logical operation sum modulo two at the block output will not be performed. The output information signal ResSum 2 is the result of performing the logical operation of the sum modulo two by the sum modulo two block BSum 2 (Fig. 9).

поступают на первые входы пороговых элементов DD57 и DD58 соответственно. Двоичные переменные

поступают на первые входы пороговых элементов DD60 и DD61 соответственно. Управляющим сигналом пороговых элементов DD57, DD58, DD60, DD61 является сигнал управления выполнения логической операции эквиваленции УпЭКВ. Этот управляющий сигнал поступает на вторые управляющие входы пороговых элементов DD57, DD58, DD60, DD61, выполняющих функции электронных ключей. Если управляющий сигнал УпЭКВ равен единице, то электронные ключи будут открыты, входные двоичные переменные

поступают на входы нейроподобных элементов DD59 и DD62 соответственно, которые выполняют логическую операцию эквиваленции. На выходе этих элементов формируются результаты выполнения логической операции эквиваленции над входными переменными. На выходе нейроподобного элемента DD59 определяется сигнал результата эквиваленции РезЭКВ1 над переменными

, на выходе нейроподобного элемента DD62 определяется сигнал результата эквиваленции РезЭквn над переменными

. Если управляющий сигнал УпЭКВ равен нулю, то электронные ключи будут заперты. Логическая операция эквиваленция на выходе блока выполняться не будет. Выходной информационный сигнал РезЭКВ является результатом выполнения логической операции эквиваленции блоком эквиваленции БЭКВ (фиг.10).Block 21 for performing the logical operation of the BECV equivalent consists of threshold elements DD57, DD58, DD60, DD61 and neural-like elements DD59 and DD62 (Fig. 10). The input information signals of the block are binary numbers: the first DPC and the second DHF. Threshold elements DD57, DD58, DD60, DD61 serve as electronic keys. Binary variables

come to the first inputs of the threshold elements DD57 and DD58, respectively. Binary variables

come to the first inputs of the threshold elements DD60 and DD61, respectively. The control signal of the threshold elements DD57, DD58, DD60, DD61 is the control signal for the execution of the logical operation of the equivalent UPEKV. This control signal is fed to the second control inputs of the threshold elements DD57, DD58, DD60, DD61, which function as electronic keys. If the control signal UPEKV is equal to one, then the electronic keys will be open, the input binary variables

come to the inputs of neural-like elements DD59 and DD62, respectively, which perform a logical operation of equivalence. At the output of these elements, the results of the execution of the logical operation of equivalence on the input variables are formed. At the output of the neural-like element DD59, the signal of the result of the equivalent ReECV1 over the variables is determined

, at the output of the neural-like element DD62, the signal of the result of the equivalent ReEqn over the variables

... If the control signal UpEKV is zero, then the electronic keys will be locked. The logical operation equivalent will not be performed at the block output. The output information signal ReEKV is the result of the execution of the logical operation of the equivalent by the unit of equivalence BEKV (figure 10).

Block 22 consists of a circuit for determining the sign of the result of the SDS and a circuit SUM-SUB of adders-subtractors. The structure of the SUM-OCH circuit includes a switching circuit and adders-subtractors (Fig. 11). The SUM-SUB circuit of the adder-subtractors contains a circuit for determining the sign of the result of the CDPD DD66, the circuit of the adder-subtractors DD67 - DD69 (Fig. 12). This block performs arithmetic operations of addition and subtraction, determines the sign bit of the result. The modules of n-bit binary of the first DFC and the second DFC numbers, the sign of the addition-subtraction operation, the SV signal, which is fed in parallel to all the inputs of the circuits, and the control signal of the operation of the adders-subtractors UPSUM-VYCH, arriving in parallel at all the inputs of the circuits, arrive at the input of the block. If the CB signal is equal to zero, then the block circuits perform the addition of binary numbers, if this signal is equal to one, then a bitwise subtraction operation is performed. The inputs of each adder-subtractor SUM-VYCHi circuit receive the same-name binary digits of the numbers Ai and Bi, the control signal for the operation of the adder-subtractors UPSUM-VYCH, the operation sign CB signal, transfer Pi from the lower digits to the higher ones and borrow Zi from the higher digits to the lower ones. Signal digits of the first ZnR A and the second ZnR B of binary numbers, the summation-subtraction signal CB (Fig. 12) are fed to the circuit for determining the sign of the result of the RCP. The borrow signal from the sign bit ZmZnR is fed to the input of the first adder-subtractor SUM-VYCH1, which performs operations with the most significant bits of the input numbers. This signal is generated when numbers are subtracted. If the loan ЗмЗнР is equal to zero, then the first binary number is greater than the second in absolute value, in this case there is no need to swap input numbers. If the borrow signal is equal to one, in this case, subtraction from the smaller number modulo the larger one occurs, then to obtain the difference, the input numbers must be swapped. The information signal of the result RES is the output signal of the block (Fig. 12).

The scheme for determining the sign of the result of the RPC determines the sign bit of the result. The structure of the circuit includes threshold elements DD70 - DD74 (Fig. 13). Input signals: a sign of the operation of summation-subtraction of the SV and a loan from the sign bit of the first number are fed to the input of the SUM-VYCH1 circuit, on which the most significant bits are summed up, are fed to the input of the threshold element PE DD70, which performs the function of the logic circuit I. Signal from the output of the threshold element DD70 is fed to the direct control input of the threshold element PE DD73, which performs the function of a logic circuit AND and to the input of the threshold element DD71, which performs the function of an inverter. The signal from the output of the inverter is fed to the direct control input of the threshold element PE DD72, which performs the function of the logical circuit I. The output signals of the threshold elements DD72 and DD73 are fed to the inputs of the threshold element PE DD74, which performs the function of the OR logic circuit. If the signal of addition-subtraction CB is equal to zero, then an arithmetic operation of the addition of binary numbers is performed. The input numbers An and Bn are summed modulo, the sign of the sum is assigned the sign of the first number. An. The output signal of the threshold element DD70 will be zero. The threshold element PE DD73 will be triggered, the output will be zero. The threshold element DD72 will be open, since the signal from the DD70 output will go to the control input through the DD71 inverter. The first input of the threshold element DD72 is the sign bit of the first number ZnR A, which through the open threshold element DD72 will go to the first input of the threshold element DD74 - OR circuit. The sign bit of the result ZnR RES - the output of the logic circuit OR element DD74, will be equal to the sign bit of the first number ZnR A.

If the summation-subtraction signal CB is equal to one, then the arithmetic operation is subtraction of binary numbers, the smaller is subtracted from the larger in absolute value. The defining signal in comparing the moduli of numbers is the borrowing signal from the sign bit of the first number ZmZnR. The sign of the difference is assigned the sign of the larger number. If the signal of borrowing ЗмЗнР is equal to zero, then the first number in absolute value is greater than the second, in this case the difference between the numbers An and Bn is calculated. The output signal of the threshold element DD70 will be zero. The threshold element PE DD73 will be triggered, the output will be zero. The threshold element DD72 will be open, since the signal from the DD70 output will go to the control input through the DD71 inverter. The first input of the threshold element DD72 is the sign bit of the first number ZnR A, which through the open threshold element DD72 will go to the first input of the threshold element DD74 - OR circuit. The sign bit of the result ZnR RES - the output of the logic circuit OR element DD74, will be equal to the sign bit of the larger number of ZnRA.

If the signal of borrowing ЗмЗнР is equal to one, then the first number is less in absolute value than the second, in this case the difference between the numbers Bn and An is calculated. The output signal of the threshold element DD70 will be equal to one. The threshold element PE DD73 will be open, the output will be a single value. The threshold element DD72 will be locked, since the signal from the DD70 output will go to the control input through the DD71 inverter. The second input of the threshold element DD73 is the sign bit of the second larger number of ZnR B, which, through the open threshold element DD73, will go to the second input of the threshold element DD74 - OR circuit. The sign bit of the result ZnR RES - the output of the logic circuit OR element DD74, will be equal to the sign bit of the larger second number ZnR B (Fig. 13).

The switching circuit swaps the places of the input binary digits when performing the subtraction operation, if a larger number is subtracted from the smaller in absolute value, as a result of which a borrow signal is generated from the sign bit of the first ZmZnR number. After analyzing this signal and performing a permutation of numbers, as a result of this, the smaller first number is subtracted from the larger second number in absolute value.

The structure of the switching circuit includes threshold elements DD75 - DD83 (Fig. 14). Input signals: control signal of summation and subtraction UPSUM-VYCH, borrowing from the sign bit of the first number ZmZnR and binary digits of numbers Ai and Bi are fed to the inputs of adder-subtractor circuits SUM-VYCHi, where an arithmetic operation is performed: summation and subtraction from a larger one in absolute value. of the same-name bits of binary numbers.

The summation and subtraction signal UPSUM-VOCH is fed in parallel to the control inputs of the threshold elements DD75 and DD80, which perform the function of electronic keys. If the control signal UPSUM-OCH is zero, then the electronic keys DD75 and DD80 will be locked. Input binary digits Аi and Вi are not supplied to the inputs of adder-subtractor circuits. If the control signal is equal to one, the electronic keys DD75 and DD80 will be open, the binary digits Ai and Bi are fed to the input of the adder-subtractor circuits, in this case the arithmetic operations will be performed. The borrowing signal from the sign bit of the first ZmZnR number is fed in parallel to the inputs of the threshold elements PE DD76 and DD81, which perform the functions of inverters and to the inputs of the threshold elements PE DD78 and DD82, which perform the functions of logic circuits I. Binary bits of the first number Ai are fed to the first inputs threshold elements PE DD75 and DD82, the second number Bi are fed to the second inputs of the threshold elements PE DD80 and DD83, which perform the functions of logic circuits I. The threshold element PE DD79 performs the function of a logic OR circuit. If the borrow signal from the sign bit of the first ZmZnR number is equal to zero, then the threshold elements DD78 and DD82 will be locked. Threshold elements DD77 and DD83 will be open, because to their inputs a zero control signal is supplied through the inverters DD76 and DD81. In this case, the binary bit of the first number Ai through the open element DD77 and the threshold element DD79 (OR logic) will arrive at the first input of the neural-like element DD86, which performs the logical function of sum modulo two. The binary bit of the second number Bi through the open element DD83 will go to the fourth input of the threshold element DD87, which performs the logical function I. If the borrow signal from the sign bit of the first number ZmZnR is equal to a single value, then the threshold elements DD77 and DD83 will be locked, since a single control signal is fed to their inputs through the DD76 and DD81 inverters. Threshold elements DD78 and DD82 will be open. In this case, the binary bit of the second number Bi through the open element DD78 and the threshold element DD79 will go to the first input of the neural-like element DD86. The binary bit of the first number Ai through the open element DD82 will arrive at the third input of the threshold element DD87. As a result, there is a permutation of binary digits, the first smaller one becomes the second, the second larger one becomes the first to perform an arithmetic subtraction operation (Fig. 14).

A full one-bit adder is designed to add three one-bit binary numbers (Fig. 14). The device has three inputs: the binary digits Ai, Bi, the transfer result Pi + 1 of the previous adder, and two outputs: the result of addition Si and the transfer signal to the most significant bit Pi.

Truth Table 1 displays the operation of a full 1-digit adder.

From table 1, the sum of Si numbers is determined by the formula

(1)

(one)

The transfer of Pi from the least significant bit to the most significant when adding numbers is determined by the formula

(2)

(2)

The operation of a full one-digit subtractor is described by truth table 2, which displays: loan Z _{i + 1} , coming from the adjacent lower-order bit, decreasing Аi, subtracted Вi, difference R _i , loan Zi arising in this i-th bit.

определяется формулойFrom table 2 the difference of numbers

is defined by the formula

(3)

(3)

The borrowing Zi from the high order to the low order is determined by the formula

(4)

(4)

и разность

одинаковые, два сумматора по модулю два, выполнены на нейроподобных элементах DD84 и DD85 (фиг.14). При выполнении операции сложение перенос

из младшего разряда в старший вычисляется на пороговом элементе DD87. При суммировании нейроподобный элемент DD86 выполняет функцию повторителя двоичного разряда

, который подаётся на первый вход элемента. На второй вход нейроподобного элемента D86 подаётся признак операции СВ. Если выполняется операция суммирование, то сигнал СВ равен нулю. На выходе нейроподобного элемента DD86 будет значение

. При выполнении операции вычитание двоичных разрядов сигнал СВ равен единице. Нейроподобный элемент DD86 выполняет операцию инвертора, на выходе которого выполняется функция

. Заём

из старшего разряда в младший вычисляется на пороговом элементе DD87.Formulas by which the sum is calculated

and the difference

identical, two adders modulo two, made on neural-like elements DD84 and DD85 (Fig. 14). When performing an operation addition, transfer

from the least significant bit to the most significant is calculated on the threshold element DD87. When summing, the neural-like element DD86 performs the function of a binary digit repeater

which is fed to the first input of the element. At the second input of the neural-like element D86, the sign of the CB operation is supplied. If the addition operation is performed, then the CB signal is equal to zero. The output of the neural-like element DD86 will be the value

... When performing the operation subtraction of binary digits, the CB signal is equal to one. The neural element DD86 performs the operation of the inverter, at the output of which the function

... Loan

from the most significant bit to the least significant one is calculated on the threshold element DD87.

и

. Этот нейроподобный элемент выполняет операцию суммирования входных двоичных разрядов. На выходе сумматора DD84 вычисляется сумма двоичных разрядов

и

. Результат суммы поступает на первый вход нейроподобного элемента DD85. На второй вход этого элемента поступает двоичный разряд переноса

из младшего разряда в старший. На выходе нейроподобного элемента DD85 вычисляется сумма

и разность

входных двоичных разрядов

и

по формуле

. На входы нейроподобного элемента DD86 подается двоичные разряды

или

и признак выполнения арифметической операции суммирования или вычитания сигнал

. Если сигнал

равен нулю, то выполняется операция суммирование двоичных чисел. Если сигнал

равен единице, то выполняется операция вычитания двоичных чисел. При выполнении операции суммирование нейроподобный элемент DD86 выполняет операцию повторителя, на выходе формируется сигнал

по формуле

. При выполнении операции вычитания нейроподобный элемент DD86 выполняет операцию отрицание, на выходе инвертора формируется сигнал

по формуле

. Пороговый элемент DD87 вычисляет перенос

из младшего разряда в старший по формуле

. При выполнении операции вычитания на пороговом элементе DD87 вычисляется заём

из старшего разряда в младший по формуле

(фиг.14). The work of the adder-subtractor is as follows. Binary bits are fed to the inputs of the neural-like element DD84

and

... This neural-like element performs the operation of summation of the input binary digits. At the output of the DD84 adder, the sum of the binary digits is calculated

and

... The result of the sum goes to the first input of the neural-like element DD85. The second input of this element receives a carry bit

from the least significant digit to the senior. At the output of the neural-like element DD85, the sum is calculated

and the difference

input binary digits

and

according to the formula

... Binary bits are supplied to the inputs of the neural-like element DD86

or

and a sign of performing an arithmetic addition or subtraction operation signal

... If the signal

is zero, then the operation of summing binary numbers is performed. If the signal

is equal to one, then the operation of subtracting binary numbers is performed. When performing the summation operation, the neural-like element DD86 performs the repeater operation, the signal is generated at the output

according to the formula

... When performing a subtraction operation, the neural-like element DD86 performs a negation operation, a signal is generated at the output of the inverter

according to the formula

... Threshold element DD87 calculates carry

from the least significant digit to the senior according to the formula

... When performing a subtraction operation on the threshold element DD87, the loan is calculated

from the high order to the low order according to the formula

(Fig. 14).

Block 4 of the second number register contains n - binary triggers Trn, where n is the number of bits of the input number. This block is designed to store the binary code of the second number. The input information signal of the unit is the UE control signal. In parallel, all the trigger inputs receive control signals: synchronization, setting to “0”, recording and outputting the result. Before the start of operation of the adder-subtractor, all triggers of the block are reset upon arrival of the information signal UP from block 6 (Fig. 3).

The block 5 for storing the results of the BHR contains a random access memory RAM DD90, a binary counter forming the addresses of the columns of RAM - Сч1 DD88, a binary counter forming the addresses of the rows of RAM - Сч2 DD89 (Fig. 15). The input information signal of the block is the signal of the control system, which comes from the output of the control unit 6. The structure of this signal includes control signals: zeroing OB, US “0”, rectangular pulses of the GI, TI, control of the operation of the operational memory VK, Cch / Zp. Binary counters at the beginning of the device operation are zeroed by the control signals OB, US “0”, respectively. The inputs of the counters receive rectangular pulses of GI, TI. The counters form the addresses of the columns HELL STL and rows HELL CTP, which are used to record the results of logical and arithmetic operations RES, arriving at the input In of the RAM DD90 RAM. Signals to control the operation of the RAM DD90 of the crystal selection and read / write, respectively, when writing, take zero values VK = 0, C / Zp = 0 (Fig. 15).

Block 6 control is synthesized based on the GSA control algorithm (Fig. 16). The labeled HSA operation of the control unit 6 is shown in Fig. 17 where it is indicated:

Logical conditions:

X ₁ : "RESET" X ₅ : "IN IN"

X ₂ : "CON" X ₆ : "Sum M 2"

X ₃ : "DIZ" X ₇ : "EKV"

X ₄ : “IN A” X ₈ : “SUM-OUCH”

Operators:

U1: "START: = 1" U22: "BIN A: = DPCH"

U2: "OB: = 1" U23: "CUT: = RESIN A"

U3: "US" 0 ": = 1" U24: "BIN B: = UPIN B"

U4: "A10" U25: "BIN B: = DHF"

U5: "B10" U26: "CUT: = RESIN B"

U6: "BRgPch: = SU" U27: "BSumM 2: = UpSum2"

У7: "БРгВч: = УП" У28: "БСумМ 2: = ДПЧ"

U8: "БРгПч: = ДКЧ" У29: "БСумМ 2: = ДВЧ"

У9: "БРгВч: = ДКЧ" У30: "RES: = ResSumM 2"

U10: "BVLAO: = UPR" U31: "BECV: = UpEKV"

U11: “BVLAO: = DPCH” U32: “BECV: = DPCH”

U12: "BVLAO: = DHF" U33: "BECW: = DHF"

U13: "BKON: = UpKN" U34: "RES: = RezEKV"

U14: "BKON: = DPCH" U35: "BSUM-VYCH: = UPSUM-VYCH"

U15: "BKON: = DHCH" U36: "BSUM-OUCH: = DPCh"

U16: "RES: = RESCON" U37: "BSUM-OUCH: = DHF"

U17: "BDIZ: = UPDZ" U38: "RES: = ResSUM-VUCH"

U18: "BDIZ: = DPCH" U39: "VK: = 0"

U19: "BDIZ: = DHCh" U40: "ZpSch: = 0"

U20: "RES: = RESDIZ" U41: "RAM: = RES"

U21: "BIN A: = UPIN A"

Table 1

Pi-1 Ai Bi Si Pi 0 0 0 0 0 0 0 one one 0 0 one 0 one 0 0 one one 0 one one 0 0 one 0 one 0 one 0 one one one 0 0 one one one one one one

table 2

Zi + 1 Ai Bi Ri Zi 0 0 0 0 0 0 0 one one one 0 one 0 one 0 0 one one 0 0 one 0 0 one one one 0 one 0 one one one 0 0 0 one one one one one

Claims (1)

A device for bitwise calculation of logical and arithmetic operations, containing a unit for performing logical and arithmetic operations, a result storage unit, a control unit, characterized in that the following are additionally introduced: a number input unit, a first number register unit, a second number register unit, and the information output of the number input unit connected to the first information input of the register unit of the second number and to the first information input of the register unit of the first number, the second information input of which is connected to the fourth information output of the control unit, the first information output of which is connected to the second information input of the second number register unit, the information output of which is connected to the third information input of the block for performing logical and arithmetic operations, the first information input of which is connected to the information output of the register unit of the first number, the control output of the number input unit is connected to the control input of the block performing logical and arithmetic operations, the information output of which is connected to the first information input of the result storage unit, the second information input of which is connected to the second information output of the control unit, the third information output of which is connected to the second information input of the logical and arithmetic operations unit, the first and second control inputs "RESET" and "START" of the control unit are external inputs of the device for bitwise calculation of logical and arithmetic operations.

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