RU2728834C1 - Display substrate and method of its preparation, display panel and display device - Google Patents

Abstract

FIELD: image forming devices.

SUBSTANCE: display substrate (100) includes carrier substrate (10) and repeating cell (11), repeating cell (11) includes a plurality of subpixels (12), which include a first subpixel (G1) and a second subpixel (G2), color of the light emitted by light-emitting element (120a) of the first subpixel (G1) is identical to the color of light emitted by the light emitting element (120b) of the second subpixel (G2). Shape of first electrode (1201a) of voltage supply of light emission of light-emitting element (120a) of first subpixel (G1) differs from shape of first electrode (1201b) of voltage supply of light emission of light-emitting element (120b) of second subpixel (G2), and each subpixel (12) includes a light emitting element (120) and pixel circuit (121) for exciting a light emitting element (120) for emitting light, orthographic projection of first electrode (1201a) of voltage supply of light emission of light-emitting element (120a) of the first subpixel (G1) on carrier substrate (10), at least partially overlaps with orthographic projection of control terminal of excitation circuit (122a) of pixel circuit (121a) of first subpixel (G1) on carrier substrate (10). Orthographic projection of first electrode (1201b) of voltage supply of light emission of light-emitting element (120b) of the second subpixel (G2) on carrier substrate (10), at least partially overlaps orthographic projection of control contact output of exciting circuit (122b) of pixel circuit (121b) of second subpixel (G2) on carrier substrate (10).

EFFECT: proposed is display substrate and method of its preparation.

49 cl, 21 dwg

Description

The technical field to which the invention relates

[0001] Embodiments of the present disclosure relate to a display substrate, a method for preparing it, a display panel, and a display device.

State of the art

[0002] Due to the rapid development of active matrix organic light-emitting diodes (AMOLEDs) in the display field, the demand for a display effect for humans is increasing. Due to the advantages of high display quality, the range of applications for high definition display devices is becoming wider. In general, the resolution of a display device can be increased by decreasing pixel sizes and decreasing pixel spacing.

The essence of the invention

[0003] At least some embodiments of the present disclosure provide a display substrate, the display substrate includes a carrier substrate and a plurality of repeating cells on a carrier substrate, each of the plurality of repeating cells comprises a plurality of subpixels, and each of the plurality of subpixels comprises a light emitting element and a pixel a circuit for driving the light emitting element to emit light; the pixel circuit contains a driving circuit; the light emitting element includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode; the plurality of subpixels comprise a first subpixel and a second subpixel, the color of the light emitted by the light emitting element of the first subpixel is the same as the color of the light emitted by the light emitting element of the second subpixel, and the shape of the first light emitting voltage supply electrode of the light emitting element of the first subpixel is different from the shape of the first electrode of the light emitting voltage a light emitting element of the second subpixel; an orthographic projection of the first light-emitting voltage supply electrode of the light emitting element of the first subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate; and the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the second sub-pixel on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the second sub-pixel pixel circuit on the carrier substrate.

[0004] For example, in the display substrate provided by some embodiments of the present disclosure, the orthographic projection area of the first light emitting voltage supply electrode of the light emitting element of the first subpixel on the carrier substrate is different from the orthographic projection area of the first light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate.

[0005] For example, in a display substrate provided by some embodiments of the present disclosure, an area of overlapping portion between the orthographic projection of the driving terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate and the orthographic projection of the first light-emitting voltage supply electrode of the first subpixel light-emitting element on the carrier substrate constitutes a first region, and a region of overlapping portion between an orthographic projection of a driving terminal of a driving circuit of a pixel circuit of a second subpixel on a carrier substrate and an orthographic projection of a first light emitting voltage supply electrode of a light emitting element of a second subpixel on a carrier substrate constitutes a second region; and the ratio of the first region to the second region satisfies the following relationship:

Amin≤A1 / A2≤Amax,

where A1 represents the first region, A2 represents the second region, Amin represents the minimum threshold value of the ratio and is 90%, and Amax represents the maximum threshold value of the ratio and is 110%.

[0006] For example, in the display substrate provided by some embodiments of the present disclosure, the orthographic projection of the control terminal of the first subpixel pixel circuit driving circuit on the carrier substrate is within the orthographic projection of the first light emitting voltage supply electrode of the first subpixel light emitting element on the carrier substrate; and the orthographic projection of the control terminal of the second subpixel pixel circuit driving circuit on the carrier substrate is within the orthographic projection of the first light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate.

[0007] For example, in a display substrate provided by some embodiments of the present disclosure, the orthographic projection of the light emitting layer of the first subpixel light emitting element on the carrier substrate is continuous with the orthographic projection of the light emitting layer of the second subpixel light emitting element on the carrier substrate.

[0008] For example, in a display substrate provided by some embodiments of the present disclosure, the pixel circuit further comprises a first light emitting drive circuit and a second light emitting drive circuit, the driving circuit includes a control terminal, a first terminal and a second terminal, and the driving circuit is configured with the ability to provide a drive current to drive the light emitting element to emit light; the first light emitting control circuit is connected to the first driving circuit terminal and the first voltage terminal, and the first light emitting control circuit is configured to turn on or off the connection between the driving circuit and the first voltage terminal; and the second light emitting control circuit is electrically connected to the second terminal of the driving circuit and the first light emitting voltage supply electrode of the light emitting element, and the second light emitting control circuit is configured to turn on or off the connection between the driving circuit and the light emitting element.

[0009] For example, in a display substrate provided by some embodiments of the present disclosure, the first subpixel pixel circuit further comprises a first parasitic circuit, and the second subpixel pixel circuit further comprises a second parasitic circuit; the first parasitic circuit is electrically connected to the control terminal of the driving circuit of the first subpixel pixel circuit and the first electrode for supplying the light emitting voltage of the light emitting element of the first subpixel, and the first parasitic circuit is configured to control the voltage of the control terminal of the driving circuit of the first subpixel pixel circuit based on the voltage of the first supply electrode a light emitting voltage of the light emitting element of the first subpixel; and the second parasitic circuit is electrically connected to the control terminal of the driving circuit of the second subpixel pixel circuit and the first electrode for supplying the light emitting voltage of the light emitting element of the second subpixel, and the second parasitic circuit is configured to control the voltage of the control terminal of the driving circuit of the second subpixel pixel circuit based on the voltage of the first electrode supplying the light emitting voltage of the light emitting element of the second subpixel.

[0010] For example, in a display substrate provided by some embodiments of the present disclosure, the first parasitic circuit includes a first capacitor, and the first capacitor includes a first electrode and a second electrode; the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel comprises an auxiliary electrode unit, and the orthographic projection of the auxiliary electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate; and the sub-electrode unit serves as the first electrode of the first capacitor, and the control terminal of the driving circuit of the first sub-pixel is multiplexed as the second electrode of the first capacitor.

[0011] For example, in the display substrate provided by some embodiments of the present disclosure, the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel further comprises a first excitation electrode unit, and the first excitation electrode unit is electrically connected to the sub-electrode unit, and an orthographic projection of the first excitation the electrode unit on the carrier substrate, an orthographic projection of the light emitting layer of the light emitting element of the first subpixel on the carrier substrate and the orthographic projection of the second electrode for supplying the light emitting voltage of the light emitting element of the first subpixel on the carrier substrate at least partially overlap.

[0012] For example, in a display substrate provided by some embodiments of the present disclosure, the second parasitic circuit includes a second capacitor, and the second capacitor includes a first electrode and a second electrode; the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel comprises a second excitation electrode unit, and an orthographic projection of the second excitation electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the second subpixel pixel circuit on the carrier substrate; an orthographic projection of the second exciting electrode unit on the carrier substrate, an orthographic projection of the light emitting layer of the second subpixel light emitting element on the carrier substrate, and an orthographic projection of the second light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate at least partially overlap; and the second driving electrode unit is multiplexed as the first electrode of the second capacitor, and the control terminal of the driving circuit of the second subpixel is multiplexed as the second electrode of the second capacitor.

[0013] For example, in a display substrate provided by some embodiments of the present disclosure, the shape of the first excitation electrode unit is the same as that of the second excitation electrode unit, and the orthographic projection area of the first excitation electrode unit on the carrier substrate is the same as the orthographic projection area of the second excitation electrode unit on a carrier substrate.

[0014] For example, in the display substrate provided by some embodiments of the present disclosure, in each repeating cell, the first subpixel and the second subpixel are disposed in the first direction, the first direction is parallel to the surface of the carrier substrate, and in the first direction, the sub-electrode unit is disposed on to the side of the first excitation electrode unit remotely from the light emitting element of the second subpixel.

[0015] For example, in the display substrate provided by some embodiments of the present disclosure, the orthographic projection of the auxiliary electrode unit on the carrier substrate does not overlap with the orthographic projection of the light emitting layer of the light emitting element of the first subpixel on the carrier substrate.

[0016] For example, in the display substrate provided by some embodiments of the present disclosure, the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel further comprises a first connecting electrode unit, in the first direction, the first connecting electrode unit is disposed on the side of the first excitation electrode unit distantly from light emitting element of the second subpixel, the first connecting electrode unit is disposed between the auxiliary electrode unit and the first excitation electrode unit, and is electrically connected to both the auxiliary electrode unit and the first excitation electrode unit.

[0017] For example, a display substrate provided by some embodiments of the present disclosure further includes an intermediate layer in a direction perpendicular to the surface of the carrier substrate, a pixel circuit is disposed between the intermediate layer and the carrier substrate, the light emitting element is located on the side of the intermediate layer remote from the carrier substrates; and the intermediate layer comprises a first via, and the first connecting electrode unit extends to the first via and is electrically connected to the first sub-pixel pixel circuit through the first via.

[0018] For example, in the display substrate provided by some embodiments of the present disclosure, the first light-emitting voltage supply electrode of the light-emitting element of the second sub-pixel further comprises a second connecting electrode unit, and the second connecting electrode unit is electrically connected to the second drive electrode unit, and in the first direction , the second connecting electrode unit is located on the side of the second excitation electrode unit distantly from the light emitting element of the first subpixel.

[0019] For example, in a display substrate provided by some embodiments of the present disclosure, the intermediate layer comprises a second via, and the second connecting electrode block extends to the second via and is electrically connected to the second sub-pixel pixel circuit through the second via.

[0020] For example, in a display substrate provided by some embodiments of the present disclosure, the first connecting electrode unit is electrically connected to the second light emitting pixel driving circuit of the first subpixel through the first via, and the second connecting electrode unit is electrically connected to the second light emitting pixel driving circuit. circuits of the second subpixel through the second via.

[0021] For example, in a display substrate provided by some embodiments of the present disclosure, a pixel circuit includes an active semiconductor layer, an electrode gate metal layer, and a source-drain electrode metal layer, in a direction perpendicular to the carrier substrate, the active semiconductor layer is disposed between the carrier substrate and the electrode metal gate layer, and the electrode metal gate layer is disposed between the active semiconductor layer and the electrode source-drain metal layer; the first connecting electrode unit extends to the source-drain electrode metal layer of the pixel circuit through the first via; and the second connecting electrode unit extends to the source-drain electrode metal layer of the pixel circuit through the second via.

[0022] For example, in a display substrate provided by some embodiments of the present disclosure, a plurality of subpixels further comprise a third subpixel and a fourth subpixel in each repeating cell, a third subpixel and a fourth subpixel are arranged along the second direction, and in the second direction, the first subpixel and the second the subpixel is located between the third subpixel and the fourth subpixel; and the second direction is parallel to the surface of the carrier substrate, and the first direction is perpendicular to the second direction.

[0023] For example, in the display substrate provided by some embodiments of the present disclosure, the first light-emitting voltage supply electrode of the light-emitting element of the third subpixel includes a third drive electrode unit and a third connecting electrode unit, the third drive electrode unit and the third connecting electrode unit are electrically connected together and the first light-emitting voltage supply electrode of the light-emitting element of the fourth subpixel comprises a fourth driving electrode unit and a fourth connecting electrode unit, the fourth driving electrode unit and the fourth connecting electrode unit are electrically connected to each other; and the intermediate layer comprises a third via and a fourth via, the third connecting electrode unit extends to the third via and is electrically connected to the third subpixel pixel circuit through the third via, and the fourth connecting electrode unit extends to the fourth via and is electrically connected to the pixel circuit the fourth subpixel through the fourth via.

[0024] For example, in the display substrate provided by some embodiments of the present disclosure, in each repeating cell, in the first direction, the third connecting electrode unit is located on the third excitation electrode unit side distantly from the auxiliary electrode unit, and in the second direction, the third connecting electrode unit is the electrode unit is disposed on the third excitation electrode unit side adjacent to the fourth excitation electrode unit; and in the first direction, the fourth electrode unit is located on the fourth excitation electrode unit side distantly from the auxiliary electrode unit, and in the second direction, the fourth electrode unit is located on the fourth excitation electrode unit side adjacent to the third excitation electrode unit.

[0025] For example, in a display substrate provided by some embodiments of the present disclosure, the third connecting electrode unit is electrically connected to the second light emitting control circuit of the third subpixel pixel circuit through the third via, and the fourth connecting electrode unit is electrically connected to the second light emitting pixel driving circuit. circuits of the fourth subpixel through the fourth via.

[0026] For example, in a display substrate provided by some embodiments of the present disclosure, a plurality of repeating cells are disposed in a second direction to form a plurality of repeating cell groups, and a plurality of repeating cell groups are disposed in a first direction; in the first direction, the first connecting electrode unit, the second connecting electrode unit, the third connecting electrode unit, and the fourth connecting electrode unit are disposed between two adjacent groups of repeating cells; and in the first direction, at least a portion of the auxiliary electrode unit is located on the side of the auxiliary electrode unit remotely from the first excitation electrode unit and is located between two adjacent repeating cells in the repeating cell group adjacent to the repeating cell group in which the auxiliary electrode unit is located.

[0027] For example, in a display substrate provided by some embodiments of the present disclosure, the first subpixel and the second subpixel are green subpixels, the third subpixel is a red subpixel, and the fourth subpixel is a blue subpixel.

[0028] For example, in a display substrate provided by some embodiments of the present disclosure, the pixel circuit further comprises a data recording circuit, a data storage circuit, a threshold compensation circuit, and a reset circuit; the data recording circuit is electrically connected to the first terminal of the driving circuit and is configured to write the data signal to the data storage circuit under the control of the scanning signal; the data storage circuit is electrically connected to the control terminal of the driving circuit and the first voltage terminal, and is configured to store the data signal; the threshold compensation circuit is electrically connected to the control terminal of the driving circuit and the second terminal of the driving circuit, and is configured to perform the threshold compensation for the driving circuit; and the reset circuit is electrically connected to the driving circuit control terminal and the first light emitting voltage supply electrode of the light emitting element, and is configured to reset the driving circuit control terminal and the first light emitting voltage supply electrode of the light emitting element under the control of the reset command signal.

[0029] For example, in a display substrate provided by some embodiments of the present disclosure, a drive circuit includes a drive transistor, a drive circuit control terminal includes a gate electrode of a drive transistor, a first drive circuit lead includes a first drive transistor electrode, a second drive circuit lead contains the second electrode of the exciting transistor; the data recording circuit contains a data recording transistor, the data storage circuit contains a third capacitor, the threshold compensation circuit contains a threshold compensation transistor, the reset circuit contains a first reset transistor and a second reset transistor, the first light emitting control circuit contains a first light emitting control transistor, the second light emitting control circuit contains a second a light emitting control transistor, the reset control signal comprises a first reset control sub-signal and a second reset control sub-signal; the first electrode of the data recording transistor is electrically connected to the first electrode of the drive transistor, the second electrode of the data recording transistor is configured to receive a data signal, and a gate electrode of the data recording transistor is configured to receive a scan signal; the first electrode of the third capacitor is electrically connected to the first voltage terminal, and the second electrode of the third capacitor is electrically connected to the gate electrode of the driving transistor; the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the exciting transistor, the second electrode of the threshold compensation transistor is electrically connected to the gate electrode of the exciting transistor, and the gate electrode of the threshold compensation transistor is configured to receive the compensation control signal; the first electrode of the first reset transistor is configured to receive the first reset signal, the second electrode of the first reset transistor is electrically connected to the gate electrode of the driving transistor, and the gate electrode of the first reset transistor is configured to receive the first reset control sub-signal; the first electrode of the second reset transistor is configured to receive the second reset signal, the second electrode of the second reset transistor is electrically connected to the first light emitting voltage supply electrode of the light emitting element, and the gate electrode of the second reset transistor is configured to receive the second reset control sub-signal; the first electrode of the first light emitting control transistor is electrically connected to the first voltage terminal, the second electrode of the first light emitting control transistor is electrically connected to the first electrode of the driving transistor, the gate electrode of the first light emitting control transistor is configured to receive the first light emitting control signal; and the first electrode of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the second light emitting control transistor is electrically connected to the first light emitting voltage supply electrode of the light emitting element, and the gate electrode of the second light emitting control transistor is configured to receive the second light emitting control signal.

[0030] Some embodiments of the present disclosure also provide a display panel including a display substrate according to any one of the embodiments of the present disclosure.

[0031] Some embodiments of the present disclosure also provide a display device, and the display device includes a display panel according to any one of the embodiments of the present disclosure.

[0032] For example, a display device provided by some embodiments of the present disclosure further includes a driver chip, the driver chip is electrically connected to the display panel, and the driver chip is located on the first subpixel side in each repeating cell away from the second subpixel.

[0033] For example, in a display device provided by some embodiments of the present disclosure, in each repeating cell, the orthographic area of the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel on the carrier substrate exceeds the orthographic projection area of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel on a carrier substrate.

[0034] Some embodiments of the present disclosure also provide a preparation method for preparing a display substrate according to any one of the embodiments of the present disclosure, and the preparation method includes: providing a carrier substrate; and forming a plurality of repeating cells on the carrier substrate, wherein each of the plurality of repeating cells comprises a plurality of subpixels, each of the plurality of subpixels comprises a pixel circuit and a light emitting element, the light emitting element comprises a first electrode for applying a light emitting voltage, a second electrode for applying a voltage of light, and a light emitting layer between the first a light emitting voltage supply electrode and a second light emitting voltage supply electrode, a plurality of subpixels comprise a first subpixel and a second subpixel, the color of the light emitted by the light emitting element of the first subpixel is the same as the color of the light emitted by the light emitting element of the second subpixel, the shape of the first light emitting voltage supply electrode of the light emitting element the first subpixel differs from the shape of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel, the orthographic projection of the first th electrode for supplying the light voltage of the light emitting element of the first subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the first subpixel on the carrier substrate, and the orthographic projection of the first electrode for supplying the light voltage of the light emitting element of the second subpixel on the carrier substrate overlaps at least partially with the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the second subpixel on the carrier substrate.

[0035] Some embodiments of the present disclosure also provide a display substrate, and the display substrate includes a carrier substrate and a plurality of repeating cells on the carrier substrate, each of the plurality of repeating cells comprises a plurality of subpixels, each of the plurality of subpixels comprises a light emitting element and a pixel circuit for driving a light emitting element for emitting light, the pixel circuit includes a drive circuit, and the light emitting element includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode; driving circuits of the plurality of subpixels are arranged in the matrix on the carrier substrate; the plurality of subpixels include a first subpixel and a second subpixel, and the color of light emitted by the light emitting element of the first subpixel is the same as the color of light emitted by the light emitting element of the second subpixel; the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel comprises an auxiliary electrode unit, a first excitation electrode unit and a first connecting electrode unit, and the first excitation electrode unit, the auxiliary electrode unit and the first connecting electrode unit are electrically connected to each other; the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel includes a second excitation electrode unit and a second excitation electrode unit, and the second excitation electrode unit is electrically connected to the second excitation electrode unit; the sub-electrode unit is disposed on the control terminal side of the first subpixel pixel circuit driving circuit at a distance from the carrier substrate; and the second driving electrode unit is disposed on the control terminal side of the driving circuit of the pixel circuit of the second sub-pixel remotely from the carrier substrate.

[0036] For example, in the display substrate provided by some embodiments of the present disclosure, the shape of the first excitation electrode unit is different from the shape of the auxiliary electrode unit, the shape of the first excitation electrode unit is the same as that of the second excitation electrode unit, and the orthographic projection area of the first excitation electrode unit on the carrier substrate is identical to the orthographic projection area of the second exciting electrode unit on the carrier substrate.

[0037] For example, in the display substrate provided by some embodiments of the present disclosure, the shape of the first connecting electrode unit is the same as the shape of the second connecting electrode unit, and the orthographic area of the first connecting electrode unit on the carrier substrate is the same as the orthographic area of the second connecting electrode unit on a carrier substrate.

[0038] For example, in a display substrate provided by some embodiments of the present disclosure, a first subpixel pixel circuit drive circuit control terminal and a second subpixel pixel circuit drive circuit control terminal are disposed in a first direction, and in a first direction, the first electrode drive unit disposed on the side of the control terminal of the first sub-pixel pixel circuit drive circuit adjacent to the control terminal of the second sub-pixel pixel circuit drive circuit.

[0039] For example, in a display substrate provided by some embodiments of the present disclosure, in a first direction, a first drive electrode unit is disposed between a first subpixel pixel circuit drive circuit control terminal and a second subpixel pixel circuit drive circuit control terminal.

[0040] For example, in the display substrate provided by some embodiments of the present disclosure, in the first direction, the first connecting electrode unit is located on the side of the first excitation electrode unit distantly from the control terminal of the second subpixel pixel circuit driving circuit.

[0041] For example, in a display substrate provided by some embodiments of the present disclosure, in a first direction, a first connecting electrode unit is disposed between a first subpixel pixel circuit drive circuit control terminal and a second subpixel pixel circuit drive circuit control terminal.

[0042] For example, in a display substrate provided by some embodiments of the present disclosure, a first connecting electrode unit is disposed between the first drive electrode unit and the sub electrode unit in the first direction.

[0043] For example, in the display substrate provided by some embodiments of the present disclosure, in the first direction, the second connecting electrode unit is located on the control terminal side of the second subpixel pixel circuit driving circuit remotely from the control terminal of the first subpixel pixel circuit driving circuit, and the second excitation electrode unit is disposed between the second connection electrode unit and the first excitation electrode unit.

[0044] For example, in the display substrate provided by some embodiments of the present disclosure, the distance between the center of the driving pin of the first subpixel pixel circuit driving circuit and the center of the first driving electrode unit is greater than the distance between the center of the driving pin of the second subpixel pixel circuit driving circuit and the center the second exciting electrode unit.

[0045] Some embodiments of the present disclosure also provide a display substrate, the display substrate includes a carrier substrate and a plurality of repeating cells on the carrier substrate, each of the plurality of repeating cells comprises a plurality of subpixels, each of the plurality of subpixels comprises a light emitting element and a pixel circuit for driving the light emitting element for emitting light, the light-emitting element comprises a first light-emitting voltage supply electrode, a second light-emitting voltage supply electrode and a light-emitting layer between the first light-emitting voltage supply electrode and the second light-emitting voltage supply electrode, the pixel circuit comprises a drive circuit, a second light-emitting control circuit and a reset circuit, the second the light emitting control circuit is electrically connected to the second light emitting control signal line, the second terminal of the driving circuit and the first voltage supply electrode emitting light from the light emitting element, and configured, under the control of the second light emitting control signal provided by the second light emitting control signal line, to turn on or off the connection between the driving circuit and the light emitting element, the reset circuit is electrically connected to the driving circuit control terminal and the first reset control signal line and is configured to reset the drive circuit control terminal under the control of the first reset control sub-signal provided by the first reset control signal line, the second light emission control signal line and the first reset control signal line are arranged along the first direction, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, orthographic projection of the first electrode for supplying the light-emitting voltage of the light-emitting element of the first subpixel on the carrier substrate, at least e, partially overlaps with both the orthographic projection of the first reset control signal line connected to the reset circuit of the second subpixel pixel circuit on the carrier substrate and the orthographic projection of the second light emitting control signal line connected to the second light emitting control circuit of the first subpixel pixel circuitry on the carrier substrate and the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the second light control signal line connected to the second light-emitting control circuit of the second subpixel pixel circuit on the carrier substrate.

[0046] For example, in a display substrate provided by some embodiments of the present disclosure, the pixel circuit further comprises a data recording circuit, the data recording circuit is electrically connected to the first terminal of the driving circuit and the first scanning signal line, and is configured to write a data signal to the driving circuit. a driving circuit terminal under the control of a scan signal provided by the first scan signal line in the first direction, the first scan signal line is located between the second light control signal line and the first reset control signal line, the first light emission voltage supply electrode of the light emitting element of the first sub-pixel and the first supply electrode light emitting voltages of the light emitting element of the second subpixel are arranged along the first direction, and in the first direction, the first scanning signal line connected to the data recording circuit a second sub-pixel pixel circuit is disposed between the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel and the first light-emitting voltage supply electrode of the light emitting element of the second sub-pixel.

[0047] For example, in the display substrate provided by some embodiments of the present disclosure, the reset circuit is further electrically connected to the first power supply and reset signal line, the reset circuit is configured to reset the control pin of the drive circuit according to the first reset signal provided by the first line power supply and reset signals under the control of the first reset control sub-signal provided by the first reset control signal line in the first direction, the first power supply and reset signal line is located on the side of the first reset control signal line distantly from the second light emission control signal line, and an orthographic projection of the first supply electrode the light emitting voltage of the light emitting element of the first subpixel on the carrier substrate additionally at least partially overlaps with the orthographic projection of the first signal line power supply and reset, connected to the reset circuit of the pixel circuit of the second subpixel on the carrier substrate.

[0048] For example, in the display substrate provided by some embodiments of the present disclosure, all of the second light control signal line, the first reset control signal line, the first scan signal line, and the first power and reset signal line continue in the second direction, and the second direction is perpendicular to the first direction.

[0049] For example, in the display substrate provided by some embodiments of the present disclosure, the second light control signal line, the first reset control signal line, the first scan signal line, and the first power and reset signal line are in parallel with each other.

[0050] For example, in the display substrate provided by some embodiments of the present disclosure, the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel includes an auxiliary electrode unit, a first excitation electrode unit and a first connection electrode unit, a first excitation electrode unit, an auxiliary electrode unit, and the first connecting electrode unit is electrically connected to each other and disposed in the first direction, the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel comprises a second exciting electrode unit and a second connecting electrode unit, the second exciting electrode unit and the second connecting electrode unit are electrically connected and disposed in the first direction , in the first direction, the first connecting electrode unit and the auxiliary electrode unit are located on the side of the first excitation electrode unit At a distance from the second excitation electrode unit, the first connecting electrode unit is located between the auxiliary electrode unit and the first excitation electrode unit, the second connecting electrode unit is located on the side of the second excitation electrode unit remotely from the first excitation electrode unit, an orthographic view of the first excitation electrode unit on a carrier substrate overlaps at least partially with the orthographic projection of the first reset control signal line connected to the reset circuit of the second subpixel pixel circuit on the carrier substrate, and with the orthographic projection of the first power and reset signal line connected to the reset circuit of the second subpixel pixel circuit on the carrier substrate the orthographic projection of the first connecting electrode unit on the carrier substrate overlaps at least partially with the orthographic projection of the second light control signal line, connected to the second light emitting control circuit of the first subpixel pixel circuit on the carrier substrate, in the first direction, the auxiliary electrode unit is located on the side of the second light emission control signal line connected to the second light emitting control circuit of the first subpixel pixel circuit distantly from the first electrode for supplying the light voltage of the light emitting element of the second sub-pixel, the orthographic projection of the second connecting electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the second light emitting control signal line connected to the second light emitting control circuit of the second subpixel pixel circuit on the carrier substrate, and in the first direction, the second driving electrode unit is disposed between the second light emitting control signal line connected to the second light emitting control circuit of the second subpixel pixel circuit and the first or a scanning signal connected to the data recording circuit of the pixel circuit of the second subpixel.

[0051] For example, in a display substrate provided by some embodiments of the present disclosure, the color of light emitted by the light emitting element of the first subpixel is the same as the color of light emitted by the light emitting element of the second subpixel, and the shape of the first light emitting voltage supply electrode of the light emitting element of the first subpixel differs from the shape of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel.

Brief Description of Drawings

[0052] To clearly illustrate the technical solutions of the embodiments of the present disclosure, drawings of the embodiments are briefly described below; it is obvious that the described drawings relate only to some embodiments of the present disclosure and, therefore, do not limit the present disclosure.

[0053] FIG. 1 is a schematic structural diagram of a repeating pixel cell in a pixel arrangement;

[0054] FIG. 2 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure;

[0055] FIG. 3A is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure;

[0056] FIG. 3B is a schematic block diagram of a first subpixel pixel circuit provided by some embodiments of the present disclosure;

[0057] FIG. 3C is a schematic block diagram of a second sub-pixel pixel circuit provided by some embodiments of the present disclosure;

[0058] FIG. 4A-4E are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure;

[0059] FIG. 5A is a planar schematic diagram of a display substrate provided by some embodiments of the present disclosure;

[0060] FIG. 5B is a flat schematic diagram of a repeating cell provided by some embodiments of the present disclosure;

[0061] FIG. 6A is a flat schematic diagram of another repeating cell provided by some embodiments of the present disclosure;

[0062] FIG. 6B is a layout diagram of a display substrate provided by some embodiments of the present disclosure;

[0063] FIG. 6C is a schematic cross-sectional diagram of a line L1-L1 'in FIG. 6B;

[0064] FIG. 6D is a schematic structural diagram in cross-section of line L2-L2 'in FIG. 6B;

[0065] FIG. 6E is a planar schematic diagram of another display substrate provided through some embodiments of the present disclosure;

[0066] FIG. 7 is a partial schematic structural diagram of a display panel provided by some embodiments of the present disclosure;

[0067] FIG. 8A is a schematic block diagram of a display device provided by some embodiments of the present disclosure;

[0068] FIG. 8B is a schematic structural diagram of a display device provided by some embodiments of the present disclosure; and

[0069] FIG. 9 is a flowchart of a preparation method for preparing a display substrate provided by an embodiment of the present disclosure.

Detailed description of the invention

[0070] To ensure that the objectives, technical details, and advantages of embodiments of the present disclosure are apparent, technical solutions of the embodiments are to be described clearly and intelligibly in connection with the drawings associated with the embodiments of the present disclosure. Obviously, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment (s) without inventive effort, which should be within the scope of the present disclosure.

[0071] Unless otherwise indicated, all technical and scientific terms used in this document have the same meanings as commonly understood by those of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", etc., as used in this disclosure, are not intended to indicate any sequence, magnitude or significance, but to distinguish between the various components. In addition, such singular references are intended not to limit the number, but to indicate the presence of at least one. The terms "comprise", "comprising", "comprise", "including", etc. are intended to indicate that the elements or objects before these terms encompass the elements or objects and their equivalents listed after these terms, but do not exclude other elements or objects. The phrases "connect", "connected", etc. do not intend to define a physical connection or a mechanical connection, but may contain an electrical connection, directly or indirectly. "On", "under", "right", "left", etc. are used only to indicate the relative positional relationship, and when the position of the object that is being described changes, the relative positional relationship may change accordingly.

[0072] In order to maintain clarity and accuracy of the following description of embodiments of the present disclosure, detailed descriptions of some known functions and known components are omitted from the present disclosure.

[0073] FIG. 1 is a schematic structural diagram of a repeating pixel cell in a pixel arrangement; as shown in FIG. 1, a pixel arrangement includes a plurality of repeating pixel cells 400, and a plurality of repeating pixel cells 400 are arranged in a matrix along a direction 405 and a direction 406. Each repeating pixel cell 400 includes a red sub-pixel 401, a blue sub-pixel 402, a first green sub-pixel 403 and a second green subpixel 404. As shown in FIG. 1, the red subpixel 401 and the blue subpixel 402 are located in the direction 405, the first green subpixel 403 and the second green subpixel 404 are located in the direction 406 and in the direction 405, the first green subpixel 403 and the second green subpixel 404 are located between the red subpixel 401 and the blue subpixel 402 ...

[0074] In the process of detecting backlight for each sub-pixel in the pixel arrangement as shown in FIG. 1, the luminance of the first green subpixel 403 and the luminance of the second green subpixel 404 are inconsistent, thereby leading to the problem of skipping the detection of bright spots, i. E. some green subpixels cannot be detected. According to the experimental results, the luminance of the first green sub-pixel 403 is higher than that of the second green sub-pixel 404, thereby causing the phenomenon that the luminance of the first green sub-pixel 403 is relatively high, while the luminance of the second green sub-pixel 404 is relatively low.

[0075] In each subpixel, parasitic capacitance occurs between the anode of the light emitting element and the gate electrode of the driving transistor, and the parasitic capacitance must affect the luminance of the light emitting from the light emitting element, and the larger the parasitic capacitance, the weaker the luminance of the light. The lower the parasitic capacitance, the stronger the brightness of the light radiation. According to the analysis of the pixel arrangement, in this pixel arrangement, the gate electrode of the driving transistor in the pixel circuit for driving the first green subpixel 403 is not blocked by the light emitting element anode of the first green subpixel 403, while the gate electrode of the driving transistor in the pixel circuit for driving the second the green subpixel 404 is blocked by the anode in the light emitting element of the second green subpixel 404. Thus, there is no parasitic capacitance between the gate electrode of the drive transistor of the first green subpixel 403 and the light emitting element of the first green subpixel 403, or there is no parasitic capacitance between the gate electrode of the drive subpixel 403 of the first green the light emitting element of the first green subpixel 403 is less than parasitic capacitance between the gate electrode of the driving transistor of the second green subpixel 404 and the light emitter the first element of the second green subpixel 404, i.e. parasitic capacitance between the drive transistor gate of the first green subpixel 403 and the light emitting element of the first green subpixel is significantly different from the parasitic capacitance between the drive transistor gate electrode of the second green subpixel 404 and the light emitting element of the second green subpixel 404, thereby resulting in a green subpixel luminance difference between the first subpixel 403 and a second green subpixel 404 in each repeating cell, which seriously affects the display effect.

[0076] At least some embodiment of the present disclosure provides a display substrate and a method for preparing it, a display panel, and a display device. In the display substrate, the first subpixel light emitting element covers the gate electrode of the first subpixel drive transistor, and the second subpixel drive transistor light emitting element also covers the second subpixel drive transistor gate, so as to reduce the parasitic capacitance difference between the first subpixel light emitting element of the first subpixel drive and the gate subpixel drive transistor and parasitic capacitance between the light emitting element of the second subpixel and the gate electrode of the drive transistor of the second subpixel, and achieve identical pixel luminance of the first subpixel and the pixel luminance of the second subpixel, thereby improving display uniformity and display effect and solving the problem of pixel luminance difference of the display panel. In addition, the display substrate has a simple structure, is easy to design and manufacture, and has a low cost.

[0077] Several embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0078] FIG. 2 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure; FIG. 3A is a planar schematic diagram of a display substrate provided by some embodiments of the present disclosure, FIG. 3A is a circuit block diagram of a pixel circuit provided by some embodiments of the present disclosure, FIG. 3B is a schematic structural diagram of a first sub-pixel pixel circuit provided by some embodiments of the present disclosure, and FIG. 3C is a schematic block diagram of a second sub-pixel pixel circuit provided by some embodiments of the present disclosure.

[0079] For example, as shown in FIG. 2, a display substrate 100 provided by an embodiment of the present disclosure includes a carrier substrate 10 and a plurality of repeating cells 11 on a carrier substrate 10, each repeating cell 11 includes a plurality of subpixels 12. Each subpixel 12 includes a light emitting element 120 and a pixel circuit 121, a pixel circuit 121 is used to drive the light emitting element 120 to emit light, and the pixel circuit 121 includes a drive circuit 122.

[0080] For example, the display substrate 100 may be applied to a display panel such as an active matrix organic light emitting diode (AMOLED) display panel and the like. The display substrate 100 may be a matrix substrate.

[0081] For example, the carrier substrate 10 may be a suitable substrate such as a glass substrate, a quartz substrate, and a plastic substrate, etc.

[0082] For example, the light emitting element 120 of each subpixel 12 includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode.

[0083] For example, the plurality of subpixels 12 include a first subpixel G1 and a second subpixel G2.

[0084] For example, as shown in FIG. 3A, the pixel circuit 121 further includes a first light emitting drive circuit 123 and a second light emitting drive circuit 124. The drive circuit 122 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a drive current for driving the light emitting element 120 to emit light. For example, the first light emitting control circuit 123 is connected to the first terminal of the driving circuit 122 and the first voltage terminal VDD and is configured to turn on or off the connection between the driving circuit 122 and the first voltage terminal VDD, and the second light emitting control circuit 124 is electrically connected to the second a terminal of the driving circuit 122 and a first light-emitting voltage supply electrode of the light-emitting element 120, and configured to turn on or off the connection between the driving circuit 122 and the light-emitting element 120.

[0085] For example, as shown in FIG. 3B and 3C, the pixel circuit 121a of the first subpixel G1 further includes the first parasitic circuit 125a, and the pixel circuit 121b of the second subpixel G2 further includes the second parasitic circuit 125b. For example, the first parasitic circuit 125a is electrically connected to the control terminal of the driving circuit 122a of the pixel circuit 121a of the first subpixel G1 and the first light-emitting voltage supply electrode of the light-emitting element 120a of the first subpixel G1, and is configured to control the voltage of the control terminal of the driving circuit 122a of the first subpixel pixel circuit 121a G1 based on the voltage of the first light emitting voltage supply electrode of the light emitting element 120a of the first subpixel G1. The second parasitic circuit 125b is electrically connected to the driving terminal of the driving circuit of the pixel circuit 121b of the second subpixel G2 and the first light-emitting voltage supply electrode of the light-emitting element 120b of the second subpixel G2, and is configured to control the voltage of the control terminal of the driving circuit 122b of the pixel circuit 121b of the second subpixel G2 based on the voltage of the first light-emitting voltage supply electrode of the light-emitting element 120b of the second subpixel G2.

[0086] It should be noted that the pixel circuit 121 may further include a parasitic circuit, and the parasitic circuit is not shown in FIG. 3A, for example, the first parasitic circuit in the pixel circuit of the first subpixel G1 and the second parasitic circuit in the pixel circuit of the second subpixel G2 are not shown in FIG. 3A.

[0087] For example, as shown in FIG. 3A, the pixel circuit 121 further includes a data recording circuit 126, a data storage circuit 127, a threshold compensation circuit 128, and a reset circuit 129. The data recording circuit 126 is electrically connected to the first terminal of the drive circuit 122 and is configured to write the data signal to the data storage circuit 127 under the control of the scan signal; the data storage circuit 127 is electrically connected to the control terminal of the driving circuit 122 and the first voltage terminal VDD, and is configured to store the data signal; the threshold compensation circuit 128 is electrically connected to the control terminal of the driving circuit 122 and the second terminal of the driving circuit 122, and is configured to perform the threshold compensation for the driving circuit 122; and the reset circuit 129 is electrically connected to the control terminal of the drive circuit 122 and the first light-emitting voltage supply electrode of the light-emitting element 120, and is configured to reset the control terminal of the drive circuit 122 and the first light-emitting voltage supply electrode of the light-emitting element 120 under the control of the reset command signal.

[0088] For example, as shown in FIG. 3A, the drive circuit 122 includes a drive transistor T1, the control terminal of the drive circuit 122 includes a gate electrode of the drive circuit T1, the first contact lead of the drive circuit 122 includes a first electrode of the drive transistor T1, and the second lead of the drive circuit 122 includes into itself the second electrode of the driving transistor T1.

[0089] For example, as shown in FIG. 3A, the data recording circuit 126 includes a data recording transistor T2, the storage circuit 127 includes a third capacitor C2, a threshold compensation circuit 128 includes a threshold compensation transistor T3, the first light emitting control circuit 123 includes a first light emitting control transistor T4 , the second light emitting control circuit 124 includes a second light emitting control transistor T5, the reset circuit 129 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first reset control sub-signal and a second reset control sub-signal.

[0090] For example, as shown in FIG. 3A, the first electrode of the data recording transistor T2 is electrically connected to the first electrode of the drive transistor T1, the second electrode of the data recording transistor T2 is electrically connected to the data line Vd to receive a data signal, and the gate electrode of the data recording transistor T2 is electrically connect to the first sweep signal line Ga1 to receive a sweep signal; the first electrode of the third capacitor C2 is electrically connected to the first voltage terminal VDD, and the second electrode of the third capacitor C2 is electrically connected to the gate electrode of the driving transistor T1; the first electrode of the compensation threshold transistor T3 is electrically connected to the second electrode of the excitation transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate electrode of the excitation transistor T1, and the gate electrode of the threshold compensation transistor T3 is electrically connected to the second scan signal line Ga2 to receive a compensation control signal; the first electrode of the first reset transistor T6 is electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the second electrode of the first reset transistor T6 is electrically connected to the gate electrode of the driving transistor T1, and the gate electrode of the first reset transistor T6 is configured electrically connect to the first reset control signal line Rst1 to receive the first reset control sub-signal; the first electrode of the second reset transistor T7 is electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first light-emitting voltage supply electrode of the light-emitting element 120, and the gate electrode of the second reset transistor T7 configured to be electrically connected to the second reset control signal line Rst2 to receive a second reset control sub-signal; the first electrode of the first light emitting control transistor T4 is electrically connected to the first voltage terminal VDD, the second electrode of the first light emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate electrode of the first light emitting control transistor T4 is electrically connected to the first signal line EM1 control light emission to receive the first control signal light emission; the first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T5 is electrically connected to the first light emitting voltage supply electrode of the light emitting element 120, and the gate electrode of the second light emitting control transistor T5 is configured to be electrically connected to the second light emitting control transistor T5 a light emission control signal line EM2 to receive a second light emission control signal; and the second light-emitting voltage supply electrode of the light-emitting element 120 is electrically connected to the second voltage terminal VSS.

[0091] For example, as shown in FIG. 3B, for the first subpixel G1, the first parasitic circuit 125a includes a first capacitor C11, and the first capacitor C11 includes a first electrode CC3a and a second electrode CC4a. The first electrode CC3a of the first capacitor C11 is electrically connected to the first light emitting voltage supply electrode of the light emitting element 120a of the first subpixel G1, and the second electrode CC4a of the first capacitor C11 is electrically connected to the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1.

[0092] For example, as shown in FIG. 3C, for the second subpixel G2, the second parasitic circuit 125b includes a second capacitor C12, and the second capacitor C12 includes a first electrode and a second electrode. The first electrode of the second capacitor C12 is electrically connected to the first light-emitting voltage supply electrode of the light emitting element 120b of the second subpixel G2, and the second electrode of the second capacitor C12 is electrically connected to the gate electrode of the driving transistor T1 of the pixel circuit 121b of the second subpixel G2.

[0093] For example, the capacitance value of the first capacitor C11 may be the same as the capacitance value of the second capacitor C12, such that the pixel luminance of the first subpixel G1 can be matched with the pixel luminance of the second subpixel G2, and display uniformity and display effect can be improved.

[0094] For example, one of the first voltage terminal VDD and the second voltage terminal VSS is a high voltage terminal, and the other of the first voltage terminal VDD and the second voltage terminal VSS is a low voltage terminal. For example, in an embodiment as shown in FIG. 3A, the first voltage terminal VDD is a voltage source to output a fixed first voltage, and the first voltage is a positive voltage; and the second voltage terminal VSS may be a voltage source to output a constant second voltage, the second voltage is a negative voltage, and the like. For example, in some examples, the second voltage terminal VSS may be grounded.

[0095] For example, for the first subpixel G1 as shown in FIG. 3B, the pixel circuit 121a of the first sub-pixel G1 further includes a data recording circuit 126a, a data storage circuit 127a, a threshold compensation circuit 128a, and a reset circuit 129a; and for the second subpixel G2 as shown in FIG. 3C, the pixel circuit 121b of the second subpixel G2 further includes a data recording circuit 126b, a data storage circuit 127b, a threshold compensation circuit 128b, and a reset circuit 129b. The connection relationship and function of each element in each circuit of the first subpixel G1 pixel circuit 121a and the second subpixel G2 pixel circuit 121b are similar to the example described above with respect to FIG. 3A, and repetition is not given here again.

[0096] For example, as shown in FIG. 3A, the sweep signal may be identical to the compensation control signal, i. E. the gate electrode of the data recording transistor T2 and the gate electrode of the threshold compensation transistor T3 may be electrically connected to an identical signal line such as the first scan signal line Ga1 to receive an identical signal (e.g., a scan signal), at this time, the display substrate 100 may not contain a second sweep signal line Ga2, thereby reducing the number of signal lines. As another example, the gate electrode of the data recording transistor T2 and the gate electrode of the compensation threshold transistor T3 may be electrically connected to different signal lines, i.e. the gate electrode of the data recording transistor T2 is electrically connected to the first scanning signal line Ga1, the gate electrode of the threshold compensation transistor T3 is electrically connected to the second scanning signal line Ga2, and the signal transmitted by the first scanning signal line Ga1 is the same as the signal transmitted by the second scanning signal line Ga2 sweep signals.

[0097] It should be noted that the scanning signal and the compensation control signal can also be different so that the gate electrode of the data writing transistor T2 and the compensation threshold transistor T3 can be separately and independently controlled, thereby increasing the flexibility of the pixel circuit control.

[0098] For example, as shown in FIG. 3A-3B, the first light emitting control signal may be the same as the second light emitting control signal, i. E. the gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 may be electrically connected to the same signal line such as the first light emitting control signal line EM1 to receive the same signal (for example, the first light emitting control signal), and at this time, the display substrate 100 may not contain the second light emission control signal line EM2, thereby reducing the number of signal lines. As another example, the gate electrode of the first light emitting control transistor T4 and the gate electrode of the second light emitting control transistor T5 may also be electrically connected to different signal lines, i. E. the gate electrode of the first light emitting control transistor T4 is electrically connected to the first light emitting control signal line EM1, the gate electrode of the second light emitting control transistor T5 is electrically connected to the second light emitting control signal line EM2, and the signal transmitted by the first light control signal line EM1 is the same as the signal, transmitted by the second light control signal line EM2.

[0099] It should be noted that in the case where the first light emitting control transistor T4 and the second light emitting control transistor T5 are different types of transistors, for example, in the case where the first light emitting control transistor T4 is a p-channel transistor and the second light emitting control transistor the driving transistor T5 is an n-channel transistor, the first light emitting control signal and the second light emitting control signal may also be different, and the embodiment of the present disclosure is not limited to this case.

[00100] For example, the first reset control sub-signal may be the same as the second reset control sub-signal, i. E. the gate electrode of the first reset transistor T6 and the gate electrode of the second reset transistor T7 may be electrically connected to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (eg, the first reset control sub-signal). At this time, the display substrate 100 may not contain the second reset control signal line Rst2, thereby reducing the number of signal lines. As another example, the gate electrode of the first reset transistor T6 and the gate electrode of the second reset transistor T7 may be electrically connected to different signal lines, i. E. the gate electrode of the first reset control signal line Rst1 is electrically connected to the first reset control signal line Rst1, the gate electrode of the second reset control signal line Rst2 is electrically connected to the second reset control signal line Rst2, and the signal transmitted by the first reset control signal line Rst1 is the same as the signal transmitted by the second line Rst2 of the reset control signals. It should be noted that the first reset control sub-signal and the second reset control sub-signal may also be different.

[00101] For example, in some examples, the second reset control sub-signal may be identical to the sweep signal, i. E. the gate electrode of the second reset transistor T7 may be electrically connected to the first scan signal line Ga1 to receive the scan signal as the second reset control sub-signal.

[00102] For example, the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be constant reference voltage terminals to output constant constant reference voltages. The first pin Vinit1 of the reset power supply and the second pin Vinit2 of the reset power may be high voltage pins or low voltage pins, provided that the first pin Vinit1 of the reset power supply and the second pin Vinit2 of the reset power can provide the first reset signal and the second a reset signal to reset the gate electrode of the driving transistor T1 and the first light-emitting voltage supply electrode of the light-emitting element 120, and the present disclosure is not limited thereto.

[00103] It should be noted that the drive circuit 122, the data recording circuit 126, the data storage circuit 127, the threshold compensation circuit 128, and the reset circuit 129 in the pixel circuit as shown in FIG. 3A-3B are schematic only. The specific structures of the driving circuit 122, the data recording circuit 126, the data storage circuit 127, the threshold compensation circuit 128, and the reset circuit 129 can be set according to actual application requirements, and the embodiment of the present disclosure is not particularly limited to this case.

[00104] For example, according to the characteristics of transistors, transistors may be classified into n-channel transistors and p-channel transistors. For clarity, embodiments of the present disclosure specifically represent the technical outline of the present disclosure by considering the case in which the transistors are p-channel transistors (eg, p-channel MOS transistors) as an example, i. E. in the description of the present disclosure, the driving transistor T1, the data recording transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6, the second reset transistor T7, etc. can be p-channel transistors. However, the transistors of the embodiments of the present disclosure are not limited to p-channel transistors, and those skilled in the art may also use n-channel transistors (e.g., n-channel MOS transistors) to achieve the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.

[00105] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with identical characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or thin-film transistors based on polycrystalline silicon, etc. The source electrode and the drain electrode of the transistor may be symmetrical in structure, so that the source electrode and the drain electrode of the transistor may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish two electrodes of transistors except for a gate electrode serving as a gate electrode, one of the two electrodes is directly described as a first electrode, and the other of the two electrodes is described as a second electrode, so that the first electrodes and second electrodes all or part of the transistors in the embodiment of the present disclosure are interchangeable as needed.

[00106] It should be noted that in addition to specifying positions, connection relationships, structures and types, etc. respective circuits (e.g., drive circuit 122a, first light emitting drive circuit 123a, second light emitting drive circuit 124a, data recording circuit 126a, storage circuit 127a, threshold compensation circuit 128a, and reset circuit 129a, etc.) in the pixel circuit 121a of the first G1 subpixels are identical to connection relationships, structures and types, etc. appropriately corresponding circuits (e.g., drive circuit 122b, first light emitting drive circuit 123b, second light emitting drive circuit 124b, data recording circuit 126b, data storage circuit 127b, threshold compensation circuit 128b and reset circuit 129b, etc.) in the pixel circuit 121b of the second subpixel G2, that is, for example, the structure and type of the drive circuit 122a in the pixel circuit 121a of the first subpixel G1 are identical to the structure and type of the drive circuit 122b in the pixel circuit 121b of the second subpixel G2. In addition, corresponding circuits in the pixel circuit 121a of the first subpixel G1 and appropriately corresponding circuits in the pixel circuit 121b of the second subpixel G2 can be prepared simultaneously using the same process, for example, the drive circuit 122a in the pixel circuit 121a of the first subpixel G1 and the drive circuit 122b in the pixel the second subpixel G2 circuit 121b can be prepared simultaneously using the same patterning process.

[00107] It should be noted that as shown in FIG. 3B, corresponding signal lines electrically connected to corresponding circuits in the pixel circuit 121a of the first subpixel G1 are a first scanning signal line Ga1a, a second scanning signal line Ga2a, a first reset control signal line Rst1a, a second reset control signal line Rst2a, a first terminal Reset power supply Vinit1a, a second reset power supply terminal Vinit2a, a first light control signal line EM1a, a second light control signal line EM2a, and a data transmission line Vd, respectively. As shown in FIG. 3C, corresponding signal lines electrically connected to corresponding circuits in the pixel circuit 121b of the second subpixel G2 are a first scan signal line Ga1b, a second scan signal line Ga2b, a first reset control signal line Rst1b, a second reset control signal line Rst2b, a first terminal Reset power supply Vinit1b, a second reset power supply terminal Vinit2b, a first light control signal line EM1b, a second light control signal line EM2b, and a data transmission line Vd, respectively.

[00108] It should be noted that in embodiments of the present disclosure, in addition to the 7T2C structure as shown in FIG. 3A (i.e., including seven transistors, one capacitor and one parasitic capacitor), the subpixel pixel circuit may also have a structure including other numbers of transistors, such as a 6T2C structure or a 9T2C structure, an embodiment of the present disclosure is not limited to this case.

[00109] FIG. 4A-4E are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure. Next, the positional relationship of respective circuits in a pixel circuit on a circuit board will be described with reference to FIG. 4A-4E. Examples as shown in FIG. 4A to 4E, take the pixel circuit 121a of the first subpixel G1 as an example. As shown in FIG. 3B, the pixel circuit 121a of the first subpixel G1 includes a drive transistor T1, a data recording transistor T2, a threshold compensation transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a first reset transistor T6 and a second reset transistor T7, a first reset capacitor T7 and the third capacitor C2. FIG. 4A-4E also show the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first power supply and reset line Init1a of the first reset power supply pin Vinit1a, the second power signal line Init2a and resetting the second reset power supply terminal Vinit2a, the first light control signal line EM1a, the second light control signal line EM2a, the data transmission lines Vd, the first power supply signal line VDD1 and the second power supply signal line VDD2 of the first voltage terminal VDD, which are connected to the pixel circuit 121a of the first subpixel G1, and the first power signal line VDD1 and the second power signal line VDD2 are electrically connected to each other. It should be noted that, in the examples, as shown in FIG. 4A-4E, the first scanning signal line Ga1a and the second scanning signal line Ga2a are the same signal line, the first power and reset signal line Init1a and the second power and reset signal line Init2a are the same signal line, the first reset control signal line Rst1a and the second the reset control signal line Rst2a is the same signal line, and the first light control signal line EM1a and the second light control signal line EM2a are the same signal line.

[00110] For example, FIG. 4A shows the active semiconductor layer 310 of the pixel circuit 121a. The active semiconductor layer 310 can be patterned using a semiconductor material. The active semiconductor layer 310 can be used to manufacture the active layers of the above drive transistor T1, the data recording transistor T2, the threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7. and each of the active layers may include a source portion, a drain portion, and a channel portion between the source portion and a drain portion. For example, the active layers of the respective transistors are provided as a whole.

[00111] For example, the active semiconductor layer 310 may be prepared with amorphous silicon, polysilicon, oxide semiconductor material, and the like. It should be noted that the above-mentioned source portion and drain portion may be n-type doped or p-type doped portions.

[00112] For example, the electrode metal gate layer of the pixel circuitry 121a may include a first conductive layer and a second conductive layer. An insulating gate layer (not shown) is formed on the active semiconductor layer 310 to protect the active semiconductor layer 310. FIG. 4B shows the first conductive layer 320 of the pixel circuit 121a, the first conductive layer 320 is disposed on the insulating gate layer so that it is insulated from the active semiconductor layer 310. The first conductive layer 320 may include a second electrode CC2a of a third capacitor C2, a first signal line Ga1a sweep, second sweep signal line Ga2a, first reset control signal line Rst1a, second reset control signal line Rst2a, first light control signal line EM1a, second light control signal line EM2a and gate electrodes of drive transistor T1, data recording transistor T2, threshold compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6, and the second reset transistor T7.

[00113] For example, as shown in FIG. 4B, the gate electrode of the data recording transistor T2 may be a part in which the first scanning signal line Ga1a overlaps the active semiconductor layer 310, the gate electrode of the first light emitting control transistor T4 may be a first part in which the first light control signal line EM1a / second line Light control signal EM2a overlaps the active semiconductor layer 310, the gate electrode of the second light emitting control transistor T5 may be a second portion in which the first light control signal line EM1a / second light control signal line EM2a overlaps the active semiconductor layer 310, the gate electrode of the first reset transistor T6 may be the first part in which the first reset control signal line RS1a / the second reset control signal line Rst2a overlaps the active semiconductor layer 310, the gate electrode of the second th reset transistor T7 is a second part in which the first reset control signal line Rst1a / the second reset control signal line Rst2a overlaps the active semiconductor layer 310, the threshold compensation transistor T3 may be a thin film transistor with a two-gate structure, the first gate electrode of the threshold compensation transistor T3 may be a part in which the second scan signal line Ga2a overlaps the active semiconductor layer 310, and the second gate electrode of the threshold compensation transistor T3 may be a part in which a protruding portion protruding from the second scan signal line Ga2a overlaps the active semiconductor layer 310. As shown in FIG. 3B and 4B, the gate electrode of the driving transistor T1 may be the second electrode CC4a of the first capacitor C11 and the second electrode CC2a of the third capacitor C2.

[00114] It should be noted that the corresponding dashed rectangular boxes in FIG. 4A show respective portions in which the first conductive layer 320 overlaps the active semiconductor layer 310.

[00115] For example, as shown in FIG. 4B, first scan signal line Ga1a / second scan signal line Ga2a, first reset control signal line Rst1a / second reset control signal line Rst2a, and first light control signal line EM1a / second light control signal line EM2a are arranged along the first X direction. First line Ga1a sweep / second sweep signal line Ga2a is disposed between the first reset control signal line Rst1a / second reset control signal line Rst2a and the first light control signal line EM1a / second light control signal line EM2a.

[00116] For example, in the first X direction, the second electrode CC4a of the first capacitor C11 (i.e., the second electrode CC2a of the third capacitor C2) is located between the first scanning signal line Ga1a / second scanning signal line Ga2a and the first light control signal line EM1 / second light control signal line EM2a. A protruding part protruding from the second scanning signal line Ga2a is located on the side of the second scanning signal line Ga2a distantly from the first light control signal line EM1a / second light control signal line EM2a.

[00117] For example, as shown in FIG. 4A, in the first direction X, the gate electrode of the data recording transistor T2, the gate electrode of the threshold compensation transistor T3, the gate electrode of the first reset transistor T6, and the gate electrode of the second reset transistor T7 are disposed on the first side of the gate electrode of the driving transistor T1, the gate electrode of the first light-emitting control transistor T4 and the gate electrode of the second light-emitting driving transistor T5 are disposed on the second side of the gate electrode of the driving transistor T1, and, for example, in the example, as shown in FIG. 6A to 6E, the first side and the second side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1 are opposite sides of the gate electrode of the driving transistor T1 in the first X direction. For example, as shown in FIG. 4A to 4E, the first side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1 may be the upper side of the gate electrode of the driving transistor T1, and the second side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1 may be the lower side of the gate electrode transistor T1.

[00118] For example, in some embodiments, as shown in FIG. 4A to 4E, in the second Y direction, the gate electrode of the data recording transistor T2 and the gate electrode of the first light emitting control transistor T4 are disposed on the third side of the gate electrode of the driving transistor T1, the first gate electrode of the threshold compensation transistor T3, the gate electrode of the second light emitting control transistor T5, and the gate an electrode of the second reset transistor T7 is disposed on the fourth side of the gate electrode of the driving transistor T1, for example, in the example shown in FIG. 4A to 4E, the third side and the fourth side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1 are opposite sides of the gate electrode of the driving transistor T1 in the second Y direction, for example, as shown in FIG. 4A to 4E, the third side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1 may be the right side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1, and the fourth side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel is the left side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1.

[00119] For example, a first insulating layer (not shown) is formed on the first conductive layer 320 to protect the first conductive layer 320. FIG. 4C shows the second conductive layer 330 of the pixel circuit 120a. The second conductive layer 330 includes a first electrode CC1a of the third capacitor C2, a first power and reset signal line Init1a, a second power and reset signal line Init2a, and a second power signal line VDD2. The second power supply signal line VDD2 is integrally formed with the first electrode CC1a of the third capacitor C2. The first electrode CC1a of the third capacitor C2 and the second electrode CC2a of the third capacitor C2 at least partially overlap so as to form the third capacitor C2.

[00120] For example, a second insulating layer (not shown) is formed on the second conductive layer 330 to protect the second conductive layer 330. FIG. 4D shows the source-drain electrode metal layer 340 of the pixel circuit 121a, the source-drain electrode metal layer 340 includes a data line Vd and a first power signal line VDD1.

[00121] FIG. 4E is a schematic diagram of a stacked positional relationship of the above active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, and the source-drain electrode metal layer 340. As shown in FIG. 4D and 4E, the data line Vd is connected to the source portion of the data recording transistor T2 in the active semiconductor layer 310 through at least one via (eg, via 381a) in the insulating gate layer, the first insulating layer, and the second insulating layer. The first power signal line VDD1 is connected to a source portion of the corresponding first light emitting control transistor T4 in the active semiconductor layer 310 through at least one via (eg via 382a) in the insulating gate layer, the first insulating layer and the second insulating layer. The first power signal line VDD1 is connected to the first electrode CC1a of the third capacitor C2 in the second conductive layer 330 through at least one via (eg, via 3832a) in the second insulating layer. The first power signal line VDD1 is also connected to the second power signal line VDD2 in the second conductive layer 330 through at least one via (eg via 3831a) in the second insulating layer.

[00122] For example, as shown in FIG. 4D and 4E, the source-drain electrode metal layer 340 further includes a first connecting portion 341a, a second connecting portion 342a, and a third connecting portion 343a. One terminal of the first connecting portion 341a is connected to a drain portion of the corresponding compensation threshold transistor T3 in the active semiconductor layer 310 through at least one via (e.g. via 384a) in the insulating gate layer, the first insulating layer and the second insulating layer, and the other terminal of the first connecting portion 341a is connected to the gate electrode of the driving transistor T1 (i.e., the second electrode CC2a of the third capacitor C2) in the first conductive layer 320 through at least one via (e.g., via 385a) in the first an insulating layer and a second insulating layer. One terminal of the second connecting portion 342a is connected to the first power and reset line Init1a / second power and reset signal line Init2a through one via (e.g. via 386a) in the second insulating layer, and the other terminal of the second connecting portion 342a is connected to a drain portion of the second reset transistor T7 in the active semiconductor layer 310 through at least one via (eg, via 387a) in the gate insulating layer, the first insulating layer, and the second insulating layer. The third connecting portion 343a is connected to the drain portion of the second light emitting control transistor T5 in the active semiconductor layer 310 through at least one via (eg via 388a) in the insulating gate layer, the first insulating layer, and the second insulating layer.

[00123] For example, an intermediate layer (not shown) is formed on the above source-drain electrode metal layer 340 to protect the source-drain electrode metal layer 340. The first light-emitting voltage supply electrode of the light-emitting element of each subpixel may be located on the intermediate layer side remote from the carrier substrate.

[00124] For example, as shown in FIG. 4A-4E, in a first X direction, a first scan line Ga1a, a second scan line Ga2a, a first reset control line Rst1a, a second reset control line Rst2a, and a first power and reset line Init1a and a second power and reset line Init2a are located on the first side of the gate electrode of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1, and the first light control signal line EM1a and the second light control signal line EM2a are located on the second side of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1.

[00125] For example, first scan signal line Ga1a, second scan signal line Ga2a, first reset control signal line Rst1a, second reset control signal line Rst2a, first light control signal line EM1a, second light control signal line EM2a, first power signal line Init1a and reset and the second power supply and reset line Init2a continue in the second Y direction and the data line Vd continues in the first X direction.

[00126] For example, the first power signal line VDD1 extends in the first X direction, and the second power signal line VDD2 continues in the second Y direction. The voltage signal lines VDD of the first terminal VDD are grid-shaped on the display substrate, i. the first power supply signal line VDD1 and the second power supply signal line VDD2 are arranged in a grid pattern on the entire display substrate such that the resistance of the signal lines of the first voltage terminal VDD is small and the voltage drop of the signal lines of the first voltage terminal VDD is low, and additionally can increase the stability of the voltage of the power source provided by the first voltage terminal VDD.

[00127] For example, the first scanning signal line Ga1a, the second scanning signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light control signal line EM1a, and the second light control signal line EM2a are disposed on the same layer, and the first power and reset signal line Init1a, the second power and reset signal line Init2a, and the second power supply signal line VDD2 are disposed on the same layer. The first power signal line VDD1 and the data transmission line Vd are disposed on the same layer.

[00128] It should be noted that the positional relationship of the arrangement of the drive circuit, the first light emitting control circuit, the second light emitting control circuit, the data recording circuit, the data storage circuit, the threshold compensation circuit and the reset circuit, and so on. in each pixel circuit is not limited to the examples as shown in FIG. 4A to 4E, and according to actual application requirements, the positions of the drive circuit, the first light emitting drive circuit, the second light emitting drive circuit, the data recording circuit, the data storage circuit, the threshold compensation circuit, and the reset circuit can be specially set.

[00129] FIG. 5A is a planar schematic diagram of a display substrate according to some embodiments of the present disclosure; fig. 5B is a flat schematic diagram of a repeating cell provided by some embodiments of the present disclosure; fig. 6A is a flat schematic diagram of another repeating cell provided by some embodiments of the present disclosure; fig. 6B is a layout diagram of a display substrate provided by some embodiments of the present disclosure; fig. 6C is a schematic cross-sectional diagram of a line L1-L1 'in FIG. 6B; fig. 6D is a schematic structural diagram in cross-section of line L2-L2 'in FIG. 6B; and FIG. 6E is a planar schematic diagram of another display substrate provided through some embodiments of the present disclosure.

[00130] For example, as shown in FIG. 5A, in some embodiments of the present disclosure, the pixel arrangement in the display substrate 10 may be a GGRB pixel arrangement in order to increase the PPI (pixels per inch) of the display panel including the display substrate 10, thereby increasing the visual resolution of the display panel at the same display resolution. For example, each repeating cell 11 includes four subpixels, the four subpixels represent the first subpixel G1, the second subpixel G2, the third subpixel R, and the fourth subpixel B, respectively, and the four subpixels can accommodate the GGRB arrangement. It should be noted that only two complete repeating cells 11 are shown in FIG. 5A, but the present disclosure is not limited thereto. The display substrate 10 includes a plurality of repeating cells 11, and a plurality of repeating cells 11 are arranged in a matrix along a first X direction and a second Y direction.

[00131] For example, as shown in FIG. 5A, portions 31-40 may be portions in which pixel circuits of respective subpixels on the carrier substrate 10 are arranged, for example, portions 31-35 are located in a first row and portions 36-40 are arranged in a second row; regions 31 and 36 are in the first column, regions 32 and 37 are in the second column, regions 33 and 38 are in the third column, regions 34 and 39 are in the fourth column, and regions 35 and 40 are in the fifth column. For example, in the example as shown in FIG. 5A, in a repeating cell 11 surrounded by dotted lines, a first subpixel G1 pixel circuit is located in a portion 32, a second subpixel G2 pixel circuit is located in a portion 37, a third subpixel R pixel circuit is located in a portion 38, and a fourth subpixel B pixel circuit is located in plot 36.

[00132] It should be noted that in the present disclosure, "row" may represent a row corresponding to areas in which corresponding pixel circuits are located, and a "column" may represent a column corresponding to areas in which corresponding pixel circuits are located.

[00133] For example, the light emitting element 120 is configured to receive a light emitting signal (eg, may be a current signal) during operation and emit light at a luminous intensity corresponding to the light emitting signal. The light emitting element 120 may be a light emitting diode, and the light emitting diode, for example, may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), and the like, but the embodiments of the present disclosure are not limited thereto.

[00134] For example, as shown in FIG. 6C, the light emitting element 120 includes a first light emitting voltage applying electrode 1201, a second light emitting voltage applying electrode 1202, and a light emitting layer 1203 between the first light emitting voltage applying electrode 1201 and the second light emitting voltage applying electrode 1202. For example, as shown in FIG. 6C, the light emitting element of the first subpixel G1 includes a first light emitting voltage supply electrode 1201a, a second light emitting voltage supply electrode 1202 and a light emitting layer 1203a, and a light emitting element of the second subpixel G2 includes a first light emitting voltage supply electrode 1201b, a second light emitting voltage supply electrode 1202 and a light emitting layer 1203a.

[00135] For example, as shown in FIG. 6C, the orthographic projection of the first light-emitting voltage supply electrode 1201a of the light-emitting element of the first subpixel G1 on the carrier substrate 10 overlaps at least partially with the orthographic projection of the control terminal 1221a of the driving circuit of the first subpixel G1 pixel circuit on the carrier substrate 10, and the orthographic projection of the first electrode 1201b of the light emitting voltage supply of the light emitting element of the second subpixel G2 on the carrier substrate 10 overlaps at least partially with the orthographic projection of the control terminal 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10.

[00136] For example, the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 and the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2 may be disposed on an identical layer, and the second light emitting voltage supply electrode 1202 of the light emitting element of the first subpixel G1 and the second electrode 1202 supplying the light emitting voltage of the light emitting element of the second subpixel G2 may be provided as a whole.

[00137] For example, the orthographic projection of the light emitting element 1203a of the light emitting element of the first subpixel G1 on the carrier substrate 10 is continuous with the orthographic projection of the light emitting layer 1203a of the light emitting element of the second subpixel G2 on the carrier substrate 10, i.e. The light emitting layer 1203a of the light emitting element of the first subpixel G1 and the light emitting layer 1203a of the light emitting element of the second subpixel G2 can be prepared by an opening hole in the plate based on a high precision metal mask (FMM), which can effectively reduce the difficulty in the FMM process. For example, the light emitting layer 1203a of the light emitting element of the first subpixel G1 and the light emitting layer 1203a of the light emitting element of the second subpixel G2 are integrated.

[00138] For example, materials of the light emitting layers 1203 of the respective subpixels may be selected according to different colors of light emitted by the light emitting elements 120 of the respective subpixels. The material of the light emitting layer 1203 of each subpixel includes a luminescent light emitting material, a phosphorescent light emitting material, and the like. For example, in some embodiments, the first light emitting voltage applying electrode 1201 is an anode, the second light emitting voltage applying electrode 1202 is a cathode, and both the first light emitting voltage applying electrode 1201 and the second light emitting voltage applying electrode 1202 are prepared by conductive materials. Note that in some examples, the first organic layer is disposed between the first light emitting voltage applying electrode 1201 and the light emitting layer 1203, and the second organic layer is disposed between the second light emitting voltage applying electrode 1202 and the light emitting layer 1203. The first organic layer and the second organic layer are used for surface leveling and can be omitted.

[00139] For example, in each repeating cell 11, the color of the light emitted by the light emitting element 120a of the first subpixel G1 is the same as the color of the light emitted by the light emitting element 120b of the second subpixel G2, i.e. the first subpixel G1 and the second subpixel G2 are subpixels of the same color. For example, the first subpixel G1 and the second subpixel G2 are sensitive color subpixels. In a case where the display substrate 100 accommodates a red-green-blue (RGB) display mode, the above sensitive color is green, i. E. the first subpixel G1 and the second subpixel G2 are green subpixels. For example, the third subpixel R may be a red subpixel and the fourth subpixel B may be a blue subpixel.

[00140] For example, four subpixels in each repeating cell 11 may form two virtual pixels, and the third R subpixel and the fourth B subpixel in the repeating cell 11, respectively, are shared by two virtual pixels. The subpixels in the plurality of repeating cells 11 form a pixel array. In the row direction of the pixel array, the subpixel density is 1.5 times the virtual pixel density, and in the direction of the pixel array columns, the subpixel density is 1.5 times the virtual pixel density.

[00141] For example, the first subpixel G1 and the second subpixel G2 belong to two virtual pixels, respectively.

[00142] It should be noted that, firstly, since the third subpixel R and the fourth subpixel B are shared by two adjacent virtual pixels, the border of each virtual pixel is also very blurry, and therefore the embodiment of the present disclosure does not limit the shapes of the respective virtual pixels. pixels. Second, the virtual pixel division is related to the drive mode, and a specific virtual pixel division mode can be determined according to the actual drive mode, which is not particularly limited by the present disclosure.

[00143] For example, as shown in FIG. 6C, an orthographic projection of the driving terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10 is located within the orthographic projection of the first light-emitting voltage supply electrode 1201a of the light emitting element 120a of the first subpixel G1 on the carrier substrate 10. Orthographic projection of the driving terminal 1221b of the driving substrate 10 circuits of the second subpixel G2 on the carrier substrate 10 is disposed within the orthographic projection of the first light emitting voltage supply electrode 1201b of the light emitting element 120b of the second subpixel G2 on the carrier substrate 10. In other words, the orthographic projection of the first light emitting voltage supply electrode 1201a of the light emitting element 120a of the first subpixel G1 on the carrier substrate 10 completely covers the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10, orthographic The aphic projection of the first light emitting voltage supply electrode 1201b of the light emitting element 120b of the second subpixel G2 on the carrier substrate 10 completely covers the orthographic projection of the driving circuit pin 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10, for example, the orthographic projection area of the first light emitting voltage supply electrode 1201a element 120a of the first subpixel G1 on the carrier substrate 10 may exceed the orthographic projection area of the control terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10, and the orthographic projection area of the first light emitting voltage supply electrode 1201b of the light emitting element 120b of the second subpixel G2 on the carrier substrate 10 may exceed the orthographic projection area of the control terminal 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10.

[00144] For example, as shown in FIG. 3B, in a case where the driving circuit 122a of the pixel circuit of the first subpixel G1 includes a driving transistor T1, the control terminal 1221a of the driving circuit 122a of the pixel circuit of the first subpixel G1 is the gate electrode of the driving transistor T1 of the pixel circuit of the first subpixel G1, the orthographic projection of the first electrode supplying a light emitting voltage of the light emitting element 120a of the first subpixel G1 on the carrier substrate 10 at least partially overlaps with an orthographic projection of the gate electrode of the driving transistor T1 of the first subpixel G1 on the carrier substrate 10; and, as shown in FIG. 3C, in a case where the driving circuit 122b of the pixel circuit of the second subpixel G2 includes a driving transistor T1, the control terminal 1221b of the driving circuit 122b of the pixel circuit of the second subpixel G2 is a gate electrode of the driving transistor T1 of the pixel circuit of the second subpixel G2, and an orthographic projection of the first electrode supplying the light-emitting voltage of the light emitting element 120b of the second subpixel G2 on the carrier substrate 10 at least partially overlaps with the orthographic projection of the gate electrode of the driving transistor T1 of the second subpixel G2 on the carrier substrate 10.

[00145] For example, an orthographic projection of the gate electrode of the driving transistor T1 of the first subpixel G1 on the carrier substrate 10 is located within the orthographic projection of the first light-emitting voltage supply electrode of the light emitting element 120a of the first subpixel G1 on the carrier substrate 10; and an orthographic projection of the gate electrode of the driving transistor T1 of the second subpixel G2 on the carrier substrate 10 is located within the orthographic projection of the first light-emitting voltage supply electrode of the light emitting element 120b of the second subpixel G2 on the carrier substrate 10.

[00146] For example, as shown in FIG. 6C, an overlapping area between the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10 and the orthographic projection of the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 on the carrier substrate 10 constitutes the first region A1. The area of the overlapping portion between the orthographic projection of the control terminal 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10 and the orthographic projection of the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2 on the carrier substrate 10 is the second region A2, and the ratio of the first region A1 to the second area A2 satisfies the following relationship:

Amin≤A1 / A2≤Amax,

where A1 represents the first region, A2 represents the second region, Amin represents the minimum threshold value of the ratio and is 90%, and Amax represents the maximum threshold value of the ratio and is 110%.

[00147] For example, in some examples, the first area A1 may be greater than or equal to the second area A2, in which case, the minimum threshold ratio Amin may be 90%, and the maximum threshold value Amax of the ratio may also be 100%; and in other examples, the first area A1 may be smaller than the second area A2, in which case, the minimum ratio threshold Amin may be 95% and the maximum ratio threshold Amax may be 105%. An embodiment of the present disclosure is not particularly limited to specific values for the minimum threshold value of the ratio and the maximum threshold value of the ratio, provided that the difference between the first area A1 and the second area A2 is provided as small (e.g., less than 10%), and furthermore, the difference between parasitic capacitance between the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 and the driving circuit control terminal 1221a of the first subpixel G1 (i.e., the first capacitor C11, as shown in FIG. 3B) and the parasitic capacitance between the first light emitting voltage electrode 1201b the light emitting element of the second subpixel G2 and the driving circuit control terminal 1221b of the second subpixel G2 (i.e., the second capacitor C12, as shown in Fig.3C) can be made small (for example, less than 10%), thereby improving the display effect of the panel display including the display substrate 100. For example, in a case where the ratio of the first area A1 and the second area A2 is between the above-mentioned minimum threshold value of the ratio and the maximum threshold value of the ratio, even with a low gray scale (for example, 64 gray scales), i.e. in the case where the recognition performance of the human eye is high, the user may not be able to see the luminance difference between the first subpixel G1 and the second subpixel G2, thereby effectively improving the display effect of the display panel and improving the user experience.

[00148] For example, as shown in FIG. 5A and 5B, the shape of the first light emitting voltage supply electrode 1201a of the light emitting element 120a of the first subpixel G1 is different from the shape of the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2. For example, in some examples, the shape of the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 may be an octagon, and the shape of the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2 may be pentagonal.

[00149] For example, in each repeating cell 11, the orthographic area of the first light emitting voltage supply electrode 1201a of the light emitting element of the first G1 subpixel on the carrier substrate 10 is different from the orthographic projection area of the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2 on the carrier substrate 10, and the orthographic projection area of the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 on the carrier substrate 10 is larger than the orthographic projection area of the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2 on the carrier substrate 10.

[00150] For example, as shown in FIG. 5B, the first light emitting voltage supply electrode 1201a of the light emitting element 120a of the first subpixel G1 includes an auxiliary electrode unit Ae, the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate 10 at least partially overlaps the orthographic projection of the driving pin 1221a of the pixel circuit driving circuit of the first subpixel G1 on the carrier substrate 10. For example, in some examples, the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10 is located within the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate 10.

[00151] For example, the orthographic projection of the gate electrode of the driving transistor T1 of the first subpixel G1 on the carrier substrate 10 is located within the orthographic projection of the auxiliary electrode unit Ae of the first light emitting voltage supply electrode of the light emitting element 120a of the first subpixel G1 on the carrier substrate 10.

[00152] For example, the auxiliary electrode unit Ae serves as the first electrode CC3 of the first capacitor C11, the control terminal 1221a of the driving circuit 122a of the first subpixel G1 is multiplexed as the second electrode CC4 of the first capacitor C11, i.e. the auxiliary electrode unit Ae is the first electrode CC3 of the first capacitor C11, and the control terminal 1221a of the driving circuit 122a of the first subpixel G1 (i.e., the gate electrode of the driving transistor T1 of the first subpixel G1) is the second electrode CC4 of the first capacitor C11.

[00153] For example, as shown in FIG. 5B, the shape of the auxiliary electrode unit Ae may be rectangular, and the orthographic projection shape of the auxiliary electrode unit Ae on the carrier substrate 10 is the same as that of the auxiliary electrode unit Ae, i.e. rectangular. However, the present disclosure is not limited thereto, and the shape of the auxiliary electrode unit Ae may be pentagonal, hexagonal, elliptical, and the like.

[00154] For example, as shown in FIG. 5B, the first light emitting voltage supply electrode 1201a of the light emitting element 120a of the first subpixel G1 further includes a first excitation electrode unit De1, and the first excitation electrode unit De1 is electrically connected to the sub electrode unit Ae.

[00155] For example, as shown in FIG. 5B, the shape of the first excitation electrode unit De1 may be a pentagon, and the orthographic projection shape of the first excitation electrode unit De1 on the carrier substrate 10 is identical to that of the first excitation electrode unit De1, i.e. represent a pentagon. A pentagon can be composed of a triangle and a rectangle.

[00156] For example, in the example as shown in 5B, the first excitation electrode unit De1 and the auxiliary electrode unit Ae are provided integrally, and thus the shape of the first light-emitting voltage applying electrode 1201a may be an octagon, and the octagon may be composed of a pentagon and a rectangle.

[00157] Note that in other examples, the first excitation electrode unit De1 and the auxiliary electrode unit Ae may be provided separately, provided that the first excitation electrode unit De1 and the auxiliary electrode unit Ae can be electrically connected to each other.

[00158] For example, the first excitation electrode unit De1 and the auxiliary electrode unit Ae can be simultaneously formed through the same patterning process.

[00159] For example, as shown in FIG. 6C, the first excitation electrode unit De1 and the auxiliary electrode unit Ae are disposed on the same layer.

[00160] For example, as shown in FIG. 6C, an orthographic projection of a first excitation electrode unit De1 on a carrier substrate 10, an orthographic projection of a light emitting layer 1203a of a light emitting element of a first subpixel G1 on a carrier substrate 10, and an orthographic projection of a second light emitting voltage supply electrode 1202 of a light emitting element of the first subpixel G1 on a carrier substrate 10, at least partially overlap.

[00161] For example, in some embodiments, the second light emitting voltage supply electrodes of the light emitting elements of all subpixels on the display substrate are provided integrally, i. E. the second light-emitting voltage applying electrode 1202 covers the entire carrier substrate 10, i.e. the second light-emitting voltage supply electrode 1202 may be a flat electrode. For example, as shown in FIG. 6C, for the first subpixel G1 and the second subpixel G2, the portion in which the flat second light-emitting voltage supply electrode 1202 overlaps with the first light-emitting voltage supply electrode 1201a of the light-emitting element of the first sub-pixel G1 may be represented as the second light-emitting voltage supply electrode 1202 of the first subpixel G1 , and a part in which the planar second light-emitting voltage supply electrode overlaps with the first light-emitting voltage-supply electrode 1201b of the light-emitting element of the second sub-pixel G2 may be represented as the second light-emitting voltage supply electrode 1202 of the light-emitting element of the second sub-pixel G2. The second light-emitting voltage supply electrode 1202 of the light-emitting element of the first subpixel G1 and the second light-emitting voltage supply electrode 1202 of the light-emitting element of the second subpixel G2 are provided integrally.

[00162] For example, as shown in FIG. 6C, the light emitting layer of the light emitting element of the first subpixel G1 and the light emitting layer of the light emitting element of the second subpixel G2 are provided integrally. For the first subpixel G1 and the second subpixel G2, the portion in which the light emitting layer 1203a overlaps with the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 may be represented as the light emitting layer of the light emitting element of the first subpixel G1, and the portion in which the light emitting layer 1203 overlaps with the first light-emitting voltage supply electrode 1201b of the light-emitting element of the second subpixel G2, may be represented as the light-emitting layer of the light-emitting element of the second subpixel G2.

[00163] For example, as shown in FIG. 6C, the display substrate 100 further includes a driving pixel layer 160, the driving pixel layer 160 is located on the side of the first light-emitting voltage supply electrode of the light-emitting element of each sub-pixel remotely from the carrier substrate 10, and includes a first hole, the first hole makes the first supply electrode 1201a accessible the light emitting voltage of the light emitting element of the first subpixel G1 and the first electrode 1201b for supplying the light emitting voltage of the light emitting element of the second subpixel G2, at least part of the light emitting layer 1203a of the light emitting element of the first subpixel G1, and at least part of the light emitting layer 1203a of the second subpixel G2 in the first hole and cover the accessible portion of the first light-emitting voltage applying electrode 1201a and the accessible portion of the first light-emitting voltage applying electrode 1201b, the region of the portion in which the first hole overlaps with the first light emitting voltage electrode 1201a is an effective light emitting region of the first subpixel G1, and a region of the portion in which the first hole overlaps with the first light emitting voltage electrode 1201b is an effective light emitting region of the second subpixel G2.

[00164] It should be noted that in an embodiment of the present disclosure, the light emitting layer of each light emitting element may include the EL layer directly and other common layers located on both sides of the EL layer, for example, other common layers include a hole injection layer, a hole transport layer , electron injection layer, electron transport layer, etc .; but in the drawings of the present disclosure, only the electroluminescent layer in the light emitting layer is shown, and other common layers are not shown.

[00165] For example, in some examples, the orthographic projection of the first excitation electrode unit De1 on the carrier substrate 10 may not completely overlap with the orthographic projection of the second light emitting voltage supply electrode 1202 of the light emitting element of the first subpixel G1 on the carrier substrate 10, for example, the orthographic projection of the first excitation electrode unit block De1 on the carrier substrate 10 is located within the orthographic projection of the second light-emitting voltage supply electrode 1202 of the light emitting element of the first subpixel G1 on the carrier substrate 10, and the orthographic projection of the light emitting layer 1203a of the light emitting element of the first subpixel G1 on the carrier substrate 10 may also be located within the orthographic projection the second electrode 1202 of the light-emitting voltage supply of the light-emitting element of the first subpixel G1 on the carrier substrate 10.

[00166] It should be noted that in a portion in which the orthographic projection of the first excitation electrode unit De1 on the carrier substrate 10, the orthographic projection of the light emitting layer 1203a of the light emitting element of the first subpixel G1 on the carrier substrate 10, and the orthographic projection of the second electrode 1202 for supplying the light emitting voltage of the first subpixels G1 on the carrier substrate 10 overlap, for the first subpixel G1, a part of the light emitting layer of the light emitting element of the first subpixel G1 corresponding to the first opening of the specifying pixel layer 160 is used to emit light.

[00167] For example, as shown in FIG. 5B, the first light-emitting voltage supply electrode 1201b of the light-emitting element 120b of the second sub-pixel G2 includes the second driving electrode unit De2. The orthographic projection of the second driving electrode unit De2 on the carrier substrate 10 at least partially overlaps with the orthographic projection of the driving pin 1221b of the driving circuit of the second subpixel G2 on the carrier substrate 10. For example, in some examples, the orthographic projection of the driving pin 1221b of the driving of the pixel circuitry of the second subpixel G2 on the carrier substrate 10 may be located within the orthographic projection of the second excitation electrode unit De2 on the carrier substrate 10. For example, the orthographic projection of the gate electrode of the excitation transistor T1 of the second subpixel G2 on the carrier substrate 10 is located within the orthographic projection of the second excitation the electrode unit De2 of the first light-emitting voltage supply electrode of the light-emitting element 120b of the second subpixel G2 on the carrier substrate 10.

[00168] For example, the second driving electrode unit De2 can be multiplexed as the first electrode of the second capacitor C12, the control terminal 1221b of the driving circuit 122b of the second subpixel G2 can be multiplexed as the second electrode of the second capacitor C12, i.e. the second driving electrode unit De2 is the first electrode of the second capacitor C12, and the control terminal 1221b of the driving circuit 122b of the second subpixel G2 (i.e., the gate electrode of the driving transistor T1 of the second subpixel G2) is the second electrode of the second capacitor C12.

[00169] For example, as shown in FIG. 5B, the shape of the first excitation electrode unit De1 may be the same as the shape of the second excitation electrode unit De2, i.e. the shape of the second exciting electrode unit De2 can also be a pentagon. The shape of the orthographic projection of the second exciting electrode unit De2 on the carrier substrate 10 is the same as the shape of the second exciting electrode unit De2, i.e. is a pentagon.

[00170] For example, the orthographic projection area of the first exciting electrode unit De1 on the carrier substrate 10 is identical to the orthographic projection area of the second exciting electrode unit De2 on the carrier substrate 10.

[00171] It should be noted that, in some embodiments, the shape of the first excitation electrode unit De1 and the shape of the second excitation electrode unit De2 may be rectangles, diamonds, or the like. The shape of the first excitation electrode unit De1 and the shape of the second excitation electrode unit De2 may be different, and the present disclosure is not limited thereto.

[00172] For example, as shown in FIG. 6C, an orthographic projection of a second excitation electrode unit De2 on a carrier substrate 10, an orthographic projection of a light emitting layer 1203a of a light emitting element of a second subpixel G2 on a carrier substrate 10, and an orthographic projection of a second light emitting voltage supply electrode 1202 of a light emitting element of a second subpixel G2 on a carrier substrate 10 at least partially overlap.

[00173] For example, in some examples, the orthographic projection of the second excitation electrode unit De2 on the carrier substrate 10 may not completely overlap with the orthographic projection of the second light-emitting voltage supply electrode 1202 of the light emitting element of the second subpixel G2 on the carrier substrate 10, for example, the orthographic projection of the second excitation electrode the unit De2 on the carrier substrate 10 is disposed within an orthographic projection of the second light-emitting voltage supply electrode 1202 of the light-emitting element of the second subpixel G2 on the carrier substrate 10.

[00174] It should be noted that in a portion in which the orthographic projection of the second excitation electrode unit De2 on the carrier substrate 10, the orthographic projection of the light emitting layer 1203a of the light emitting element of the second subpixel G2 on the carrier substrate 10, and the orthographic projection of the second electrode 1202 for supplying the light emitting voltage of the second subpixels G2 on the carrier substrate 10 overlap, for the second subpixel G2, a part of the light emitting layer of the light emitting element of the second subpixel G2 corresponding to the first hole of the setting pixel layer 160 is used to emit light.

[00175] For example, as shown in FIG. 5A and 5B, in each repeating cell 11, the first subpixel G1 and the second subpixel G2 are arranged along the first X direction, and the first X direction is parallel to the surface of the carrier substrate 10. For example, in the first X direction, the auxiliary electrode unit Ae is located on the side of the first driving the electrode unit De1 remotely from the light emitting element of the second subpixel G2, that is, as shown in FIG. 5B, in the first X direction, the first excitation electrode unit De1 is disposed between the sub electrode unit Ae and the second excitation electrode unit De2.

[00176] For example, as shown in FIG. 6C, the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate 10 does not overlap with the orthographic projection of the light emitting layer 1203a of the light emitting element of the first subpixel G1 on the carrier substrate 10. For example, in some examples, the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate 10 does not completely overlap with an orthographic projection of the light emitting layer 1203a of the light emitting element of the first subpixel G1 on the carrier substrate 10.

[00177] For example, as shown in FIG. 6A and 6B, the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel G1 further includes a first connection electrode unit Ce1, in the first direction X, the first connection electrode unit Ce1 is located on the side of the first excitation electrode unit De1 remotely from the light-emitting element of the second subpixel G2, the first connecting electrode unit Ce1 is disposed between the auxiliary electrode unit Ae and the first excitation electrode unit De1, and is electrically connected to both the auxiliary electrode unit Ae and the first excitation electrode unit De1.

[00178] For example, in some embodiments, the first connecting electrode unit Ce1, the auxiliary electrode unit Ae, and the first excitation electrode unit De1 are provided integrally. It should be noted that in other examples, the first electrode connection unit Ce1, the auxiliary electrode unit Ae, and the first excitation electrode unit De1 may be provided separately, provided that the first electrode connection unit Ce1, the auxiliary electrode unit Ae and the first excitation electrode unit De1 can electrically connect with each other.

[00179] For example, the first connecting electrode unit Ce1 is used to connect the first driving electrode unit De1 and the pixel circuit of the first subpixel G1.

[00180] For example, as shown in FIG. 6C, the first connecting electrode unit Ce1, the auxiliary electrode unit Ae, and the first excitation electrode unit De1 are disposed on the same layer. The first connecting electrode unit Ce1, the sub electrode unit Ae, and the first excitation electrode unit De1 can be simultaneously formed by the same patterning process.

[00181] For example, the shape of the first connecting electrode unit Ce1 may be a regular shape, such as a rectangle, a diamond, and the like; and the shape of the first connecting electrode unit Ce1 may also be irregular.

[00182] For example, as shown in FIG. 6A and 6B, in some examples, the shape of the auxiliary electrode unit Ae and the shape of the first connecting electrode unit Ce1 are rectangles, and in the second direction Y, the width of the auxiliary electrode unit Ae is smaller than the width of the first connecting electrode unit Ce1, i.e. the auxiliary electrode unit Ae and the first electrode connecting unit Ce1 form a stepped shape. In the second Y direction, the width of the first electrode connection unit Ce1 is smaller than the maximum width of the first excitation electrode unit De1.

[00183] For example, the first excitation electrode unit De1 has five inner corners, and the five inner corners may include two right angles, two obtuse angles, and an acute angle, and the first electrode connection unit Ce1 extends from the side where the acute angle of the first the excitation electrode unit De1 towards the first excitation electrode unit De1 from the light emitting element of the second subpixel G2.

[00184] For example, in some embodiments, the orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate 10 does not overlap with the orthographic projection of the light emitting layer 1203a of the light emitting element of the first subpixel G1 on the carrier substrate 10, and the orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate 10 does not overlap with the orthographic projection of the driving terminal 1221a of the pixel circuit driving circuit of the first subpixel G1 on the carrier substrate 10. However, the present disclosure is not limited to this case, the orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate 10 may partially overlap with the orthographic projection the control terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10. It should be noted that in a case where the orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate 10 overlaps with the orthographic projection of the driving pin 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10, the overlapping area between the orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate 10 and the orthographic projection of the driving pin 1221a of the driving pixel circuit of the first subpixel G1 on the carrier substrate 10 is smaller than the overlapping area between the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate 10 and the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first subpixel G1 on the carrier substrate 10.

[00185] For example, as shown in FIG. 6C and 6D, the display substrate 100 further includes an intermediate layer 101. In a direction perpendicular to the surface of the carrier substrate 10, the pixel circuit 121 of each subpixel is disposed between the intermediate layer 101 and the carrier substrate 10, and the light emitting element 120 is located on the side of the intermediate layer 101 remotely from the carrier substrate 10, i.e. an intermediate layer 101 is disposed between the light emitting element 120 and the carrier substrate 10.

[00186] For example, in some embodiments, the layers in which the light emitting elements of all subpixels are located constitute the first group of functional layers, the layers in which the pixel circuits of all subpixels are located constitute the second group of functional layers, i. in the direction perpendicular to the surface of the carrier substrate 10, the first group of functional layers is located on the side of the intermediate layer 101 remotely from the carrier substrate 10, the second group of functional layers is located on the side of the intermediate layer 101 close to the carrier substrate 10, i.e. the second group of functional layers is located between the intermediate layer 101 and the carrier substrate 10, and the intermediate layer 101 is located between the first group of functional layers and the second group of functional layers. The intermediate layer 101 is located between the first group of functional layers and the second group of functional layers. For example, drive circuit 122, data recording circuit 126, data storage circuit 127, threshold compensation circuit 128, and reset circuit 129 as shown in FIG. 3A are located in the second set of functional layers. For example, the first parasitic circuit 125a in the pixel circuit 121a of the first subpixel G1 and the second parasitic circuit 125b in the pixel circuit 121b of the second subpixel G2 are also located in the second group of functional layers.

[00187] It should be noted that in an embodiment of the present disclosure, the first functional layer group may include a plurality of sub-layers, for example, the first functional layer group may include a sub-layer in which the first light-emitting voltage supply electrode 1201a of the light-emitting element of the first sub-pixel G1 is disposed , a sublayer in which the second light emitting voltage supply electrode 1202 of the light emitting element of the first subpixel G1 is disposed, and a sublayer in which the light emitting layer 1203a of the light emitting element of the first subpixel G1 is disposed. Likewise, the second group of functional layers may also include a plurality of sub-layers. For example, the second group of functional layers may include sublayers in which corresponding elements are located in the pixel circuit of the first subpixel G2. In case the pixel circuit includes a transistor, the second group of functional layers may include a sublayer in which the gate electrode of the transistor is located, a sublayer in which a source electrode and a drain electrode of the transistor are located, a sublayer in which an active layer is located, and a sublayer, in which an insulating barrier layer is located, etc.

[00188] For example, the intermediate layer 101 may be a flat layer. For example, as shown in FIG. 6C and 6D, in a direction perpendicular to the surface of the carrier substrate 10, the first light emitting voltage supply electrode 1201a of the light emitting element of the first subpixel G1 is on the side of the light emitting layer 1203a of the light emitting element of the first subpixel G1 close to the intermediate layer 101, and the second voltage supply electrode 1202 of the light emitting element of the light emitting element of the first subpixel G1 is located on the side of the light emitting layer 1203a of the light emitting element of the first subpixel G1 remotely from the intermediate layer 101.

[00189] For example, as shown in FIG. 6C, the intermediate layer 101 includes a first via h1, and the first electrode connecting block Ce1 extends to the first via h1 and is electrically connected to the pixel circuit of the first sub-pixel G1 via the first via h1, for example, the first electrode connecting block Ce1 is electrically connected to the second light emitting control circuit 124a of the pixel circuit of the first subpixel G1 through the first via h1. For example, the first connecting electrode unit Ce1 may cover and fill the first via h1.

[00190] For example, in the first subpixel G1, the first connecting electrode unit Ce1 is electrically connected to the second electrode of the second light emitting control transistor T5 of the pixel circuit of the first subpixel G1 through the first via h1.

[00191] For example, as shown in FIG. 4A-4E, the pixel circuit 121 may include an active semiconductor layer 310, an electrode gate metal layer (including a first conductive layer 320 and a second conductive layer 330), and a source-drain electrode metal layer 340. In the direction perpendicular to the carrier substrate 10, the active semiconductor layer 310 is sandwiched between the carrier substrate 10 and the electrode metal gate layer, and the electrode metal gate layer is sandwiched between the active semiconductor layer 310 and the electrode source-drain metal layer 340. For example, the first conductive layer 320 of the electrode metal gate layer is disposed between the active semiconductor layer 310 and the second conductive layer 330 of the electrode metal gate layer, and the second conductive layer 330 of the electrode metal gate layer is disposed between the first conductive layer 320 of the electrode metal gate layer and the electrode metal layer 340 "source-drain".

[00192] For example, in the present disclosure, the active layers of respective transistors (e.g., drive transistor T1, data write transistor T2, threshold compensation transistor T3, first light emitting control transistor T4, second light emitting control transistor T5, first reset transistor T6, and second transistor T7 reset, etc.) in the pixel circuit 121 of each subpixel are located in the active semiconductor layer 310, the gate electrodes of the respective transistors in the pixel circuit 121 are located in the first conductive layer 320 of the electrode metal gate layer, and the source electrodes and drain electrodes of the respective transistors in the pixel circuit 121 are disposed in the source-drain electrode metal layer 340.

[00193] For example, the first connecting electrode unit Ce1 extends to the source-drain electrode metal layer of the pixel circuit through the first via h1.

[00194] For example, the first light emitting voltage supply electrode of the light emitting element of the second subpixel G2 further includes a second connecting electrode unit Ce2, and the second connecting electrode unit Ce2 is electrically connected to the second driving electrode unit De2. For example, in some embodiments, the second electrode connection unit Ce2 is provided integrally with the second excitation electrode unit De2. Note that in other examples, the second electrode connection unit Ce2 and the second excitation electrode unit De2 may be provided separately, provided that the second electrode connection unit Ce2 and the second excitation electrode unit De2 can be electrically connected to each other.

[00195] For example, the second connecting electrode unit Ce2 is used to connect the second driving electrode unit De2 and the pixel circuit of the second sub-pixel G2.

[00196] For example, as shown in FIG. 6A and 6B, in the first X direction, the second electrode connection unit Ce2 is located on the side of the second excitation electrode unit De2 remotely from the light emitting element of the first subpixel G1, that is, as shown in FIG. 6A and 6B, the second driving electrode unit De2 is disposed between the second connecting electrode unit Ce2 and the first driving electrode unit De1 in the first X direction.

[00197] For example, as shown in FIG. 6C, the second connecting electrode unit Ce2 and the second excitation electrode unit De2 are disposed on the same layer. The second connecting electrode unit Ce2 and the second driving electrode unit De2 can be formed simultaneously by the same patterning process.

[00198] For example, the shape of the second connecting electrode unit Ce2 may be a regular shape such as a rectangle and a diamond, and so on. The shape of the second Ce2 connecting electrode unit may be irregular.

[00199] For example, in some examples, in the second Y direction, the width of the second connecting electrode unit Ce2 is smaller than the maximum width of the second excitation electrode unit De2. For example, the second excitation electrode unit De2 includes five internal corners, the five internal corners may include two right angles, two obtuse angles, and an acute angle, and the second connection electrode unit Ce2 extends from the side where the acute angle of the second excitation electrode is located. unit De2, towards the second driving electrode unit De2 from the light emitting element of the first subpixel G1.

[00200] For example, in some examples, the shape of the first connecting electrode unit Ce1 may be the same as the shape of the second connecting electrode unit Ce2.

[00201] For example, in some embodiments, the orthographic projection of the second connecting electrode unit Ce2 on the carrier substrate 10 does not overlap with the orthographic projection of the light emitting layer 1203a of the light emitting element of the second subpixel G2 on the carrier substrate 10, and the orthographic projection of the second connecting electrode unit Ce2 on the carrier substrate 10 does not overlap with the orthographic projection of the control terminal 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10. However, the present disclosure is not limited to this case, and the orthographic projection of the second connecting electrode unit Ce2 on the carrier substrate 10 may partially overlap with the orthographic the projection of the control terminal 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10. It should be noted that in the case where the orthographic projection of the second connecting electrode unit Ce 2 on the carrier substrate 10 overlaps with the orthographic projection of the control pin 1221b of the driving circuit of the pixel circuit of the second subpixel G2 on the carrier substrate 10, the overlapping region between the orthographic projection of the second connecting electrode unit Ce2 on the carrier substrate 10 and the orthographic projection of the driving pin 1221b of the driving pixel circuit of the second subpixel G2 circuitry on the carrier substrate 10 is smaller than the overlapping area between the orthographic projection of the second driving electrode unit De2 on the carrier substrate 10 and the orthographic projection of the control terminal 1221b of the driving circuit of the second subpixel circuitry G2 on the carrier substrate 10.

[00202] For example, similar to the first subpixel G1, in a direction perpendicular to the surface of the carrier substrate 10, the first light emitting voltage supply electrode 1201b of the light emitting element of the second subpixel G2 is located on the side of the light emitting layer 1203a of the light emitting element of the second subpixel G2 close to the intermediate layer 101, and the second The light emitting voltage 1202 of the light emitting element of the second subpixel G2 is located on the side of the light emitting layer 1203a of the light emitting element of the second subpixel G2 remotely from the intermediate layer 101.

[00203] For example, as shown in FIG. 6C, the intermediate layer 101 includes a second via h2, and the second electrode connecting block Ce2 extends to the second via h2 and is electrically connected to the pixel circuit of the second sub-pixel G2 via the second via h2, for example, the second electrode connecting block Ce2 is electrically connected to the second light emitting control circuit 124b of the pixel circuit of the second subpixel G2 through the second via h2. For example, the second connecting electrode block Ce2 can cover and fill the second via h2.

[00204] For example, in the second subpixel G2, the second connecting electrode unit Ce2 is electrically connected to the second electrode of the second light emitting control transistor T5 of the pixel circuit 121b of the second subpixel G2 through the second via h2.

[00205] For example, the second connecting electrode unit Ce2 extends to the source-drain electrode metal layer of the pixel circuit through the second via h2.

[00206] For example, as shown in FIG. 5A, in each repeating cell 11, a third R subpixel and a B fourth subpixel are arranged along the second Y direction, and in the second Y direction, the first subpixel G1 and the second subpixel G2 are located between the third subpixel R and the fourth subpixel B, the second Y direction is parallel to the surface of the carrier substrate 10, and the first X direction and the second Y direction are perpendicular to each other.

[00207] For example, in each repeating cell 11, the line connecting the center of the first subpixel G1 and the center of the second subpixel G2 is the first center line, and the line connecting the center of the third subpixel R and the center of the fourth subpixel B is the second center line ... The length of the first center line is less than the length of the second center line. For example, the first center line and the second center line are vertically bisected and the first center line is substantially parallel to the first X direction and the second center line is substantially parallel to the second Y direction.

[00208] For example, the light emitting element of the third subpixel R includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer. As shown in FIG. 6D, the light emitting element of the fourth subpixel B includes a first light emitting voltage applying electrode 1201d, a second light emitting voltage applying electrode 1202d, and a light emitting layer 1203d. Note that, for the third subpixel R, the portion in which the flat second light-emitting voltage supply electrode 1202 overlaps with the first light-emitting voltage supply electrode of the light-emitting element of the third sub-pixel R may be represented as the second light-emitting voltage supply electrode of the light-emitting element of the third subpixel R; and for the fourth subpixel B, a portion in which the flat second light-emitting voltage supply electrode overlaps with the first light-emitting voltage-supply electrode of the light-emitting element of the fourth sub-pixel B may be represented as the second light-emitting voltage supply electrode of the light-emitting element of the fourth subpixel B. In other words, the second voltage supply electrode light emitting light emitting element of the first subpixel G1, the second light emitting voltage supply electrode of the light emitting element of the second subpixel G2, the second light emitting voltage supply electrode of the light emitting element of the third subpixel R, and the second light emitting voltage supply electrode of the light emitting element of the fourth subpixel B are integrated.

[00209] For example, the orthographic projection of the first light-emitting voltage supply electrode of the light emitting element of the third subpixel R on the carrier substrate 10 may at least partially overlap with the orthographic projection of the driving terminal of the third subpixel R pixel circuit driving circuit on the carrier substrate 10.

[00210] For example, the orthographic projection of the first light-emitting voltage supply electrode 1202d of the light emitting element of the fourth subpixel B on the carrier substrate 10 may also overlap at least partially with the orthographic projection of the driving circuit terminal of the fourth subpixel B pixel circuit on the carrier substrate 10. For example as shown in FIG. 6D, an orthographic projection of the driving terminal 1221d of the driving circuit of the pixel circuit of the fourth subpixel B on the carrier substrate 10 is located within the orthographic projection of the first light-emitting voltage supply electrode 1202d of the light emitting element of the fourth subpixel B on the carrier substrate 10.

[00211] For example, as shown in FIG. 6A and 6B, the first light-emitting voltage supply electrode of the light-emitting element of the third subpixel R includes the third excitation electrode unit De3 and the third excitation electrode unit Ce3, and the third excitation electrode unit De3 and the third electrode connection unit Ce3 are electrically connected to each other, and the first electrode 1201d supplying the light-emitting voltage of the light-emitting element of the fourth subpixel B includes the fourth driving electrode unit De4 and the fourth connecting electrode unit Ce4, and the fourth driving electrode unit De4 and the fourth connecting electrode unit Ce4 are electrically connected to each other. For example, the orthographic projection of the driving terminal 1221c of the third subpixel circuit driving circuit R on the carrier substrate 10 overlaps at least partially with the orthographic projection of the third driving electrode unit De3 on the carrier substrate 10; and as shown in FIG. 6D, the orthographic projection of the control terminal 1221d of the driving circuit terminal of the pixel circuit of the fourth subpixel B on the carrier substrate 10 overlaps at least partially with the orthographic projection of the fourth driving electrode unit De4 on the carrier substrate 10, for example, the orthographic projection of the driving pin 1221d of the driving pixel circuit the circuitry of the fourth subpixel B on the carrier substrate 10 is disposed within an orthographic projection of the fourth exciting electrode unit De4 on the carrier substrate 10.

[00212] For example, the third connecting electrode unit Ce3 is used to connect the third driving electrode unit De3 and the pixel circuit of the third sub-pixel R; and the fourth connecting electrode unit Ce4 is used to connect the fourth driving electrode unit De4 and the pixel circuit of the fourth subpixel B.

[00213] For example, the pixel circuit of the third subpixel R further includes a third parasitic circuit, and the pixel circuit of the fourth subpixel B further includes a fourth parasitic circuit. The third parasitic circuit includes a fourth capacitor, and the fourth parasitic circuit includes a fifth capacitor. The third driving electrode unit De3 is multiplexed as the first electrode of the fourth capacitor, and the control terminal of the driving circuit of the third subpixel R is multiplexed as the second electrode of the fourth capacitor. The fourth driving electrode unit De4 is multiplexed as the first electrode of the fifth capacitor, and the driving terminal of the driving circuit of the fourth subpixel B is multiplexed as the second electrode of the fifth capacitor.

[00214] For example, the shape of the third excitation electrode unit De3 may be a regular hexagon, and the shape of the fourth excitation electrode unit De4 may also be a regular hexagon. The shape of the third electrode connection unit Ce3 may also be an irregular hexagon, and the shape of the fourth electrode connection unit Ce4 may also be an irregular hexagon.

[00215] It should be noted that, in some embodiments, the shape of the third excitation electrode unit De3 and the shape of the fourth excitation electrode unit De4 may be rectangles, long ellipses, and so on. The present disclosure does not particularly limit the shape of the third excitation electrode unit De3, the shape of the third excitation electrode unit Ce3, the shape of the fourth excitation electrode unit De4, and the shape of the fourth excitation electrode unit Ce4.

[00216] For example, the third electrode connection unit Ce3 may be a portion protruding outward on one side (eg, the lower right side of the hexagon) of the hexagonal third excitation electrode unit De3; and the fourth connecting electrode unit Ce4 may be a portion protruding outward from one side (for example, the lower left side of the hexagonal) hexagonal fourth driving electrode unit De4.

[00217] It should be noted that the area of the exciting electrode unit of each subpixel can be specifically set according to the light output of the luminescent material. For example, if the light output of the luminescent material is higher, the area of the sub-pixel drive electrode unit may be smaller; and while the light output of the luminescent material is lower, the area of the subpixel drive electrode unit may be larger. For example, in some embodiments, the area of the third excitation electrode unit De3 is smaller than the area of the fourth excitation electrode unit De4. The region of the third exciting electrode unit De3 is larger than the region of the first exciting electrode unit De1, and the region of the third exciting electrode unit De3 is larger than the region of the second exciting electrode unit De2.

[00218] For example, in some embodiments, the third excitation electrode unit De3 and the third excitation electrode unit Ce3 are provided integrally, and the fourth excitation electrode unit De4 and the fourth excitation electrode unit Ce4 are also provided integrally. Note that in other examples, the third excitation electrode unit De3 and the third excitation electrode unit Ce3 may be provided separately, provided that the third excitation electrode unit De3 and the third excitation electrode unit Ce3 can be electrically connected to each other. Likewise, the fourth excitation electrode unit De4 and the fourth electrode connection unit Ce4 may be provided separately, provided that the fourth excitation electrode unit De4 and the fourth electrode connection unit Ce4 can be electrically connected to each other.

[00219] For example, the third driving electrode unit De3 and the third connecting electrode unit Ce3 are disposed on the same layer. As shown in FIG. 6D, the fourth exciting electrode unit De4 and the fourth connecting electrode unit Ce4 are disposed on the same layer.

[00220] For example, similar to the first subpixel G1 and the second subpixel G2, in a direction perpendicular to the surface of the carrier substrate 10, the first light-emitting voltage supply electrode of the light-emitting element of the third sub-pixel R is located on the light-emitting layer side of the light-emitting element of the third sub-pixel R close to the intermediate layer 101, and the second light-emitting voltage supply electrode of the light-emitting element of the third sub-pixel R is located on the side of the light-emitting layer of the light-emitting element of the third sub-pixel R remotely from the intermediate layer 101; and, as shown in FIG. 6D, in a direction perpendicular to the surface of the carrier substrate 10, the first light-emitting voltage supply electrode 1201d of the light-emitting element of the fourth sub-pixel B is on the side of the light-emitting layer 1203d of the light-emitting element of the fourth sub-pixel B close to the intermediate layer 101, and the second light-emitting voltage supply electrode 1202d of the fourth sub-pixel B B is on the side of the light emitting layer 1203d of the light emitting element of the fourth subpixel B distantly from the intermediate layer 101.

[00221] For example, as shown in FIG. 6B, the intermediate layer 101 includes a third via h3, and the third connecting electrode unit Ce3 extends to the third via h3 and is electrically connected to the pixel circuit of the third sub-pixel R via the third via h3. For example, the third connecting electrode block Ce3 can cover and fill the third via h3.

[00222] For example, as shown in FIG. 6D, the intermediate layer 101 includes a fourth via h4, and the fourth connecting electrode block Ce4 extends to the fourth via h4 and is electrically connected to the pixel circuit of the fourth subpixel B via the fourth via h4. For example, the fourth connecting electrode block Ce4 may cover and fill the fourth via h4.

[00223] For example, the third connecting electrode unit Ce3 extends to the source-drain electrode metal layer of the pixel circuit through the third via h3; and the fourth electrode connection unit Ce4 extends to the source-drain electrode metal layer of the pixel circuit through the fourth via h4.

[00224] For example, the third electrode connection unit Ce3 extends to the source-drain electrode metal layer of the pixel circuit through the third via h3 to be electrically connected to the second electrode of the second light emitting control transistor of the third sub-pixel R located on the electrode metal layer " source-drain "pixel circuit. For example, the fourth connecting electrode unit Ce4 extends to the source-drain electrode metal layer of the pixel circuit through the fourth via h4 so as to be electrically connected to the second electrode of the second light-emitting control transistor of the fourth sub-pixel B located on the source-drain electrode metal layer "pixel circuitry.

[00225] For example, as shown in FIG. 6A and 6B, in each repeating cell 11, the third electrode unit Ce3 is located on the third excitation electrode unit De3 side distantly from the auxiliary electrode unit Ae of the first subpixel G1 in the first X direction, and the third electrode unit Ce3 is located on the third excitation electrode unit side De3 adjacent to the fourth excitation electrode unit De4 in the second Y direction, i.e. in the example as shown in FIG. 6A and 6B, the third electrode connection unit Ce3 is located on the lower right side of the third excitation electrode unit De3, i.e. the shape of the first light-emitting voltage supply electrode 1201c of the light emitting element of the third sub-pixel R may be a Q-shaped mirror symmetric shape.

[00226] For example, as shown in FIG. 6A and 6B, in each repeating cell 11, the fourth electrode unit Ce4 is located on the fourth excitation electrode unit De4 side distantly from the auxiliary electrode unit Ae of the first subpixel G1 in the first direction X, and the fourth electrode unit Ce4 is located on the fourth excitation electrode unit side De4 close to the third excitation electrode unit De3 in the second Y direction, i.e. in the example as shown in FIG. 6A and 6B, the fourth electrode connection unit Ce4 is disposed on the lower left side of the fourth excitation electrode unit De4, i.e. the shape of the first light-emitting voltage supply electrode 1202d of the light-emitting element of the fourth subpixel B may be a Q shape.

[00227] For example, the third connecting electrode unit Ce3 is electrically connected to the second light emitting control circuit 124c of the third subpixel pixel circuitry through the third via h3, and, for example, the third connecting electrode unit Ce3 is electrically connected to the second electrode of the second light emitting control transistor of the third subpixel pixel circuit R through the third via h3.

[00228] For example, as shown in FIG. 6D, the fourth connecting electrode unit Ce4 is electrically connected to the second light emitting control circuit 124d of the pixel circuit of the fourth subpixel B via the fourth via h4, for example, the fourth connecting electrode unit Ce4 is electrically connected to the second electrode of the second light emitting control transistor of the pixel circuit of the fourth subpixel B via the fourth via hole h4.

[00229] For example, as shown in FIG. 6B, an intermediate layer (not shown) is formed on the source-drain electrode metal layer 340 as shown in FIG. 6D, and a first light-emitting voltage supply electrode of the light-emitting element of each sub-pixel is provided on the intermediate layer. The first connecting electrode unit Ce1, the first driving electrode unit De1 and the auxiliary electrode unit Ae of the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel G1, the second connecting electrode unit Ce2 and the second driving electrode unit De2 of the first light-emitting voltage supply electrode of the light-emitting element of the second sub-pixel G2, the third the connecting electrode unit Ce3 and the third excitation electrode unit De3 of the first light-emitting voltage supply electrode of the light-emitting element of the light-emitting element of the third subpixel R and the fourth connecting electrode unit Ce4 and the fourth excitation electrode unit De4 of the first light-emitting voltage supply electrode of the light-emitting element of the fourth subpixel B are disposed on the intermediate layer, the first connecting electrode unit Ce4 the first sub-pixel unit Ce1 G1 is connected to the second light-emitting control transistor T5 in the first sub-pixel pixel circuit 121a G1 through the first via h1, the second connecting electrode unit Ce2 of the second subpixel G2 is connected to the second light emitting control transistor T5 in the pixel circuit 121b of the second subpixel G2 through the second via h2, the third electrode connecting block Ce3 of the third subpixel R is connected to the second light emitting control transistor T5 in the pixel circuit of the third subpixel R through the third via h3, and the fourth connecting electrode unit Ce4 of the fourth subpixel B is connected to the second light emitting control transistor T5 in the pixel circuit of the fourth subpixel B through the fourth via h4.

[00230] For example, the orthographic projection of the auxiliary electrode unit Ae of the first subpixel G1 on the carrier substrate at least partially overlaps with the orthographic projection of the gate electrode of the exciting transistor in the pixel circuit 121a of the first subpixel G1 on the carrier substrate, the orthographic projection of the second driving electrode unit De2 of the second subpixel G2 on the carrier substrate at least partially overlaps with the orthographic projection of the gate electrode of the driving transistor in the pixel circuit 121b of the second subpixel G2 on the carrier substrate, the orthographic projection of the third driving electrode unit De3 of the third subpixel R on the carrier substrate is at least partially overlapped with an orthographic projection of the gate electrode of the exciting transistor in the pixel circuit of the third subpixel R on the carrier substrate, and the orthographic projection of the fourth driving electrode unit De4 of the fourth subpixel B on the carrier its substrate at least partially overlaps with the orthographic projection of the gate electrode of the exciting transistor in the pixel circuit of the fourth subpixel B on the carrier substrate.

[00231] It should be noted that FIG. 6E shows drive electrode units of respective subpixels, auxiliary electrode units of respective first subpixels, and connection electrode units of respective subpixels, and FIG. 6E also shows vias corresponding to the proper connecting electrode blocks. It should be noted that the connecting electrode unit of each sub-pixel can cover and fill the corresponding via. For example, the first electrode connection unit covers and fills the first via h1, the second electrode connection unit covers and fills the second via h2, the third electrode connection unit covers and fills the third via h3, and the fourth electrode connection unit covers and fills the fourth via h4 ... However, to show the positions of the respective vias, the corresponding vias are located above the respective connecting electrode blocks in FIG. 6E.

[00232] For example, as shown in FIG. 6E, in the second direction Y, corresponding vias are arranged as a plurality of via rows, and corresponding vias in each row are arranged in the order of the third via h3, the first via h1, the fourth via h4, and the second via h2, i.e. e. the third via h3, the first via h1, the fourth via h4, and the second via h2 represent one layout period HT1, in the layout period HT1, the first via h1 corresponds to the first subpixel G1 located in the second row and adjacent to the first via h1, the second via h2 corresponds to the second subpixel G2 located in the first row and adjacent to the second via h2, the third via h3 corresponds to the third subpixel R located in the first row and adjacent to the third via h3, and the fourth via h4 corresponds to the fourth subpixel B located in the first row and adjacent to the fourth via h4.

[00233] For example, in the second Y direction, the corresponding vias in each row are located on an identical straight line, i. E. the first via h1, the third via h3, the second via h2, and the fourth via h4 in each layout period HT1 are located on the same straight line, and the layout periods HT1 are also located on the same straight line.

[00234] For example, in the second Y direction, the distance between any two adjacent vias is the first fixed distance d1, that is, as shown in FIG. 6E, in the layout period HT1, the distance between the first via h1 and the fourth via h4 is the first fixed distance d1, the distance between the first via h1 and the third via h3 is also the first fixed distance d1, the distance between the second via h2 and the third via h3 is also the first fixed distance d1, and the distance between the second via h2 and the fourth via h4 is also the first fixed distance d1. Note that “two adjacent vias” means that there is no via between two adjacent vias, and the first fixed distance d1 may represent the distance between the centers of two adjacent vias in the second Y direction.

[00235] For example, as shown in FIG. 6E, in the first X direction, the corresponding first vias h1 and the corresponding second vias h2 are arranged as a plurality of first vias columns, the corresponding third vias h3 and the corresponding fourth vias h4 are arranged as the plurality of second vias columns, and in the second in the Y direction, the first via columns and the second via columns are alternately arranged, i. e. the plurality of first via columns may be odd-numbered columns and the plurality of second via columns may be even-numbered columns. In each first via column, the corresponding first vias h1 and the corresponding second vias h2 are located on the same straight line, and in every second via column, the corresponding third vias h3 and the corresponding fourth vias h4 are also located on the same straight line.

[00236] For example, in the first X direction, the distance between any adjacent first via h1 and the second via h2 is the second fixed distance d2, the distance between any adjacent third via h3 and the fourth via h4 is the third fixed distance d3, and the second fixed distance d2 and the third fixed distance d3 are equal. It should be noted that the second fixed distance d2 may represent the distance between the center of the first via h1 and the center of the second via h2 that is adjacent to the first via h1 in the first X direction, and the third fixed distance d3 may represent the distance between the center of the third via the hole h3 and the center of the fourth via h4, which is adjacent to the third via h3 in the first X direction.

[00237] For example, a plurality of repeating cells 11 are arranged along the second Y direction to form a plurality of repeating cell groups, and a plurality of repeating cell groups are placed along the first X direction. As shown in FIG. 6E, in the first X direction, the first electrode connection unit, the second electrode connection unit, the third electrode connection unit, and the fourth electrode connection unit are located between two adjacent groups of repeating cells, and in the first X direction, at least a portion of the auxiliary electrode unit is located on to the side of the auxiliary electrode unit remotely from the first excitation electrode unit and between two adjacent repeating cells in the repeating cell group adjacent to the repeating cell group in which the auxiliary electrode unit is located. For example, in some embodiments, the P-th group of repeating cells is located in the first row, and the (P + 1) th group of repeating cells is located in the second row. For repeating cells located in the (P + 1) th repetitive cell group, at least part of the auxiliary electrode unit Ae is located on the side of the auxiliary electrode unit Ae distantly from the first excitation electrode unit De1 and between two adjacent repeating cells in the repeating cell group (i.e., in the P-th repetitive cell group) adjacent to the repetitive cell group (i.e., the (P + 1) th repetitive cell group), in which the auxiliary electrode unit Ae is located, for example, as shown in FIG. ... 6E, at least part of the auxiliary electrode block Ae in a repeating cell located in the second row extends to the first row and is located between two adjacent repeating cells located in the first row, for example, at least part of the auxiliary electrode block Ae in the repeating the cell located in the second row is located between the adjacent third subpixel R and the fourth subpixel B in the first row.

[00238] For example, as shown in FIG. 6C, the second light emitting drive transistor of the second light emitting drive circuit 124a of the first subpixel G1 includes a second electrode 1241a (eg, a drain electrode) and an active layer 1242a. The drive transistor of the drive circuit of the first subpixel G1 includes a gate electrode 1221a (i.e., a control terminal of the drive circuit 122a) and an active layer 1222a. It should be noted that FIG. 6C does not show the gate electrode and the first electrode of the second light emitting control transistor of the first subpixel G1 and the first electrode and the second drive transistor electrode of the first subpixel G1, etc.

[00239] For example, an insulating gate layer is sandwiched between the active semiconductor layer 310 and the first conductive layer 320, that is, as shown in FIG. 6C, an insulating gate layer 131 is located between the drive transistor gate electrode 1221a of the first subpixel G1 and the drive transistor active layer 1222a of the first subpixel G1, and the insulating gate layer 131 covers the entire display substrate 100, whereby the insulating gate layer 131 is also located between the gate electrode and the active layer of the second light-emitting control transistor. The gate electrode 1221a of the driving transistor of the first subpixel G1 is located on the side of the insulating gate layer 131 distantly from the carrier substrate 10. As shown in FIG. 6C, the first light control signal line EM1a connected to the first light emitting control circuit of the first subpixel G1, and the second light control signal line EM2a connected to the second light emitting control circuit of the first subpixel G1 are also disposed on the side of the insulating gate layer 131 remotely from the carrier substrate 10. ...

[00240] For example, as shown in FIG. 6C, the orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate 10 overlaps at least partially with the orthographic projection of the second light control signal line EM2a (i.e., the first light control signal line EM1a connected to the first light emitting control circuit of the first subpixel G1 ) connected to the second light-emitting control circuit of the pixel circuit of the first sub-pixel G1 on the carrier substrate 10.

[00241] For example, as shown in FIG. 6C, the first insulating layer 132 is further provided on the gate electrode 1221a of the driving transistor of the first subpixel G1, and the first electrode CC1a of the third capacitor C2 of the first subpixel G1 is provided on the side of the first insulating layer 132 distantly from the carrier substrate 10. The second insulating layer 133 is provided on the side of the second electrode CC2a of the third capacitor C2 remotely from the carrier substrate 10. The second electrode 1241a of the second light emitting control transistor of the first subpixel G1 is located on the side of the second insulating layer 133 remotely from the carrier substrate 10 and is electrically connected to the active layer 1242a of the second light emitting control transistor through the via 388a penetrating through the second insulating layer 133, the first insulating layer 132 and the insulating gate layer 131. For example, the first insulating layer 132 and the second insulating layer 133 also cover the entire display substrate 100.

[00242] For example, the first connecting portion 341a of the first subpixel G1 is also provided on the side of the second insulating layer 133 remotely from the carrier substrate 10. The first connecting portion 341a of the first subpixel G1 is electrically connected to the gate electrode 1221a of the driving transistor of the first subpixel G1 through a via 385a penetrating through the second insulating layer 133, the first electrode CC1a of the third capacitor C2, the first subpixel G1, and the first insulating layer 132. The orthographic projection of the first connecting portion 341a on the carrier substrate 10 overlaps at least partially with the orthographic projection of the gate electrode 1221a of the driving transistor of the first subpixel G1 on the carrier substrate 10, i.e. the orthographic projection of the first connecting portion 341a on the carrier substrate 10, the orthographic projection of the gate electrode 1221a of the driving transistor of the first subpixel G1 on the supporting substrate 10, and the orthographic projection of the auxiliary electrode unit Ae on the supporting substrate 10 at least partially overlap.

[00243] It should be noted that for the first subpixel G1, in a direction perpendicular to the carrier substrate 10, metal layers such as the first electrode CC1a of the third capacitor C2 of the first subpixel G1, the first connecting portion 341a of the first subpixel G1, and the like are additionally provided between the first electrode CC3a (i.e., the auxiliary electrode unit Ae) and the second electrode CC4a (i.e., the gate electrode 1221a of the driving transistor of the first subpixel G1) of the first capacitor C11. Therefore, parasitic capacitance may also occur between the auxiliary electrode unit Ae and the first connecting portion 341a of the first subpixel G1, and parasitic capacitance may also occur between the auxiliary electrode unit Ae and the first electrode CC1a of the third capacitor C2 of the first subpixel G1, and parasitic capacitance may also occur between the first electrode CC1a of the third capacitor C2 of the first subpixel G1 and the first connecting portion 341a of the first subpixel G1, parasitic capacitance may also occur between the gate electrode 1221a of the driving transistor of the first subpixel G1 and the first connecting portion 341a of the first subpixel G1, and parasitic capacitance may also occur between the gate electrode 1221a the first subpixel G1; and the first electrode CC1a of the third capacitor C2 of the first subpixel G1. The positions and sizes of these parasitic capacitances are associated with a particular arrangement of the display substrate, and the present disclosure does not detail these parasitic capacitances.

[00244] For example, the second electrode 1241a of the second light emitting control transistor of the first subpixel G1 and the first connecting portion 341a are disposed in the source-drain electrode metal layer 340 of the pixel circuit, the gate electrode 1221a of the driving transistor of the first subpixel G1, and the first light control signal line EM1a / a second light emitting control signal line EM2a is disposed in a first conductive layer 320 of the pixel circuit, a first electrode CC1a of a third capacitor C2 of a first subpixel G1 is disposed in a second conductive layer 330 of a pixel circuit, and an active layer 1242a of a second light emitting control transistor and an active layer 1222a of a driving transistor of the first subpixel G1 located in the active semiconductor layer 310 of the pixel circuit.

[00245] For example, the first connecting electrode unit Ce1 extends to the source-drain electrode metal layer 340 of the pixel circuit through the first via h1, so as to electrically connect to the second electrode 1241a of the second light emitting control transistor of the first subpixel G1 located in the electrode metal layer 340 "source-drain" of the pixel circuit.

[00246] For example, as shown in FIG. 6C, in a direction perpendicular to the carrier substrate 10, a first power and reset line Init1b / a second power and reset line Init2b connected to a pixel circuit of a second subpixel G2, at least a portion of a second connecting portion 342b of a second subpixel G2 and a via 386b are provided between the first connecting electrode unit Ce1 and the carrier substrate 10, and the second connecting portion 342b of the second subpixel G2 is electrically connected to the first power and reset signal line Init1b / second power and reset signal line Init2b through the via 386b.

[00247] For example, the first power and reset line Init1b / the second power and reset line Init2b is located in the second conductive layer 330 of the pixel circuit.

[00248] For example, as shown in FIG. 6C, in a direction perpendicular to the carrier substrate 10, a first reset control signal line Rst1a / a second reset control signal line Rst2a connected to the pixel circuit of the second subpixel G2, at least a portion of the second connecting portion 342b of the second subpixel G2, at least a portion the first connecting portion 341b of the second subpixel G2, the via 387b, the via 384b, the second electrode 1291b of the first reset transistor T6 of the second subpixel G2 (also the second electrode of the threshold compensation transistor T3 of the second subpixel G2), the first electrode 1292b of the first reset transistor T6 of the second subpixel G2 ( also, the first electrode of the second reset transistor T7 of the second subpixel G2) is disposed between the first excitation electrode unit De1 and the carrier substrate 10, the second connecting portion 342b of the second subpixel G2 is electrically connected to the first electrode 1292b of the first reset transistor T6 of the second subpixel G2 via a transition hole 387b, and the first connecting portion 341b of the second subpixel G2 is electrically connected to the second electrode 1291b of the first reset transistor T6 of the second subpixel G2 through the via 384b.

[00249] For example, as shown in FIG. 6C, the second light emitting drive transistor of the second light emitting drive circuit 124b of the second subpixel G2 includes a second electrode 1241b (eg, a drain electrode) and an active layer 1242b. The driving transistor of the driving circuit of the second subpixel G2 includes a gate electrode 1221b (i.e., a control terminal of the driving circuit 122b) and an active layer 1222b. It should be noted that FIG. 6C does not show the gate electrode and the first electrode of the second light emitting control transistor of the second subpixel G2 and the first electrode and the second drive transistor electrode of the second subpixel G2, etc.

[00250] For example, an insulating gate layer 131 is also provided between the gate electrode 1221b and the drive transistor active layer 1222b of the second subpixel G2. The first insulating layer 132 is also provided on the gate electrode 1221b of the driving transistor of the second subpixel G2. The first electrode CC1b of the third capacitor C2 of the second subpixel G2 is provided on the side of the first insulating layer 132 remotely from the carrier substrate 10. The second electrode 1241b of the second light emitting control transistor of the second subpixel G2 is located on the side of the second insulating layer 133 remotely from the carrier substrate 10 and is electrically connected to the active layer 1242b of the second light emitting control transistor of the second subpixel G2 through a via 388b penetrating the second insulating layer 133, the first insulating layer 132, and the insulating gate layer 131.

[00251] For example, as shown in FIG. 6C, a first light emitting control signal line EM1b connected to the first light emitting driving circuit of the second subpixel G2, and a second light emitting control signal line EM2b connected to the second light emitting driving circuit are also provided on the side of the insulating gate layer 131 remotely from the carrier substrate 10.

[00252] For example, as shown in FIG. 6C, the orthographic projection of the second connecting electrode unit Ce2 on the carrier substrate 10 at least partially overlaps with the orthographic projection of the second light control signal line EM2b connected to the second light emitting control circuit of the pixel circuit of the second sub-pixel G2 (i.e., the first signal line EM1b a light-emitting control connected to the first light-emitting driving circuit of the second sub-pixel G2) on the carrier substrate 10.

[00253] For example, as shown in FIG. 6C, a first scanning signal line Ga1b electrically connected to the data recording transistor of the second subpixel G2, and a second scanning signal line Ga2b electrically connected to the threshold compensation transistor of the second subpixel G2 are also provided on the side of the insulating gate layer 131 remotely from the carrier substrate 10.

[00254] For example, the first connecting portion 341b of the second subpixel G2 is further provided on the side of the second insulating layer 133 remotely from the carrier substrate 10, and the first connecting portion 341b of the second subpixel G2 is electrically connected to the gate electrode 1221b of the driving transistor of the second subpixel G2 through the via 385b, penetrating through the second insulating layer 133, the first electrode CC1b of the third capacitor C2 of the second subpixel G2, and the first insulating layer 132. The orthographic projection of the first connecting portion 341b of the second subpixel G2 on the carrier substrate 10 at least partially overlaps the orthographic projection of the gate electrode 1221b of the driving transistor the second subpixel G2 on the carrier substrate 10, i.e. the orthographic projection of the first connecting portion 341b on the carrier substrate 10, the orthographic projection of the gate electrode 1221b of the driving transistor of the second subpixel G2 on the carrier substrate 10, and the orthographic projection of the second driving electrode unit De2 on the carrier substrate 10 at least partially overlap.

[00255] It should be noted that, for the second sub-pixel G2, in a direction perpendicular to the carrier substrate 10, metal layers such as the first electrode CC1b of the third capacitor C2 of the second sub-pixel G2, the first connecting portion 341b of the second sub-pixel G2, and the like are also provided. between the first electrode CC1b (i.e., the second driving electrode unit De2) and the second electrode (i.e., the gate electrode 1221b of the driving transistor of the second subpixel G2) of the second capacitor C12. Therefore, parasitic capacitance may also occur between the second driving electrode unit De2 and the first connecting portion 341b of the second subpixel G2, and parasitic capacitance may also occur between the second excitation electrode unit De2 and the first electrode CC1b of the third capacitor C2 of the second subpixel G2, and parasitic capacitance may also occur between the first electrode CC1b of the third capacitor C2 of the second subpixel G2 and the first connecting portion 341b of the second subpixel G2, parasitic capacitance may also occur between the gate electrode 1221b of the driving transistor of the second subpixel G2 and the first connecting portion 341b of the second subpixel G2, and parasitic capacitance may also occur between the gate electrode 1221b the driving transistor of the second subpixel G2; and the first electrode CC1b of the third capacitor C2 of the second subpixel G2. The positions and sizes of these parasitic capacitances are associated with a particular arrangement of the display substrate, and the present disclosure does not detail these parasitic capacitances.

[00256] For example, the second electrode 1241b of the second light emitting control transistor of the second subpixel G2 and the first connecting portion 341b are disposed in the source-drain electrode metal layer 340 of the pixel circuit, the gate electrode 1221b of the driving transistor of the second subpixel G2, and the first light emitting control signal line EM1b / a second light emitting control signal line EM2b is located in the first conductive layer 320 of the pixel circuit, the first electrode CC1b of the third capacitor C2 of the second subpixel G2 is located in the second conductive layer 330 of the pixel circuit, and the active layer 1242b of the second light emitting control transistor and the active layer 1222b of the driving transistor of the second subpixel G2 located in the active semiconductor layer 310 of the pixel circuit.

[00257] For example, the second electrode connection unit Ce2 extends to the source-drain electrode metal layer 340 of the pixel circuit through the second via h2 so as to electrically connect to the second electrode 1241b which is disposed in the source-drain electrode metal layer 340 "pixel circuit of the second light emitting control transistor of the second subpixel G2.

[00258] For example, as shown in FIG. 6B and 6C, the shape of the overlapping portion between the orthographic projection of the first light-emitting voltage electrode of the second subpixel G2 on the carrier substrate and the orthographic projection of the active semiconductor layer corresponding to the pixel circuit of the second subpixel G2 on the carrier substrate may include a "" shape, and a portion of the active of the semiconductor layer corresponding to the shape "" includes an active layer of a driving transistor of the pixel circuit of the second subpixel G2. In a direction perpendicular to the carrier substrate, a part of the active semiconductor layer corresponding to the pixel circuit of the second subpixel G2 overlapping with the first light-emitting voltage supply electrode of the second subpixel G2 may include an active layer of a driving transistor of the pixel circuit of the second subpixel G2. In addition, the part of the active semiconductor layer corresponding to the pixel circuit of the second subpixel G2 overlapping with the first light emitting voltage supply electrode of the second subpixel G2 may further include a drain portion of the second light emitting control transistor T5 of the pixel circuit of the second subpixel G2.

[00259] For example, as shown in FIG. 6B and 6C, the orthographic projection of the first light-emitting voltage supply electrode of the second subpixel G2 on the carrier substrate overlaps with the orthographic projection of the source-drain electrode metal layer corresponding to the pixel pattern of the second subpixel G2 on the carrier substrate. In the direction perpendicular to the carrier substrate, a portion of the source-drain metal layer corresponding to the pixel circuit of the second subpixel G2 overlapped with the first light-emitting voltage supply electrode of the second subpixel G2 includes a portion of the first connecting portion (i.e., a portion of the first connecting portion overlapping with the gate electrode of the driving transistor of the pixel circuit of the second subpixel G2) and the third connecting portion (i.e., the drain electrode of the second light emitting control transistor T5 of the pixel circuit of the second subpixel G2), a portion of the first power signal line VDD1, and the like.

[00260] For example, as shown in FIG. 6B and 6C, in a direction perpendicular to the carrier substrate, a portion of the active semiconductor layer corresponding to the pixel circuit of the second subpixel G2 overlapped with the first light emitting voltage supply electrode of the first subpixel G1 may include active layers and drain portions of the first reset transistor T6 and the second transistor T7 reset in the reset circuit 129b of the pixel circuit of the second subpixel G2, a part of the active layer ("Π" shape) of the drive transistor in the pixel circuit of the first subpixel G1, and a drain portion of the second light emitting control transistor T5 of the pixel circuit of the first subpixel G1.

[00261] For example, as shown in FIG. 6B and 6C, the orthographic projection of the first light-emitting voltage supply electrode of the first subpixel G1 on the carrier substrate partially overlaps with the orthographic projection of the source-drain electrode metal layer corresponding to the pixel circuit of the first subpixel G1 on the carrier substrate, and the orthographic projection of the source-drain electrode metal layer drain "corresponding to the pixel pattern of the second sub-pixel G2 on the carrier substrate. For example, in a direction perpendicular to the carrier substrate, a portion of the source-drain electrode metal layer corresponding to the pixel circuit of the second subpixel G2 overlapped with the first light-emitting voltage supply electrode of the first subpixel G1 includes a portion of the first connecting portion (i.e., a portion the first connecting part overlapping with the drain portion of the threshold compensation transistor), the second connecting part (i.e., the connecting part between the drain electrode of the second reset transistor of the pixel circuit of the second subpixel G2 and the first power supply and reset signal line), a portion of the first power supply signal line VDD1, and etc. The portion of the source-drain electrode metal layer corresponding to the pixel circuit of the first subpixel G1 overlapping with the first light-emitting voltage supply electrode of the first subpixel G1 includes a portion of the first connecting portion (i.e., a portion of the first connecting portion overlapping with the gate electrode of the exciting of the pixel circuit transistor of the first subpixel G1) and the third connecting portion (i.e., the drain electrode of the second light emitting control transistor of the pixel circuit of the first subpixel G1), etc. For example, as shown in FIG. 6D, the second light emitting drive transistor of the second light emitting drive circuit 124d of the fourth subpixel B includes a second electrode 1241d (eg, a drain electrode) and an active layer 1242c. The driving transistor of the driving circuit of the third subpixel R includes a gate electrode 1221d (i.e., a control terminal of the driving circuit 122d) and an active layer 1222d. It should be noted that FIG. 6D does not show the gate electrode and the first electrode of the second light emitting control transistor of the fourth subpixel B and the first electrode and the second drive transistor electrode of the fourth subpixel B, etc.

[00262] For example, as shown in FIG. 6D, an insulating gate layer 131 is provided between the gate electrode 1221d and an active layer 1222d of a driving transistor of the fourth subpixel B, and the first insulating layer 132 is also provided on the gate electrode 1221d of a driving transistor of the fourth subpixel B. The first electrode CC1d of the third capacitor C2 of the fourth subpixel B is provided on the side of the first insulating layer 132 remotely from the carrier substrate 10. The second electrode 1241d of the second light emitting control transistor of the fourth subpixel B is located on the side of the second insulating layer 133 remotely from the carrier substrate 10 and is electrically connected to the active layer 1242d of the second light emitting control transistor of the fourth subpixel B via the via 388d penetrating through the second insulating layer 133, the first insulating layer 132 and the insulating barrier layer 131.

[00263] For example, as shown in FIG. 6D, a first light control signal line EM1d connected to the first light emitting driving circuit of the fourth subpixel B and a second light control signal line EM2d connected to the second light emitting control circuit are also provided on the side of the insulating gate layer 131 remotely from the carrier substrate 10. For example, as shown in FIG. 6B and 6C, for the fourth subpixel B located in the second row, the first light control signal line EM1d and the second light control signal line EM2d corresponding to the fourth subpixel B are the same signal line, and the first light control signal line EM1d / second line EM2d light control signals and the first light control signal line EM1b / second light control signal line EM2b corresponding to the second sub-pixel G2 located in the second row are also the same signal line.

[00264] For example, as shown in FIG. 6D, the orthographic projection of the fourth connecting electrode unit Ce4 on the carrier substrate 10 at least partially overlaps with the orthographic projection of the second light control signal line EM2d connected to the second light emitting control circuit of the pixel circuit of the fourth subpixel B (i.e., the first signal line EM1d light emitting control connected to the first light emitting driving circuit of the fourth subpixel B) on the carrier substrate 10.

[00265] For example, as shown in FIG. 6D, a first scan signal line Ga1d electrically connected to the data recording transistor of the fourth subpixel B, and a second scan signal line Ga2d electrically connected to the threshold compensation transistor of the fourth subpixel B are also provided on the side of the insulating gate layer 131 remotely from the carrier substrate 10. For example as shown in FIG. 6B and 6C, for the fourth sub-pixel B located in the second row, the first scanning signal line Ga1d and the second scanning signal line Ga2d corresponding to the fourth sub-pixel B are the same signal line, and the first scanning signal line Ga1d / second scanning signal line Ga2d and the first scan signal line Ga1b / second scan signal line Ga2b corresponding to the second subpixel G2 located in the second row are also the same signal line.

[00266] For example, the first connecting portion 341d of the fourth subpixel B is also provided on the side of the second insulating layer 133 remotely from the carrier substrate 10, and the first connecting portion 341d of the fourth subpixel B is electrically connected to the gate electrode 1221d of the driving transistor of the fourth subpixel B via the via 385d, penetrating through the second insulating layer 133, the first electrode CC1d of the third capacitor C2 of the fourth subpixel B, and the first insulating layer 132. The orthographic projection of the first connecting portion 341d of the fourth subpixel B on the carrier substrate 10 at least partially overlaps the orthographic projection of the gate electrode 1221d of the driving transistor the fourth subpixel B on the carrier substrate 10, i.e. the orthographic projection of the first connecting portion 341d on the carrier substrate 10, the orthographic projection of the gate electrode 1221d of the driving transistor of the fourth subpixel B on the carrier substrate 10, and the orthographic projection of the fourth driving electrode unit De4 on the carrier substrate 10 at least partially overlap.

[00267] It should be noted that, for the fourth sub-pixel B, in a direction perpendicular to the carrier substrate 10, metal layers such as the first electrode CC1d of the third capacitor C2 of the fourth sub-pixel B, the first connecting portion 341d of the fourth sub-pixel B, and the like are also provided. between the fourth driving electrode unit De4 and the gate electrode 1221d of the driving transistor of the fourth subpixel B. Therefore, parasitic capacitance may also occur between the fourth driving electrode unit De4 and the first connecting portion 341d of the fourth subpixel B, and parasitic capacitance may also occur between the fourth driving electrode unit De4 and the first electrode CC1d of the third capacitor C2 of the fourth subpixel B, stray capacitance may also occur between the first electrode CC1d of the third capacitor C2 of the fourth subpixel B and the first connecting portion 341d of the fourth subpixel B, and stray capacitance may also occur between the gate The driving transistor gate 1221d of the fourth subpixel B and the first connecting portion 341d of the fourth subpixel B, and parasitic capacitance may also occur between the gate electrode 1221d of the driving transistor of the fourth subpixel B and the first electrode CC1d of the third capacitor C2 of the fourth subpixel B. The positions and sizes of these capacitances are related with a specific layout structure of the display substrate, and the present disclosure does not detail these stray capacitances.

[00268] For example, as shown in FIG. 6D, a first power and reset line Init1d / a second power and reset line Init2 connected to the fourth subpixel pixel circuit B and via 386d is provided on the carrier substrate 10. At least a portion of the second connecting portion 342d of the fourth subpixel B is provided between the fourth driving electrode unit Ce1 and the carrier substrate 10 in a direction perpendicular to the carrier substrate 10, and the second connecting portion 342d of the fourth subpixel B is electrically connected to the first power supply and reset line Init1d / second power and reset signal line Init2d through the via 386d.

[00269] For example, as shown in FIG. 6D, in a direction perpendicular to the carrier substrate 10, a first reset control signal line Rst1d / a second reset control signal line Rst2d connected to the pixel circuit of the fourth subpixel B, at least part of the second connecting portion 342d of the fourth subpixel B, the first connecting portion 341d of the fourth subpixel B, via 387d, via 384d, second electrode 1291d of the first reset transistor T6 of the fourth subpixel B (also the second electrode of the threshold compensation transistor T3 of the fourth subpixel B), the first electrode 1292d of the first reset transistor T6 of the fourth subpixel B (also the first electrode of the second transistor T7 reset of the fourth subpixel B) are provided between the fourth drive electrode unit De4 and the carrier substrate 10, the second connecting portion 342d of the fourth subpixel B is electrically connected to the first electrode 1292d of the first reset transistor T6 of the fourth subpixel B via a transition hole 387d, and the first connecting portion 341d of the fourth subpixel B is electrically connected to the second electrode 1291d of the first reset transistor T6 of the fourth subpixel B via the via 384d.

[00270] For example, the second electrode 1241d of the second light emitting control transistor of the fourth subpixel B and the first connecting portion 341d are disposed in the source-drain electrode metal layer 340 of the pixel circuit, the gate electrode 1221d of the driving transistor of the fourth subpixel B, and the first light emitting control signal line EM1d / the second line EM2d of light control signals are located in the first conductive layer 320 of the pixel circuit of the fourth subpixel B, the first electrode CC1d of the third capacitor C2 of the fourth subpixel B and the first line Init1d of power and reset signals / the second line Init2d of signals of power and reset are located in the second conductive layer 330 of the pixel circuits, and the active layer 1242d of the second light emitting control transistor and the active layer 1222d of the driving transistor of the fourth subpixel B are located in the active semiconductor layer 310 of the pixel circuit.

[00271] For example, the fourth connecting electrode unit Ce4 extends to the source-drain electrode metal layer of the pixel circuit through the fourth via h4 so as to be electrically connected to the second electrode 1241d, which is located in the source-drain electrode metal layer of the pixel circuit. circuits of the second light-emitting control transistor of the fourth subpixel B.

[00272] For example, the connection relationship between respective circuits (eg, drive circuit, first light emitting drive circuit, second light emitting drive circuit, data storage circuit, reset circuit, threshold compensation circuit, data recording circuit, etc.) of the third subpixel pixel circuit R and the connection relationship between respective pixel circuit circuits of the fourth subpixel B are identical to the example as shown in FIG. 3A.

[00273] An embodiment of the present disclosure also provides a display substrate. As shown in FIG. 2, the display substrate 100 includes a carrier substrate 10 and a plurality of repeating cells 11 on the carrier substrate 10, each repeating cell 11 includes a plurality of subpixels 12. Each subpixel 12 includes a light emitting element 120 and a pixel circuit 121 for driving the light emitting element 120 for emitting light, and the pixel circuit 121 includes a drive circuit 122.

[00274] For example, as shown in FIG. 5A, driving circuits 122 of a plurality of subpixels 12 are arranged in an array on a carrier substrate 10. For example, portions 31-40 may be portions in which driving circuits of respective subpixels are located on a carrier substrate 10. In an example, as shown in FIG. 5A, two rows and five columns of the driver circuits are shown. For example, in the example as shown in FIG. 3A, in a repeating cell 11 surrounded by dashed lines, a driving circuit of the pixel circuit of the first subpixel G1 is located in a portion 32, a driving circuit of a pixel circuit of a second subpixel G2 is located in a portion 37, a driving circuit of a pixel circuit of a third subpixel R is located in a portion 38, and a driving circuit a pixel circuit diagram of the fourth subpixel B is located in a portion 36.

[00275] It should be noted that in the present disclosure, "row" may represent a row corresponding to areas in which respective pixel patterns are located, and a "column" may represent a column corresponding to areas in which respective pixel patterns are located.

[00276] For example, the light emitting element 120 of each subpixel includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode. For example, in some embodiments, the first light-emitting voltage supply electrode is an anode and the second light-emitting voltage supply electrode is a cathode.

[00277] For example, as shown in FIG. 5A and 6A, the plurality of subpixels 12 include a first subpixel G1 and a second subpixel G2. For example, the color of light emitted by the light emitting element of the first subpixel G1 is the same as the color of the light emitted by the light emitting element of the second subpixel G2, for example, both the first subpixel G1 and the second subpixel G2 are green subpixels.

[00278] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel G1 and the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel G2 are disposed in the first X direction.

[00279] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode 1201a of the light-emitting element of the first subpixel G1 includes an auxiliary electrode unit Ae, a first excitation electrode unit De1 and a first connecting electrode unit Ce1 and an auxiliary electrode unit Ae, a first excitation electrode unit De1 and a first connecting electrode unit Ce1 electrically interconnected.

[00280] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode 1201b of the light-emitting element of the second sub-pixel G2 includes a second excitation electrode unit De2 and a second excitation electrode unit Ce2, and the second excitation electrode unit De2 is electrically connected to the second excitation electrode unit Ce2.

[00281] For example, the area of the first light-emitting voltage supply electrode 1201a of the light-emitting element of the first subpixel G1 is different from the area of the first light-emitting voltage electrode 1201b of the light-emitting element of the second subpixel G2, for example, the area of the first light-emitting voltage electrode 1201a of the light-emitting element of the first subpixel G1 is larger than the area of the first electrode 1201a. 1201b supplying a light-emitting voltage to the light emitting element of the second subpixel G2.

[00282] For example, as shown in FIG. 6B, the auxiliary electrode unit Ae is located on the control terminal side of the driving circuit of the pixel circuit of the first subpixel G1 remotely from the carrier substrate 10, and the second driving electrode unit De2 is located on the control terminal side of the driving circuit of the pixel circuit of the second subpixel G2 remotely from the carrier substrate 10. For example, the shape of the auxiliary electrode unit Ae is different from that of the second excitation electrode unit De2, i.e. the shape of the anode portion of the first subpixel G1 located on the control terminal side of the driving circuit of the pixel circuit of the first subpixel G1 remotely from the carrier substrate 10 differs from the shape of the anode portion of the second subpixel G2 located on the control terminal side of the driving circuit of the pixel circuit of the second subpixel G2 remotely from carrier substrate 10.

[00283] For example, as shown in FIG. 3A, the driving circuit 122 of the pixel circuit 121 of each sub-pixel includes a driving transistor T1. The auxiliary electrode unit Ae is disposed on the gate electrode side of the excitation transistor T1 of the pixel circuit of the first subpixel G1 remotely from the carrier substrate 10, and the second excitation electrode unit De2 is disposed on the gate electrode side of the excitation transistor T1 of the pixel circuit of the second subpixel G2 remotely from the carrier substrate 10.

[00284] For example, the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate at least partially overlaps with the orthographic projection of the gate electrode of the driving transistor T1 of the pixel circuit of the first subpixel G1 on the carrier substrate, and the orthographic projection of the second driving electrode unit De2 on the carrier substrate, at least partially overlaps with the orthographic projection of the gate electrode of the driving transistor T1 of the pixel circuit of the second subpixel G2 on the carrier substrate.

[00285] For example, a region of overlapping portion between the orthographic projection of the auxiliary electrode unit Ae on the carrier substrate and the orthographic projection of the gate electrode of the driving transistor T1 of the pixel circuit of the first subpixel G1 on the carrier substrate constitutes the first region, the region of the overlapping portion between the orthographic projection of the second driving electrode unit De2 on the carrier substrate and the orthographic projection of the gate electrode of the driving transistor T1 of the pixel circuit of the second subpixel G2 on the carrier substrate constitutes the second region, and the ratio of the first region to the second region satisfies the following relationship:

Amin≤A1 / A2≤Amax,

where A1 represents the first region, A2 represents the second region, Amin represents the minimum threshold value of the ratio and is 90%, and Amax represents the maximum threshold value of the ratio and is 110%.

[00286] For example, as shown in FIG. 6A and 6B, the shape of the first excitation electrode unit De1 is different from that of the auxiliary electrode unit Ae, and the shape of the first excitation electrode unit De1 is the same as that of the second excitation electrode unit De2. For example, the shape of the first excitation electrode unit De1 and the shape of the second excitation electrode unit De2 may be pentagons, and the shape of the auxiliary electrode unit Ae may be a rectangle. However, the present disclosure is not limited to this case. The shape of the first excitation electrode unit De1 and the shape of the second excitation electrode unit De2 may also be rectangles or the like, and the shape of the auxiliary electrode unit Ae may be a pentagon, a hexagon, an ellipse, and the like.

[00287] For example, the orthographic projection area of the first exciting electrode unit De1 on the carrier substrate 10 is identical to the orthographic projection area of the second exciting electrode unit De2 on the carrier substrate 10.

[00288] For example, as shown in FIG. 6A and 6B, the shape of the first electrode connection unit Ce1 may be the same as that of the second electrode connection unit Ce2. For example, the shape of the first electrode connection unit Ce1 and the shape of the second electrode connection unit Ce2 may be rectangles.

[00289] For example, the orthographic projection area of the first connecting electrode unit Ce1 on the carrier substrate 10 is the same as the orthographic projection area of the second connecting electrode unit Ce2 on the carrier substrate 10.

[00290] It should be noted that in some embodiments of the present disclosure, the shape of the first connecting electrode unit Ce1 may also be different from the shape of the second connecting electrode unit Ce2, and / or the orthographic projection area of the first connecting electrode unit Ce1 on the carrier substrate 10 may also be different from orthographic projection areas of the second connecting electrode unit Ce2 on the carrier substrate 10.

[00291] For example, as shown in FIG. 6B, the driving terminal of the pixel circuit driving circuit of the first subpixel G1 and the driving terminal of the driving circuit of the pixel circuit of the second subpixel G2 are arranged in the first X direction, i.e. The gate electrode of the driving transistor T1 of the pixel circuit of the first subpixel G1 and the gate electrode of the driving transistor T1 of the pixel circuit of the second subpixel G2 are disposed in the first direction X.

[00292] For example, as shown in FIG. 6B, in the first direction X, the first electrode unit De1 is disposed on the side of the driving terminal of the driving circuit of the pixel circuit of the first subpixel G1 adjacent to the driving terminal of the driving circuit of the pixel circuit of the second subpixel G2. For example, in some examples, as shown in FIG. 6B, in the first direction X, the first electrode unit De1 is disposed between the driving terminal of the driving circuit of the pixel circuit of the first subpixel G1 and the driving terminal of the driving circuit of the pixel circuit of the second subpixel G2.

[00293] For example, as shown in FIG. 6B, in the first X direction, the first electrode connection unit Ce1 is located on the side of the first excitation electrode unit De1 remotely from the control terminal of the driving circuit of the pixel circuit of the second subpixel G2. For example, in the first X direction, the first electrode connection unit Ce1 is disposed between the driving terminal of the pixel circuit driving circuit of the first subpixel G1 and the driving terminal of the driving circuit of the pixel circuit of the second subpixel G2. In other words, in the first X direction, the first electrode connecting unit Ce1 and the first driving electrode unit De1 are disposed between the driving terminal of the driving circuit of the pixel circuit of the first subpixel G1 and the driving terminal of the driving circuit of the pixel circuit of the second subpixel G2.

[00294] For example, in the first X direction, the first electrode connection unit Ce1 is disposed on the side of the first excitation electrode unit De1 remotely from the second excitation electrode unit De2, i.e. the first excitation electrode unit De1 is disposed between the first connecting electrode unit Ce1 and the second excitation electrode unit De2.

[00295] For example, in the first X direction, the first electrode connection unit Ce1 is disposed between the first excitation electrode unit De1 and the auxiliary electrode unit Ae, i. E. the auxiliary electrode unit Ae is located on the side of the first electrode connection unit Ce1, distantly from the first excitation electrode unit De1.

[00296] For example, in the first X direction, the second connecting electrode unit Ce2 is located on the side of the driving terminal of the driving circuit of the pixel circuit of the second subpixel G2 remotely from the driving terminal of the driving circuit of the first subpixel G1.

[00297] For example, in the first X direction, the second driving electrode unit De2 is disposed between the second connecting electrode unit Ce2 and the first driving electrode unit De1, i.e. the second connecting electrode unit Ce2 is located on the side of the second excitation electrode unit De2 remotely from the first excitation electrode unit De1.

[00298] For example, as shown in FIG. 5A, the plurality of sub-pixels 12 further include a third sub-pixel R and a fourth sub-pixel B. For example, the first light-emitting voltage supply electrode of the light-emitting element of the third sub-pixel R and the first light-emitting voltage supply electrode of the light-emitting element of the fourth sub-pixel B are disposed in the second Y direction. The first X direction and the second Y directions are perpendicular to each other.

[00299] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode of the light-emitting element of the third subpixel R includes the third driving electrode unit De3 and the third connecting electrode unit Ce3, and the third driving electrode unit De3 and the third connecting electrode unit Ce3 are electrically connected to each other. For example, the orthographic projection of the third driving electrode unit De3 on the carrier substrate at least partially overlaps with the orthographic projection of the driving terminal of the driving circuit of the pixel circuit of the third subpixel R on the carrier substrate.

[00300] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode of the light emitting element of the fourth subpixel B includes the fourth driving electrode unit De4 and the fourth connecting electrode unit Ce4, and the fourth driving electrode unit De4 and the fourth connecting electrode unit Ce4 are electrically connected to each other. For example, as shown in FIG. 6B, the fourth driving electrode unit De4 is disposed on the driving terminal side of the driving circuit of the pixel circuit of the fourth subpixel B distantly from the carrier substrate 10, for example, an orthographic projection of the fourth driving electrode unit De4 on the carrier substrate at least partially overlaps the orthographic projection of the driving pin outputting the driving circuit of the pixel circuit of the fourth subpixel B on the carrier substrate.

[00301] For example, in the first X direction, the distance between the center of the driving circuit control terminal (i.e., the gate electrode of the driving transistor) of the pixel circuit of the first subpixel G1 and the center of the first driving electrode unit De1 is greater than the distance between the center of the driving pin of the driving circuit of the pixel the circuitry of the second sub-pixel G2 and the center of the second excitation electrode unit De2.

[00302] It should be noted that in the present disclosure, "center" may represent the geometric center of the element's physical shape. When designing a pixel arrangement, elements such as the gate electrode of the drive transistor and the anode of the light emitting element are generally designed to have regular shapes such as rectangle, hexagon, pentagon, trapezoid, or other shapes. When designed, the center of the element (for example, the gate electrode of the driving transistor or the anode of the light emitting element, etc.) may be the geometric center of the above regular shape. However, in the actual manufacturing process, the shapes of elements such as the gate electrode of the drive transistor and the anode of the light emitting element that are formed generally deviate from the regular shapes designed above. For example, the corresponding corners of the above regular shapes may be rounded so that the shapes of elements such as a gate electrode of a driving transistor, an anode of a light emitting element, etc., may be rim shapes. In addition, the shapes of the elements, such as the gate electrode of the driving transistor and the anode of the light emitting element, which are actually manufactured, may also have other variations with respect to the design shapes. For example, the shape of a subpixel designed as a hexagon may become approximately elliptical in the actual manufacturing process. Therefore, the centers of elements such as the gate electrode of the driving transistor and the anode of the light-emitting element may not represent strict geometric centers of irregularly shaped subpixels. In an embodiment of the present disclosure, the center of the element may be offset from the geometric center of the shape of the element. In addition, "center" can also represent the center of gravity of the element.

[00303] An embodiment of the present disclosure also provides a display substrate. As shown in FIG. 2, the display substrate 100 includes a carrier substrate 10 and a plurality of repeating cells 11 on the carrier substrate 10, and each repeating cell 11 includes a plurality of subpixels 12. Each subpixel 12 includes a light emitting element 120 and a pixel circuit 121, and a pixel circuit 121 is used to drive the light emitting element 120 to emit light.

[00304] For example, the light emitting element of each subpixel includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode.

[00305] For example, as shown in FIG. 3A, the pixel circuit 121 of each sub-pixel includes a drive circuit 122, a second light emitting drive circuit 124, and a reset circuit 129.

[00306] For example, the second light emitting control circuit 124 is electrically connected to the second light emitting control signal line EM2, the second terminal of the driving circuit 122 and the first light emitting voltage supply electrode of the light emitting element 120, and is configured to achieve connection control between the driving circuit 122 and the light emitting element 120 such that it is turned on or off under the control of the second light control signal provided by the second light control signal line EM2.

[00307] The reset circuit 129 is electrically connected to the control pin of the drive circuit 122 and the first reset control signal line Rst1, and is configured to reset the control pin of the drive circuit 122 under the control of the first reset control sub-signal provided by the first reset control signal line Rst1.

[00308] For example, the second light control signal line EM2 and the first reset control signal line Rst1 are arranged in the first X direction. As shown in FIG. 4B, for the first subpixel G1, a second light control signal line EM2a connected to the second light emitting driving circuit of the first subpixel G1, and a first reset control signal line Rst1a connected to the reset circuit of the first subpixel G1 are arranged along the first X direction.

[00309] For example, as shown in FIG. 5A, the plurality of subpixels 12 include a first subpixel G1 and a second subpixel G2. For example, the color of the light emitted by the light emitting element of the first subpixel G1 is the same as the color of the light emitted by the light emitting element of the second subpixel G2, and the shape of the first light emitting voltage supply electrode of the light emitting element of the first subpixel G1 is different from that of the first light emitting voltage supply electrode of the light emitting element of the second subpixel. G2.

[00310] For example, as shown in FIG. 6B, the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel G1 on the carrier substrate at least partially overlaps with both the orthographic projection of the first reset control signal line Rst1b connected to the reset circuit of the pixel circuit of the second subpixel G2 on the carrier substrate, and with an orthographic projection of the second light emitting control signal line EM2a connected to the second light emitting control circuit of the pixel circuit of the first subpixel G1 on the carrier substrate. The orthographic projection of the first light emitting voltage supply electrode of the light emitting element of the second subpixel G2 on the carrier substrate at least partially overlaps with the orthographic projection of the second light control signal line EM2b connected to the second light emitting control circuit of the pixel circuit of the second subpixel G2 on the carrier substrate.

[00311] For example, as shown in FIG. 3A, the reset circuit 129 is also electrically connected to the first light emitting voltage supply electrode of the light emitting element and the second reset control signal line Rst2, and is configured to reset the first light emitting voltage supply electrode of the light emitting element under the control of the second reset control sub-signal provided by the second reset control signal line Rst2 ... For example, in some embodiments, the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line.

[00312] For example, as shown in FIG. 3A, the pixel circuit 121 of each subpixel further includes a data recording circuit 126, the data recording circuit 126 is electrically connected to the first terminal of the driving circuit 122 and the first scanning signal line Ga1, and the data recording circuit 126 is configured to write the data signal to the control terminal. outputting the driving circuit 122 under the control of the sweep signal provided by the first sweep signal line Ga1.

[00313] For example, in the first X direction, the first scanning signal line Ga1 is located between the second light emission control signal line EM1 and the first reset control signal line Rst1. As shown in FIG. 4B, for the first subpixel G1, the first scanning signal line Ga1a connected to the data recording circuit of the first subpixel G1 is disposed between the second light control signal line EM2a connected to the second light emitting control circuit of the first subpixel G1 and the first reset control signal line Rst1a connected with the reset circuit of the first subpixel G1.

[00314] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel G1 and the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel G2 are disposed in the first X direction.

[00315] For example, as shown in FIG. 6B, in the first X direction, a first scanning signal line Ga1b connected to the pixel circuit data recording circuit of the second subpixel G2 is disposed between the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel G1 and the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel G2.

[00316] For example, each subpixel reset circuit 129 is also electrically connected to the first power and reset signal line, and the reset circuit 129 is configured to reset the control pin of the driving circuit 1222 according to the first reset signal provided by the first power and reset signal line under control a first reset control sub-signal provided by the first reset control signal line.

[00317] For example, the reset circuit 129 of each subpixel is also electrically connected to the second power and reset signal line, and the reset circuit 129 is configured to reset the first light emitting voltage supply electrode of the light emitting element according to the second reset signal provided by the second power and reset signal line. controlling the second reset control sub-signal provided by the second reset control signal line. For example, in some embodiments, the first power and reset signal line and the second power and reset signal line are the same signal line.

[00318] For example, in the first X direction, the first power supply and reset signal line is located on the side of the first reset control signal line distantly from the second light control signal line, i. E. the first reset control signal line is located between the first power supply and reset signal line and the second light emission control signal line. As shown in FIG. 4E, for the first subpixel G1, in the first X direction, the first power and reset line Init1a connected to the reset circuit of the first subpixel G1 is located on the side of the first reset control signal line Rst1a connected to the reset circuit of the first subpixel G1 remotely from the second line EM2a light emitting control signals connected to the second light emitting control circuit of the first subpixel G1, i.e. the first reset control signal line Rst1a is located between the first power supply and reset signal line Init1a and the second light control signal line EM2a.

[00319] For example, the second light control signal line, the first reset control signal line, the first scan signal line, and the first power and reset signal line extend in the second direction, and the second direction is perpendicular to the first direction. For example, the second light control signal line, the first reset control signal line, the first scan signal line, and the first power supply and reset signal line are parallel to each other, for example, substantially parallel. As shown in FIG. 4E, for the first subpixel G1, the second light control signal line EM2a connected to the second light emitting control circuit of the first subpixel G1, the first reset control signal line Rst1a connected to the reset circuit of the first subpixel G1, the first scan signal line Ga1a connected to the data recording circuit the first subpixel G1, and the first power and reset signal line Init1a connected to the reset circuit of the first subpixel G1 extend in the second Y direction and are substantially parallel to each other.

[00320] It should be noted that in the present disclosure, “continuation” represents the routing direction of each signal line (eg, second light control signal line, first reset control signal line, first scan signal line, and first power and reset signal line) in general. Each signal line may not be a straight line in microscopic form, but may continue along the second Y direction in a wavy shape.

[00321] For example, as shown in FIG. 6B, an orthographic projection of the first light-emitting voltage supply electrode of the light emitting element of the first subpixel G1 on the carrier substrate at least partially overlaps with the orthographic projection of the first power supply and reset line Rst1b connected to the reset circuit of the pixel circuit of the second subpixel G2 on the carrier substrate.

[00322] For example, as shown in FIG. 6A, the first light-emitting voltage supply electrode of the light emitting element of the first subpixel G1 includes the sub electrode unit Ae, the first excitation electrode unit De1 and the first connecting electrode unit Ce1, the sub electrode unit Ae, the first excitation electrode unit De1, and the first connecting electrode unit Ce1 are electrically connected interconnected and arranged in the first X direction. The first light-emitting voltage supply electrode of the light-emitting element of the second subpixel G2 includes a second excitation electrode unit De2 and a second excitation electrode unit Ce2, and the second excitation electrode unit De2 and the second connection electrode unit Ce2 are electrically connected to each other and are placed along the first X direction.

[00323] For example, in the first X direction, the first electrode connection unit Ce1 and the auxiliary electrode unit Ae are located on the side of the first excitation electrode unit De1 remotely from the second excitation electrode unit De2, the first electrode connection unit Ce1 is located between the auxiliary electrode Ae and the first excitation electrode the unit De1, and the second electrode connection unit Ce2 is located on the side of the second excitation electrode unit De2 remotely from the first excitation electrode unit De1.

[00324] For example, as shown in FIG. 6B, the orthographic projection of the first excitation electrode unit De1 on the carrier substrate at least partially overlaps with both the orthographic projection of the first reset control signal line Rst1b connected to the reset circuit of the pixel circuit of the second subpixel G2 on the carrier substrate and the orthographic projection of the first line Init1b of the power supply and reset signals connected to the reset circuit of the pixel circuit of the second subpixel G2 on the carrier substrate. The orthographic projection of the first connecting electrode unit Ce1 on the carrier substrate at least partially overlaps with the orthographic projection of the second light control signal line EM1a connected to the second light emitting control circuit of the pixel circuit of the first subpixel G1 on the carrier substrate. In the first direction, the sub electrode unit Ae is located on the side of the second light control signal line EM1a connected to the second light emitting control circuit of the pixel circuit of the first subpixel G1 remotely from the first light emitting voltage supply electrode of the light emitting element of the second subpixel G2.

[00325] For example, as shown in FIG. 6B, the orthographic projection of the second connecting electrode unit Ce2 on the carrier substrate at least partially overlaps with the orthographic projection of the second light control signal line EM1b connected to the second light emitting control circuit of the pixel circuit of the second subpixel G2 on the carrier substrate, and in the first direction X, the second excitation electrode unit De2 is disposed between the second light control signal line EM1b connected to the second light emitting control circuit of the pixel circuit of the second subpixel G2 and the first scan signal line Ga1b connected to the data recording circuit of the pixel circuit of the second subpixel G2.

[00326] An embodiment of the present disclosure also provides a display panel. FIG. 7 is a partial block diagram of a display panel provided by some embodiments of the present disclosure. For example, as shown in FIG. 7, the display panel 700 includes a display substrate 100 provided by any of the above embodiments.

[00327] For example, as shown in FIG. 7, a plurality of repeating cells 11 are arranged along the second Y direction to form a plurality of repeating cell groups. FIG. 7 shows two groups of repeating cells, and the two groups of repeating cells, respectively, represent the Pth group of repeating cells and the (P + 1) th group of repeating cells, and the Pth group of repeating cells and the (P + 1) th a repeating cell group are two adjacent repeating cell groups, for example, P is a positive integer greater than or equal to a cell. A plurality of groups of repeating cells are arranged along the first X direction. That is, a plurality of repeating cells 11 in the display substrate 100 are arranged in a matrix along the first X direction and the second Y direction.

[00328] It should be noted that with reference to the above FIGS. 5A and 6E, the Pth repeating cell group is located in the first row, and the (P + 1) th repeating cell group is located in the second row. FIG. 7 does not show the light emitting element connection electrode units of the respective subpixels.

[00329] For example, the continuing line for the line connecting the center of the first subpixel G1 and the center of the second subpixel G2 of the repeating cell in the Pth repetitive cell group does not coincide with the continuing line for the line connecting the center of the first subpixel G1 and the center of the second subpixel G2 of the repeating cell in the (P + 1) th group of repeating cells. For example, an extended line for a line connecting the center of the first subpixel G1 and the center of the second subpixel G2 of a repeating cell in a P-th repeating cell group passes through the center of the interval between adjacent two repeating cells in a (P + 1) th repeating cell group, similarly, the continuing line for the line connecting the center of the first subpixel G1 and the center of the second subpixel G2 of the repeating cell in the (P + 1) th repeating cell group passes through the center of the interval between adjacent two repeating cells in the Pth repeating cell group.

[00330] For example, the display panel 700 may be a liquid crystal display panel or an organic light emitting diode (OLED) display panel or the like. For example, in the case where the display panel 700 is a liquid crystal display panel, the display substrate 100 may be an array substrate or a color film substrate. In the case where the display panel 700 is an organic light emitting diode display panel, the display substrate 100 may be an array substrate.

[00331] For example, the display panel 700 may be a rectangular panel, a circular panel, an elliptical panel, a polygonal panel, or the like. In addition, the display panel 700 may be not only a flat panel, but also a curved panel or even a spherical panel.

[00332] For example, the display panel 700 may also have a touch function, i. E. the display panel 600 may be a touchscreen display panel.

[00333] For example, the display panel 700 can be applied to any product or component with a display function, such as a mobile phone, tablet computer, television set, display, laptop, digital photo frame, navigator, and so on.

[00334] An embodiment of the present disclosure also provides a display device, FIG. 8A is a schematic block diagram of a display device provided by some embodiments of the present disclosure, and FIG. 8B is a schematic structural diagram of a display device provided by some embodiments of the present disclosure.

[00335] For example, as shown in FIG. 8A, the display device 800 provided by an embodiment of the present disclosure includes a display panel 801, and the display panel 801 includes a display substrate 802, the display panel 801 is a display panel 700 described in any of the above embodiments, and a substrate 802 display is a display substrate 100 described in any of the above embodiments.

[00336] For example, as shown in FIG. 8A, the display device 800 may further include a drive chip 803, and the drive chip 803 is electrically connected to the display panel 801.

[00337] For example, the driver chip 803 is located on the side of the first subpixel G1 in each repeating cell 11 distantly from the second subpixel G2. As shown in FIG. 8B, the first subpixel G1 and the second subpixel G2 in each repeating cell 11 on the display substrate 802 are disposed along the first X direction, in the first X direction, the driver chip 803 is located on the side of the first subpixel G1 in each repeating cell 11 distantly from the second subpixel G2. In other words, in the first X direction, the distance between the first subpixel G1 and the drive chip 803 is less than the distance between the second subpixel G2 and the drive chip 803. For example, in the example as shown in FIG. 8B, the first sub-pixel G1 is closer to the top side of the display panel 801 than the second sub-pixel G2, so that the driver chip 803 can be located on the top side of the display panel 801.

[00338] For example, the driver chip 803 may be a semiconductor chip and may include a data driver. A data driver in the driver chip 803 is used to drive a plurality of data lines in the display panel 801. For example, the data control signal generator can provide data signals to a plurality of data lines.

[00339] For example, display device 800 can be any product or component having a display function such as a mobile phone, tablet computer, television set, display, laptop, digital photo frame, navigator, and so on.

[00340] It should be noted that other components of the display device 800 (eg, a control device, an image data encoding / decoding device, a gate driver, a timing controller, a timing circuit, etc.) are to be understood by those skilled in the art, and are not described in detail in this document, nor should they be construed as limiting the present disclosure.

[00341] An embodiment of the present disclosure also provides a preparation method for preparing a display substrate according to any of the above embodiments, and FIG. 9 is a flowchart of a preparation method for preparing a display substrate provided by an embodiment of the present disclosure.

[00342] For example, as shown in FIG. 9, a method for preparing a display substrate may include:

[00343] S10. Providing a carrier substrate.

[00344] S11. Formation of multiple repeating cells on the carrier substrate.

[00345] For example, in step S11, each repeating cell includes a plurality of subpixels, each subpixel includes a pixel circuit and a light emitting element, the light emitting element includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first a light emitting voltage supply electrode and a second light emitting voltage supply electrode, a plurality of subpixels include a first subpixel and a second subpixel, the color of the light emitted by the light emitting element of the first subpixel is the same as the color of the light emitted by the light emitting element of the second subpixel, the shape of the first light emitting voltage electrode the light emitting element of the first subpixel differs from the shape of the first light emitting voltage supply electrode of the light emitting element of the second subpixel, an orthographic projection of the first light emitting voltage supply electrode of the first subpixel light emitting element on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate, and the orthographic projection of the first light emitting voltage supply electrode of the second subpixel light emitting element on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the second subpixel on the carrier substrate.

[00346] For example, in step S11, in a case where the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel is formed, the first excitation electrode unit and the sub-electrode unit are formed by one patterning process, and the orthographic projection of the sub-electrode unit on the carrier substrate is at least partially overlaps with the orthographic projection of the control pin of the driving circuit of the first subpixel pixel circuit on the carrier substrate, for example, the orthographic projection of the control pin of the driving circuit of the first subpixel pixel circuit on the carrier substrate is located within the orthographic projection of the auxiliary electrode unit on the carrier substrate. For example, in an embodiment of the present disclosure, one patterning process may include photolithographic coating, exposure, etching and development, photoresist removal, and other operations.

[00347] Note that in a case where the first light-emitting voltage supply electrode includes the first connecting electrode unit, the first connecting electrode unit may be formed while the first excitation electrode unit and the sub electrode unit are formed.

[00348] For example, in step S11, if the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel is formed, the second driving electrode unit is formed, and the orthographic projection of the second driving electrode unit on the carrier substrate at least partially overlaps the orthographic projection of the driving of the driving circuit terminal of the second subpixel pixel circuit on the carrier substrate, for example, an orthographic projection of the driving terminal of the driving circuit of the second subpixel pixel circuit on the carrier substrate is located within the orthographic projection of the second driving electrode unit on the carrier substrate.

[00349] It should be noted that in a case where the second light-emitting voltage supply electrode includes a second connecting electrode unit, the second excitation electrode unit and the second connecting electrode unit can be formed by a single patterning process.

[00350] It should be noted that for a detailed description regarding a repeating cell, reference should be made to the relevant description in the above embodiment of the display substrate, and repetition is not given here.

[00351] For this disclosure, the following aspects should be explained:

[00352] (1) The drawings of the embodiments of the present disclosure mean only structures associated with the embodiments of the present disclosure, and other structures may mean a general structure.

[00353] (2) For clarity, in the drawings used to describe embodiments of the present disclosure, thicknesses and sizes of layers or structures are exaggerated. It should be understood that in the event that an element such as a layer, film, patch or substrate is referred to as being "on" or "below" another element, the element can be "directly" "on" or "below" another element, or an intermediate element may be provided between the element and another element.

[00354] (3) In the absence of conflict, embodiments of the present disclosure and features in the embodiments may be combined with each other to obtain new embodiments.

[00355] The above are merely exemplary embodiments of the present disclosure, and are not intended to define the scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims (132)

1. A display substrate comprising a carrier substrate and a plurality of repeating cells on the carrier substrate, wherein each of the plurality of repeating cells contains a plurality of subpixels, and each of the plurality of subpixels comprises a light emitting element and a pixel circuit for driving the light emitting element to emit light; the pixel circuit contains a driving circuit; the light emitting element includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode; the plurality of subpixels comprise a first subpixel and a second subpixel, the color of the light emitted by the light emitting element of the first subpixel is the same as the color of the light emitted by the light emitting element of the second subpixel, and the shape of the first light emitting voltage supply electrode of the light emitting element of the first subpixel is different from the shape of the first electrode of the light emitting voltage a light emitting element of the second subpixel; an orthographic projection of the first light-emitting voltage supply electrode of the light emitting element of the first subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate; and the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the second subpixel pixel circuit on the carrier substrate. 2. The display substrate of claim 1, wherein the orthographic projection area of the first light emitting voltage supply electrode of the light emitting element of the first subpixel on the carrier substrate is different from the orthographic projection area of the first light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate. 3. The display substrate according to claim 1 or 2, wherein a region of the overlapping portion between an orthographic projection of the driving terminal of the driving circuit of the pixel circuit of the first subpixel on the carrier substrate and the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel on the carrier substrate constitutes the first region, and a region of the overlapping portion between an orthographic projection of the control terminal of the driving circuit of the pixel circuit of the second subpixel on the carrier substrate and the orthographic projection of the first light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate constitutes a second region; and the ratio of the first area to the second area satisfies the following relationship: Amin≤A1 / A2≤Amax, where A1 represents the first region, A2 represents the second region, Amin represents the minimum threshold value of the ratio and is 90%, and Amax represents the maximum threshold value of the ratio and is 110%. 4. The display substrate according to any one of claims 1 to 3, in which the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the first subpixel on the carrier substrate is within the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel on the carrier substrate; and the orthographic projection of the control terminal of the driving circuit of the second subpixel pixel circuit on the carrier substrate is within the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel on the carrier substrate. 5. The display substrate according to any one of claims 1 to 4, wherein the orthographic projection of the light emitting layer of the first subpixel light emitting element on the carrier substrate is continuous with the orthographic projection of the light emitting layer of the second subpixel light emitting element on the carrier substrate. 6. The display substrate of any one of claims 1 to 5, wherein the pixel circuit further comprises a first light emitting drive circuit and a second light emitting drive circuit, the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current for driving the light emitting element to emit light; the first light emitting control circuit is connected to the first terminal of the driving circuit and the first voltage terminal and is configured to turn on or off the connection between the driving circuit and the first voltage terminal; and the second light emitting control circuit is electrically connected to the second terminal of the driving circuit and the first light-emitting voltage supply electrode of the light-emitting element, and is configured to turn on or off the connection between the driving circuit and the light-emitting element. 7. The display substrate of claim 6, wherein the first subpixel pixel circuit further comprises a first parasitic circuit, and the second subpixel pixel circuit further comprises a second parasitic circuit; the first parasitic circuit is electrically connected to the control terminal of the driving circuit of the first subpixel pixel circuit and the first electrode for supplying the light emitting voltage of the light emitting element of the first subpixel, and the first parasitic circuit is configured to control the voltage of the control terminal of the driving circuit of the first subpixel pixel circuit based on the voltage of the first supply electrode a light emitting voltage of the light emitting element of the first subpixel; and the second parasitic circuit is electrically connected to the control terminal of the driving circuit of the second subpixel pixel circuit and the first electrode for supplying the light emitting voltage of the light emitting element of the second subpixel, and the second parasitic circuit is configured to control the voltage of the control terminal of the driving circuit of the second subpixel pixel circuit based on the voltage of the first supply electrode the light-emitting voltage of the light-emitting element of the second sub-pixel. 8. The display substrate of claim 7, wherein the first parasitic circuit comprises a first capacitor, and the first capacitor comprises a first electrode and a second electrode; the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel comprises an auxiliary electrode unit, and the orthographic projection of the auxiliary electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate; and the sub-electrode unit serves as the first electrode of the first capacitor, and the control terminal of the driving circuit of the first subpixel is multiplexed as the second electrode of the first capacitor. 9. The display substrate of claim 8, wherein the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel further comprises a first excitation electrode unit, and the first excitation electrode unit is electrically connected to the sub-electrode unit, and an orthographic projection of the first exciting electrode unit on the carrier substrate, an orthographic projection of the light emitting layer of the first subpixel light emitting element on the carrier substrate, and an orthographic projection of the second light emitting voltage supply electrode of the first subpixel light emitting element on the carrier substrate at least partially overlap. 10. The display substrate of claim 9, wherein the second parasitic circuit comprises a second capacitor and the second capacitor comprises a first electrode and a second electrode; the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel comprises a second excitation electrode unit, and an orthographic projection of the second excitation electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the second subpixel pixel circuit on the carrier substrate; an orthographic projection of the second exciting electrode unit on the carrier substrate, an orthographic projection of the light emitting layer of the second subpixel light emitting element on the carrier substrate, and an orthographic projection of the second light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate at least partially overlap; and the second driving electrode unit is multiplexed as the first electrode of the second capacitor, and the control terminal of the driving circuit of the second subpixel is multiplexed as the second electrode of the second capacitor. 11. The display substrate of claim 10, wherein the shape of the first excitation electrode unit is the same as the shape of the second excitation electrode unit and the orthographic area of the first excitation electrode unit on the carrier substrate is the same as the orthographic area of the second excitation electrode unit on the support substrate. 12. The display substrate of claim 10 or 11, wherein in each repeating cell, the first sub-pixel and the second sub-pixel are disposed in the first direction, the first direction is parallel to the surface of the carrier substrate, and in the first direction, the sub-electrode unit is disposed on the side of the first excitation electrode unit distantly from the light emitting element of the second sub-pixel. 13. The display substrate according to any one of claims 8 to 12, wherein the orthographic projection of the auxiliary electrode unit on the carrier substrate does not overlap with the orthographic projection of the light emitting layer of the light emitting element of the first subpixel on the carrier substrate. 14. The display substrate of claim 12, wherein the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel further comprises a first connecting electrode unit, in the first direction, the first connecting electrode unit is located on the side of the first excitation electrode unit distantly from the light emitting element of the second subpixel, and the first connecting electrode unit is located between the auxiliary electrode unit and the first excitation electrode unit and is electrically connected to both the auxiliary electrode unit and the first excitation electrode block. 15. The display substrate of claim 14 further comprising an intermediate layer, wherein, in a direction perpendicular to the surface of the carrier substrate, the pixel circuit is disposed between the intermediate layer and the carrier substrate, the light emitting element is located on the side of the intermediate layer remote from the carrier substrate; and the intermediate layer contains a first via, and the first connecting electrode unit extends to the first via and is electrically connected to the first subpixel pixel circuit through the first via. 16. The display substrate of claim 15, wherein the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel further comprises a second connecting electrode unit, and the second connecting electrode unit is electrically connected to the second drive electrode unit, and in the first direction, the second connecting electrode unit is located on the side of the second excitation electrode unit distantly from the light emitting element of the first subpixel. 17. The display substrate of claim 16, wherein the intermediate layer comprises a second via and the second connecting electrode unit extends to the second via and is electrically connected to the second sub-pixel pixel circuit through the second via. 18. The display substrate according to claim 16 or 17, wherein the first connecting electrode unit is electrically connected to the second light emitting control circuit of the first subpixel pixel circuit through the first via, and the second connecting electrode unit is electrically connected to the second light emitting control circuit of the second subpixel pixel circuit through second via. 19. A display substrate according to any one of claims 16 to 18, wherein the pixel circuit comprises an active semiconductor layer, an electrode gate metal layer and a source-drain electrode metal layer, in a direction perpendicular to the carrier substrate, the active semiconductor layer is located between the carrier substrate and an electrode metal gate layer, and the electrode metal gate layer is disposed between the active semiconductor layer and the electrode source-drain metal layer; the first connecting electrode unit extends to the source-drain electrode metal layer of the pixel circuit through the first via; and the second connecting electrode unit extends to the source-drain electrode metal layer of the pixel circuit through the second via. 20. The display substrate according to any one of claims 16 to 19, wherein the plurality of subpixels further comprise a third subpixel and a fourth subpixel, wherein in each repeating cell, the third subpixel and the fourth subpixel are arranged along the second direction, and in the second direction, the first subpixel and the second subpixel are located between the third subpixel and the fourth subpixel; and the second direction is parallel to the surface of the carrier substrate, and the first direction is perpendicular to the second direction. 21. The display substrate of claim 20, wherein the first light-emitting voltage supply electrode of the light-emitting element of the third subpixel comprises a third drive electrode unit and a third electrode connection unit, the third drive electrode unit and the third electrode connection unit are electrically connected to each other, and the first voltage supply electrode light emitting of the light emitting element of the fourth subpixel comprises a fourth driving electrode unit and a fourth connecting electrode unit, the fourth driving electrode unit and the fourth connecting electrode unit are electrically connected to each other; and the intermediate layer contains a third via and a fourth via, the third connecting electrode block extends to the third via and is electrically connected to the pixel circuit of the third sub-pixel via the third via, and the fourth connecting electrode block extends to the fourth via and is electrically connected to the pixel circuit of the fourth subpixel through the fourth via. 22. The display substrate of claim 21, wherein in each repeating cell: in the first direction, the third connection electrode unit is located on the third excitation electrode unit side distantly from the auxiliary electrode unit, and in the second direction, the third connection electrode unit is located on the third excitation electrode unit side adjacent to the fourth excitation electrode unit; and in the first direction, the fourth connecting electrode unit is located on the fourth excitation electrode unit side distantly from the auxiliary electrode unit, and in the second direction, the fourth excitation electrode unit is located on the fourth excitation electrode unit side adjacent to the third excitation electrode unit. 23. The display substrate according to claim 21 or 22, wherein the third connecting electrode unit is electrically connected to the second light emitting control circuit of the third subpixel pixel circuit through the third via, and the fourth connecting electrode unit is electrically connected to the second light emitting control circuit of the fourth subpixel pixel circuit through the fourth via. 24. The display substrate according to any one of claims 21 to 23, in which a plurality of repeating cells are arranged in a second direction to form a plurality of repeating cell groups, and a plurality of repeating cell groups are arranged in a first direction; in the first direction, the first connecting electrode unit, the second connecting electrode unit, the third connecting electrode unit, and the fourth connecting electrode unit are disposed between two adjacent groups of repeating cells; and in the first direction, at least a portion of the auxiliary electrode unit is located on the side of the auxiliary electrode unit distantly from the first excitation electrode unit and is located between two adjacent repeating cells in the repeating cell group adjacent to the repeating cell group in which the auxiliary electrode unit is located. 25. The display substrate according to any one of claims 20 to 24, wherein the first subpixel and the second subpixel are green subpixels, the third subpixel is a red subpixel, and the fourth subpixel is a blue subpixel. 26. The display substrate according to any one of claims 6 to 25, in which the pixel circuit further comprises a data recording circuit, a data storage circuit, a threshold compensation circuit and a reset circuit; the data recording circuit is electrically connected to the first terminal of the driving circuit and configured to write the data signal to the data storage circuit under the control of the scanning signal; the data storage circuit is electrically connected to the control terminal of the driving circuit and the first voltage terminal and is configured to store the data signal; the threshold compensation circuit is electrically connected to the control terminal of the driving circuit and the second terminal of the driving circuit, and is configured to perform the threshold compensation for the driving circuit; and the reset circuit is electrically connected to the driving circuit control terminal and the first light emitting voltage supply electrode of the light emitting element, and is configured to reset the driving circuit control terminal and the first light emitting voltage supply electrode of the light emitting element under the control of the reset control signal. 27. The display substrate of claim 26, wherein the driving circuit comprises a driving transistor, a driving circuit control terminal comprises a gate electrode of a driving transistor, a first driving circuit terminal comprises a first driving transistor electrode, a second driving circuit terminal comprises a second driving transistor electrode; the data recording circuit contains a data recording transistor, the data storage circuit contains a third capacitor, the threshold compensation circuit contains a threshold compensation transistor, the reset circuit contains a first reset transistor and a second reset transistor, the first light emitting control circuit contains a first light emitting control transistor, the second light emitting control circuit contains a second a light emitting control transistor, the reset control signal comprises a first reset control sub-signal and a second reset control sub-signal; the first electrode of the data recording transistor is electrically connected to the first electrode of the drive transistor, the second electrode of the data recording transistor is configured to receive a data signal, and a gate electrode of the data recording transistor is configured to receive a scan signal; the first electrode of the third capacitor is electrically connected to the first voltage terminal, and the second electrode of the third capacitor is electrically connected to the gate electrode of the driving transistor; the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the exciting transistor, the second electrode of the threshold compensation transistor is electrically connected to the gate electrode of the exciting transistor, and the gate electrode of the threshold compensation transistor is configured to receive the compensation control signal; the first electrode of the first reset transistor is configured to receive the first reset signal, the second electrode of the first reset transistor is electrically connected to the gate electrode of the driving transistor, and the gate electrode of the first reset transistor is configured to receive the first reset control sub-signal; the first electrode of the second reset transistor is configured to receive the second reset signal, the second electrode of the second reset transistor is electrically connected to the first light emitting voltage supply electrode of the light emitting element, and the gate electrode of the second reset transistor is configured to receive the second reset control sub-signal; the first electrode of the first light emitting control transistor is electrically connected to the first voltage terminal, the second electrode of the first light emitting control transistor is electrically connected to the first electrode of the driving transistor, the gate electrode of the first light emitting control transistor is configured to receive the first light emitting control signal; and the first electrode of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the second light emitting control transistor is electrically connected to the first light emitting voltage supply electrode of the light emitting element, and the gate electrode of the second light emitting control transistor is configured to receive the second light emitting control signal. 28. A display panel comprising a display substrate according to any one of claims 1 to 27. 29. A display device comprising a display panel according to claim 28. 30. A display device according to claim 29, further comprising: a drive chip, wherein the driver chip is electrically connected to the display panel, and the driver chip is disposed on the first sub-pixel side in each repeating cell at a distance from the second sub-pixel. 31. The display device of claim 29, wherein in each repeating cell, the orthographic projection area of the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel on the carrier substrate is larger than the orthographic projection area of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel on the carrier substrate. 32. A preparation method for preparing a display substrate according to any one of claims 1 to 27, comprising the steps of: provide a carrier substrate; and forming a plurality of repeating cells on the carrier substrate, each of the plurality of repeating cells comprising a plurality of subpixels, each of the plurality of subpixels comprising a pixel circuit and a light-emitting element, the light-emitting element comprises a first electrode for applying a light-emitting voltage, a second electrode for applying a voltage of light, and a light-emitting layer between the first electrode the light emitting voltage and the second light emitting voltage supply electrode, the plurality of subpixels include the first subpixel and the second subpixel, the color of the light emitted by the light emitting element of the first subpixel is the same as the color of the light emitted by the light emitting element of the second subpixel, the shape of the first light emitting voltage supply electrode of the light emitting element of the first subpixel differs from the shape of the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel, the orthographic projection of the first electric The light emitting voltage supply electrode of the light emitting element of the first subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the first subpixel pixel circuit on the carrier substrate, and the orthographic projection of the first light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate, at least partially overlaps with the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the second subpixel on the carrier substrate. 33. A display substrate comprising a carrier substrate and a plurality of repeating cells on the carrier substrate, wherein each of the plurality of repeating cells contains a plurality of subpixels, each of the plurality of subpixels comprises a light emitting element and a pixel circuit for driving the light emitting element to emit light, the pixel circuit contains a drive circuit, and the light emitting element comprises a first electrode for supplying a light emitting voltage, a second electrode for supplying a voltage of light and a light emitting layer between the first light-emitting voltage supply electrode and the second light-emitting voltage supply electrode; driving circuits of the plurality of subpixels are arranged in the matrix on the carrier substrate; the plurality of subpixels include a first subpixel and a second subpixel, and the color of light emitted by the light emitting element of the first subpixel is the same as the color of light emitted by the light emitting element of the second subpixel; the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel comprises an auxiliary electrode unit, a first excitation electrode unit and a first connecting electrode unit, and the first excitation electrode unit, the auxiliary electrode unit and the first connecting electrode unit are electrically connected to each other; the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel includes a second excitation electrode unit and a second excitation electrode unit, and the second excitation electrode unit is electrically connected to the second excitation electrode unit; the sub-electrode unit is disposed on the control terminal side of the first subpixel pixel circuit driving circuit at a distance from the carrier substrate; and the second driving electrode unit is disposed on the control terminal side of the driving circuit of the second sub-pixel pixel circuit at a distance from the carrier substrate. 34. The display substrate of claim 33, wherein the shape of the first excitation electrode unit is different from that of the auxiliary electrode unit, the shape of the first excitation electrode unit is the same as that of the second excitation electrode unit, and the orthographic projection area of the first excitation electrode unit on the carrier substrate is the same an orthographic projection of the second exciting electrode unit on the carrier substrate. 35. The display substrate of claim 33 or 34, wherein the shape of the first connecting electrode unit is the same as that of the second connecting electrode unit and the orthographic area of the first connecting electrode unit on the carrier substrate is the same as the orthographic area of the second connecting electrode unit on the carrier substrate. 36. The display substrate according to any one of claims 33 to 35, wherein the driving terminal of the first subpixel pixel circuit driving circuit and the driving terminal of the second subpixel pixel circuit driving circuit are disposed in the first direction, and in the first direction, the first driving electrode unit is disposed on the control terminal side of the driving circuit of the first subpixel pixel circuit adjacent to the control terminal of the driving circuit of the second subpixel pixel circuit. 37. The display substrate of claim 36, wherein in the first direction, the first driving electrode unit is disposed between the driving terminal of the first subpixel pixel circuit driving circuit and the driving terminal of the second subpixel pixel circuit driving circuit. 38. The display substrate of claim 37, wherein in the first direction, the first connecting electrode unit is disposed on the side of the first excitation electrode unit remotely from the control terminal of the driving circuit of the second subpixel pixel circuit. 39. The display substrate of claim 38, wherein, in the first direction, the first connecting electrode unit is disposed between a control terminal of the first subpixel pixel circuit driving circuit and a control terminal of the second subpixel pixel circuit driving circuit. 40. The display substrate according to claim 38 or 39, wherein the first connecting electrode unit is disposed between the first excitation electrode unit and the auxiliary electrode unit in the first direction. 41. The display substrate according to any one of claims 36 to 40, wherein in the first direction, the second connecting electrode unit is disposed on the control terminal side of the driving circuit of the second subpixel pixel circuit distantly from the driving terminal of the driving circuit of the first subpixel pixel circuit, and the second excitation electrode unit is disposed between the second connection electrode unit and the first excitation electrode unit. 42. The display substrate according to any one of claims 33 to 41, in which the distance between the center of the control terminal of the driving circuit of the first subpixel pixel circuit and the center of the first driving electrode unit is greater than the distance between the center of the control terminal of the driving circuit of the second subpixel pixel circuit and the center of the second driving circuit. electrode block. 43. A display substrate comprising a carrier substrate and a plurality of repeating cells on the carrier substrate, wherein each of the plurality of repeating cells contains a plurality of subpixels, each of the plurality of subpixels comprises a light emitting element and a pixel circuit for driving the light emitting element to emit light, the light emitting element includes a first light emitting voltage supply electrode, a second light emitting voltage supply electrode, and a light emitting layer between the first light emitting voltage supply electrode and the second light emitting voltage supply electrode, the pixel circuit includes a drive circuit, a second light-emitting drive circuit and a reset circuit, the second light emitting control circuit is electrically connected to the second light emitting control signal line, the second drive circuit terminal and the first light emitting voltage supply electrode of the light emitting element, and is configured, under the control of the second light emitting control signal provided by the second light emitting control signal line, to turn the connection on or off between the driving circuit and the light-emitting element, the reset circuit is electrically connected to the driving circuit control terminal and the first reset control signal line, and is configured to reset the driving circuit control terminal under the control of the first reset control sub-signal provided by the first reset control signal line, a second line of light control signals and a first line of reset control signals are disposed along the first direction, multiple subpixels contain a first subpixel and a second subpixel, the orthographic projection of the first electrode for supplying the light-emitting voltage of the light-emitting element of the first subpixel on the carrier substrate at least partially overlaps both with the orthographic projection of the first line of reset control signals connected to the reset circuit of the pixel circuit of the second subpixel on the carrier substrate, and with the orthographic projection of the second line light-emitting control signals connected to the second light-emitting control circuit of the pixel circuit of the first sub-pixel on the carrier substrate, and an orthographic projection of the first light emitting voltage supply electrode of the light emitting element of the second subpixel on the carrier substrate at least partially overlaps with the orthographic projection of the second line of light control signals connected to the second light emitting control circuit of the second subpixel pixel circuit on the carrier substrate. 44. The display substrate of claim 43, wherein the pixel circuit further comprises a data recording circuit, the data recording circuit is electrically connected to the first terminal of the driving circuit and the first scanning signal line, and is configured to write the data signal to the control terminal of the driving circuit under the control of the scanning signal provided by the first scanning signal line, in the first direction, the first scan signal line is located between the second light emission control signal line and the first reset control signal line, the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel and the first light-emitting voltage supply electrode of the light-emitting element of the second sub-pixel are disposed along the first direction, and in the first direction, a first scanning signal line connected to the data recording circuit of the second sub-pixel pixel circuit is disposed between the first light-emitting voltage supply electrode of the light-emitting element of the first sub-pixel and the first light-emitting voltage supply electrode of the light-emitting element of the second sub-pixel. 45. The display substrate of claim 43 or 44, wherein the reset circuit is further electrically connected to the first power supply and reset signal line, the reset circuit is configured to reset the drive circuit control terminal according to the first reset signal provided by the first power supply and reset signal line under the control of the first reset control sub-signal provided by the first reset control signal line, in the first direction, the first power supply and reset signal line is located on the side of the first reset control signal line distantly from the second light emission control signal line, and the orthographic projection of the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel on the carrier substrate additionally at least partially overlaps with the orthographic projection of the first power and reset signal line connected to the second subpixel pixel circuit reset circuit on the carrier substrate. 46. The display substrate of claim 45, wherein all of the second light control signal line, the first reset control signal line, the first scan signal line, and the first power and reset signal line extend in a second direction and the second direction is perpendicular to the first direction. 47. The display substrate of claim 45 or 46, wherein the second light control signal line, the first reset control signal line, the first scan signal line, and the first power and reset signal line are in parallel with each other. 48. A display substrate according to any one of claims 45 to 47, wherein the first light-emitting voltage supply electrode of the light-emitting element of the first subpixel comprises an auxiliary electrode unit, a first excitation electrode unit and a first electrode connection unit, a first excitation electrode unit, an auxiliary electrode unit and a first connection the electrode unit is electrically connected to each other and placed in the first direction, the first light-emitting voltage supply electrode of the light-emitting element of the second subpixel comprises a second excitation electrode unit and a second electrode connection unit, the second excitation electrode unit and the second electrode connection unit are electrically connected and disposed in the first direction, in the first direction, both of the first connecting electrode unit and the auxiliary electrode unit are located on the side of the first excitation electrode unit distantly from the second excitation electrode unit, the first connecting electrode unit is located between the auxiliary electrode unit and the first excitation electrode unit, the second connecting electrode unit is located on the side of the second an excitation electrode unit remotely from the first excitation electrode unit, the orthographic projection of the first exciting electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the first reset control signal line connected to the reset circuit of the second subpixel pixel circuit on the carrier substrate, and with the orthographic projection of the first power and reset signal line connected to a reset circuit for the pixel circuit of the second sub-pixel on the carrier substrate, an orthographic projection of the first connecting electrode unit on the carrier substrate at least partially overlaps with an orthographic projection of a second light emitting control signal line coupled to a second light emitting control circuit of a first subpixel pixel circuit on a carrier substrate, in the first direction, the auxiliary electrode unit is disposed on the side of the second light emitting control signal line connected to the second light emitting control circuit of the pixel circuit of the first subpixel remotely from the first light emitting voltage supply electrode of the light emitting element of the second subpixel, the orthographic projection of the second connecting electrode unit on the carrier substrate at least partially overlaps with the orthographic projection of the second light emission control signal line connected to the second light emitting control circuit of the second subpixel pixel circuit on the carrier substrate, and in the first direction, a second driving electrode unit is disposed between a second light-emitting control signal line connected to the second light-emitting control circuit of the second sub-pixel pixel circuit and a first scan signal line connected to the second sub-pixel pixel circuit data recording circuit. 49. The display substrate according to any one of claims 43 to 48, in which the color of the light emitted by the light emitting element of the first subpixel is the same as the color of the light emitted by the light emitting element of the second subpixel, and the shape of the first light emitting voltage supply electrode of the light emitting element of the first subpixel is different from shapes of the first light-emitting voltage supply electrode of the light-emitting element of the second sub-pixel.

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